Module aarch64

1.27.0 · Source
Available on AArch64 or target_arch="arm64ec" only.
Expand description

Platform-specific intrinsics for the aarch64 platform.

See the module documentation for more details.

Structs§

float64x1_t
ARM-specific 64-bit wide vector of one packed f64.
float64x1x2_t
ARM-specific type containing two float64x1_t vectors.
float64x1x3_t
ARM-specific type containing three float64x1_t vectors.
float64x1x4_t
ARM-specific type containing four float64x1_t vectors.
float64x2_t
ARM-specific 128-bit wide vector of two packed f64.
float64x2x2_t
ARM-specific type containing two float64x2_t vectors.
float64x2x3_t
ARM-specific type containing three float64x2_t vectors.
float64x2x4_t
ARM-specific type containing four float64x2_t vectors.
SYExperimental
Full system is the required shareability domain, reads and writes are the required access types
float32x2_tExperimental
ARM-specific 64-bit wide vector of two packed f32.
float32x2x2_tExperimental
ARM-specific type containing two float32x2_t vectors.
float32x2x3_tExperimental
ARM-specific type containing three float32x2_t vectors.
float32x2x4_tExperimental
ARM-specific type containing four float32x2_t vectors.
float32x4_tExperimental
ARM-specific 128-bit wide vector of four packed f32.
float32x4x2_tExperimental
ARM-specific type containing two float32x4_t vectors.
float32x4x3_tExperimental
ARM-specific type containing three float32x4_t vectors.
float32x4x4_tExperimental
ARM-specific type containing four float32x4_t vectors.
int8x8_tExperimental
ARM-specific 64-bit wide vector of eight packed i8.
int8x8x2_tExperimental
ARM-specific type containing two int8x8_t vectors.
int8x8x3_tExperimental
ARM-specific type containing three int8x8_t vectors.
int8x8x4_tExperimental
ARM-specific type containing four int8x8_t vectors.
int8x16_tExperimental
ARM-specific 128-bit wide vector of sixteen packed i8.
int8x16x2_tExperimental
ARM-specific type containing two int8x16_t vectors.
int8x16x3_tExperimental
ARM-specific type containing three int8x16_t vectors.
int8x16x4_tExperimental
ARM-specific type containing four int8x16_t vectors.
int16x4_tExperimental
ARM-specific 64-bit wide vector of four packed i16.
int16x4x2_tExperimental
ARM-specific type containing two int16x4_t vectors.
int16x4x3_tExperimental
ARM-specific type containing three int16x4_t vectors.
int16x4x4_tExperimental
ARM-specific type containing four int16x4_t vectors.
int16x8_tExperimental
ARM-specific 128-bit wide vector of eight packed i16.
int16x8x2_tExperimental
ARM-specific type containing two int16x8_t vectors.
int16x8x3_tExperimental
ARM-specific type containing three int16x8_t vectors.
int16x8x4_tExperimental
ARM-specific type containing four int16x8_t vectors.
int32x2_tExperimental
ARM-specific 64-bit wide vector of two packed i32.
int32x2x2_tExperimental
ARM-specific type containing two int32x2_t vectors.
int32x2x3_tExperimental
ARM-specific type containing three int32x2_t vectors.
int32x2x4_tExperimental
ARM-specific type containing four int32x2_t vectors.
int32x4_tExperimental
ARM-specific 128-bit wide vector of four packed i32.
int32x4x2_tExperimental
ARM-specific type containing two int32x4_t vectors.
int32x4x3_tExperimental
ARM-specific type containing three int32x4_t vectors.
int32x4x4_tExperimental
ARM-specific type containing four int32x4_t vectors.
int64x1_tExperimental
ARM-specific 64-bit wide vector of one packed i64.
int64x1x2_tExperimental
ARM-specific type containing two int64x1_t vectors.
int64x1x3_tExperimental
ARM-specific type containing three int64x1_t vectors.
int64x1x4_tExperimental
ARM-specific type containing four int64x1_t vectors.
int64x2_tExperimental
ARM-specific 128-bit wide vector of two packed i64.
int64x2x2_tExperimental
ARM-specific type containing two int64x2_t vectors.
int64x2x3_tExperimental
ARM-specific type containing three int64x2_t vectors.
int64x2x4_tExperimental
ARM-specific type containing four int64x2_t vectors.
poly8x8_tExperimental
ARM-specific 64-bit wide polynomial vector of eight packed p8.
poly8x8x2_tExperimental
ARM-specific type containing two poly8x8_t vectors.
poly8x8x3_tExperimental
ARM-specific type containing three poly8x8_t vectors.
poly8x8x4_tExperimental
ARM-specific type containing four poly8x8_t vectors.
poly8x16_tExperimental
ARM-specific 128-bit wide vector of sixteen packed p8.
poly8x16x2_tExperimental
ARM-specific type containing two poly8x16_t vectors.
poly8x16x3_tExperimental
ARM-specific type containing three poly8x16_t vectors.
poly8x16x4_tExperimental
ARM-specific type containing four poly8x16_t vectors.
poly16x4_tExperimental
ARM-specific 64-bit wide vector of four packed p16.
poly16x4x2_tExperimental
ARM-specific type containing two poly16x4_t vectors.
poly16x4x3_tExperimental
ARM-specific type containing three poly16x4_t vectors.
poly16x4x4_tExperimental
ARM-specific type containing four poly16x4_t vectors.
poly16x8_tExperimental
ARM-specific 128-bit wide vector of eight packed p16.
poly16x8x2_tExperimental
ARM-specific type containing two poly16x8_t vectors.
poly16x8x3_tExperimental
ARM-specific type containing three poly16x8_t vectors.
poly16x8x4_tExperimental
ARM-specific type containing four poly16x8_t vectors.
poly64x1_tExperimental
ARM-specific 64-bit wide vector of one packed p64.
poly64x1x2_tExperimental
ARM-specific type containing two poly64x1_t vectors.
poly64x1x3_tExperimental
ARM-specific type containing three poly64x1_t vectors.
poly64x1x4_tExperimental
ARM-specific type containing four poly64x1_t vectors.
poly64x2_tExperimental
ARM-specific 128-bit wide vector of two packed p64.
poly64x2x2_tExperimental
ARM-specific type containing two poly64x2_t vectors.
poly64x2x3_tExperimental
ARM-specific type containing three poly64x2_t vectors.
poly64x2x4_tExperimental
ARM-specific type containing four poly64x2_t vectors.
uint8x8_tExperimental
ARM-specific 64-bit wide vector of eight packed u8.
uint8x8x2_tExperimental
ARM-specific type containing two uint8x8_t vectors.
uint8x8x3_tExperimental
ARM-specific type containing three uint8x8_t vectors.
uint8x8x4_tExperimental
ARM-specific type containing four uint8x8_t vectors.
uint8x16_tExperimental
ARM-specific 128-bit wide vector of sixteen packed u8.
uint8x16x2_tExperimental
ARM-specific type containing two uint8x16_t vectors.
uint8x16x3_tExperimental
ARM-specific type containing three uint8x16_t vectors.
uint8x16x4_tExperimental
ARM-specific type containing four uint8x16_t vectors.
uint16x4_tExperimental
ARM-specific 64-bit wide vector of four packed u16.
uint16x4x2_tExperimental
ARM-specific type containing two uint16x4_t vectors.
uint16x4x3_tExperimental
ARM-specific type containing three uint16x4_t vectors.
uint16x4x4_tExperimental
ARM-specific type containing four uint16x4_t vectors.
uint16x8_tExperimental
ARM-specific 128-bit wide vector of eight packed u16.
uint16x8x2_tExperimental
ARM-specific type containing two uint16x8_t vectors.
uint16x8x3_tExperimental
ARM-specific type containing three uint16x8_t vectors.
uint16x8x4_tExperimental
ARM-specific type containing four uint16x8_t vectors.
uint32x2_tExperimental
ARM-specific 64-bit wide vector of two packed u32.
uint32x2x2_tExperimental
ARM-specific type containing two uint32x2_t vectors.
uint32x2x3_tExperimental
ARM-specific type containing three uint32x2_t vectors.
uint32x2x4_tExperimental
ARM-specific type containing four uint32x2_t vectors.
uint32x4_tExperimental
ARM-specific 128-bit wide vector of four packed u32.
uint32x4x2_tExperimental
ARM-specific type containing two uint32x4_t vectors.
uint32x4x3_tExperimental
ARM-specific type containing three uint32x4_t vectors.
uint32x4x4_tExperimental
ARM-specific type containing four uint32x4_t vectors.
uint64x1_tExperimental
ARM-specific 64-bit wide vector of one packed u64.
uint64x1x2_tExperimental
ARM-specific type containing two uint64x1_t vectors.
uint64x1x3_tExperimental
ARM-specific type containing three uint64x1_t vectors.
uint64x1x4_tExperimental
ARM-specific type containing four uint64x1_t vectors.
uint64x2_tExperimental
ARM-specific 128-bit wide vector of two packed u64.
uint64x2x2_tExperimental
ARM-specific type containing two uint64x2_t vectors.
uint64x2x3_tExperimental
ARM-specific type containing three uint64x2_t vectors.
uint64x2x4_tExperimental
ARM-specific type containing four uint64x2_t vectors.

Constants§

_PREFETCH_LOCALITY0Experimental
See prefetch.
_PREFETCH_LOCALITY1Experimental
See prefetch.
_PREFETCH_LOCALITY2Experimental
See prefetch.
_PREFETCH_LOCALITY3Experimental
See prefetch.
_PREFETCH_READExperimental
See prefetch.
_PREFETCH_WRITEExperimental
See prefetch.
_TMFAILURE_CNCLExperimental
Transaction executed a TCANCEL instruction
_TMFAILURE_DBGExperimental
Transaction aborted due to a debug trap.
_TMFAILURE_ERRExperimental
Transaction aborted because a non-permissible operation was attempted
_TMFAILURE_IMPExperimental
Fallback error type for any other reason
_TMFAILURE_INTExperimental
Transaction failed from interrupt
_TMFAILURE_MEMExperimental
Transaction aborted because a conflict occurred
_TMFAILURE_NESTExperimental
Transaction aborted due to transactional nesting level was exceeded
_TMFAILURE_REASONExperimental
Extraction mask for failure reason
_TMFAILURE_RTRYExperimental
Transaction retry is possible.
_TMFAILURE_SIZEExperimental
Transaction aborted due to read or write set limit was exceeded
_TMFAILURE_TRIVIALExperimental
Indicates a TRIVIAL version of TM is available
_TMSTART_SUCCESSExperimental
Transaction successfully started.

Functions§

vabal_high_s8neon
Signed Absolute difference and Accumulate Long
vabal_high_s16neon
Signed Absolute difference and Accumulate Long
vabal_high_s32neon
Signed Absolute difference and Accumulate Long
vabal_high_u8neon
Unsigned Absolute difference and Accumulate Long
vabal_high_u16neon
Unsigned Absolute difference and Accumulate Long
vabal_high_u32neon
Unsigned Absolute difference and Accumulate Long
vabd_f64neon
Absolute difference between the arguments of Floating
vabdd_f64neon
Floating-point absolute difference
vabdl_high_s8neon
Signed Absolute difference Long
vabdl_high_s16neon
Signed Absolute difference Long
vabdl_high_s32neon
Signed Absolute difference Long
vabdl_high_u8neon
Unsigned Absolute difference Long
vabdl_high_u16neon
Unsigned Absolute difference Long
vabdl_high_u32neon
Unsigned Absolute difference Long
vabdq_f64neon
Absolute difference between the arguments of Floating
vabds_f32neon
Floating-point absolute difference
vabs_f64neon
Floating-point absolute value
vabs_s64neon
Absolute Value (wrapping).
vabsd_s64neon
Absolute Value (wrapping).
vabsq_f64neon
Floating-point absolute value
vabsq_s64neon
Absolute Value (wrapping).
vadd_f64neon
Vector add.
vadd_s64neon
Vector add.
vadd_u64neon
Vector add.
vaddd_s64neon
Vector add.
vaddd_u64neon
Vector add.
vaddlv_s8neon
Signed Add Long across Vector
vaddlv_s16neon
Signed Add Long across Vector
vaddlv_s32neon
Signed Add Long across Vector
vaddlv_u8neon
Unsigned Add Long across Vector
vaddlv_u16neon
Unsigned Add Long across Vector
vaddlv_u32neon
Unsigned Add Long across Vector
vaddlvq_s8neon
Signed Add Long across Vector
vaddlvq_s16neon
Signed Add Long across Vector
vaddlvq_s32neon
Signed Add Long across Vector
vaddlvq_u8neon
Unsigned Add Long across Vector
vaddlvq_u16neon
Unsigned Add Long across Vector
vaddlvq_u32neon
Unsigned Add Long across Vector
vaddq_f64neon
Vector add.
vaddv_f32neon
Floating-point add across vector
vaddv_s8neon
Add across vector
vaddv_s16neon
Add across vector
vaddv_s32neon
Add across vector
vaddv_u8neon
Add across vector
vaddv_u16neon
Add across vector
vaddv_u32neon
Add across vector
vaddvq_f32neon
Floating-point add across vector
vaddvq_f64neon
Floating-point add across vector
vaddvq_s8neon
Add across vector
vaddvq_s16neon
Add across vector
vaddvq_s32neon
Add across vector
vaddvq_s64neon
Add across vector
vaddvq_u8neon
Add across vector
vaddvq_u16neon
Add across vector
vaddvq_u32neon
Add across vector
vaddvq_u64neon
Add across vector
vbcaxq_s8neon,sha3
Bit clear and exclusive OR
vbcaxq_s16neon,sha3
Bit clear and exclusive OR
vbcaxq_s32neon,sha3
Bit clear and exclusive OR
vbcaxq_s64neon,sha3
Bit clear and exclusive OR
vbcaxq_u8neon,sha3
Bit clear and exclusive OR
vbcaxq_u16neon,sha3
Bit clear and exclusive OR
vbcaxq_u32neon,sha3
Bit clear and exclusive OR
vbcaxq_u64neon,sha3
Bit clear and exclusive OR
vbsl_f64neon
Bitwise Select instructions. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.
vbsl_p64neon
Bitwise Select.
vbslq_f64neon
Bitwise Select. (128-bit)
vbslq_p64neon
Bitwise Select. (128-bit)
vcage_f64neon
Floating-point absolute compare greater than or equal
vcaged_f64neon
Floating-point absolute compare greater than or equal
vcageq_f64neon
Floating-point absolute compare greater than or equal
vcages_f32neon
Floating-point absolute compare greater than or equal
vcagt_f64neon
Floating-point absolute compare greater than
vcagtd_f64neon
Floating-point absolute compare greater than
vcagtq_f64neon
Floating-point absolute compare greater than
vcagts_f32neon
Floating-point absolute compare greater than
vcale_f64neon
Floating-point absolute compare less than or equal
vcaled_f64neon
Floating-point absolute compare less than or equal
vcaleq_f64neon
Floating-point absolute compare less than or equal
vcales_f32neon
Floating-point absolute compare less than or equal
vcalt_f64neon
Floating-point absolute compare less than
vcaltd_f64neon
Floating-point absolute compare less than
vcaltq_f64neon
Floating-point absolute compare less than
vcalts_f32neon
Floating-point absolute compare less than
vceq_f64neon
Floating-point compare equal
vceq_p64neon
Compare bitwise Equal (vector)
vceq_s64neon
Compare bitwise Equal (vector)
vceq_u64neon
Compare bitwise Equal (vector)
vceqd_f64neon
Floating-point compare equal
vceqd_s64neon
Compare bitwise equal
vceqd_u64neon
Compare bitwise equal
vceqq_f64neon
Floating-point compare equal
vceqq_p64neon
Compare bitwise Equal (vector)
vceqq_s64neon
Compare bitwise Equal (vector)
vceqq_u64neon
Compare bitwise Equal (vector)
vceqs_f32neon
Floating-point compare equal
vceqz_f32neon
Floating-point compare bitwise equal to zero
vceqz_f64neon
Floating-point compare bitwise equal to zero
vceqz_p8neon
Signed compare bitwise equal to zero
vceqz_p64neon
Signed compare bitwise equal to zero
vceqz_s8neon
Signed compare bitwise equal to zero
vceqz_s16neon
Signed compare bitwise equal to zero
vceqz_s32neon
Signed compare bitwise equal to zero
vceqz_s64neon
Signed compare bitwise equal to zero
vceqz_u8neon
Unsigned compare bitwise equal to zero
vceqz_u16neon
Unsigned compare bitwise equal to zero
vceqz_u32neon
Unsigned compare bitwise equal to zero
vceqz_u64neon
Unsigned compare bitwise equal to zero
vceqzd_f64neon
Floating-point compare bitwise equal to zero
vceqzd_s64neon
Compare bitwise equal to zero
vceqzd_u64neon
Compare bitwise equal to zero
vceqzq_f32neon
Floating-point compare bitwise equal to zero
vceqzq_f64neon
Floating-point compare bitwise equal to zero
vceqzq_p8neon
Signed compare bitwise equal to zero
vceqzq_p64neon
Signed compare bitwise equal to zero
vceqzq_s8neon
Signed compare bitwise equal to zero
vceqzq_s16neon
Signed compare bitwise equal to zero
vceqzq_s32neon
Signed compare bitwise equal to zero
vceqzq_s64neon
Signed compare bitwise equal to zero
vceqzq_u8neon
Unsigned compare bitwise equal to zero
vceqzq_u16neon
Unsigned compare bitwise equal to zero
vceqzq_u32neon
Unsigned compare bitwise equal to zero
vceqzq_u64neon
Unsigned compare bitwise equal to zero
vceqzs_f32neon
Floating-point compare bitwise equal to zero
vcge_f64neon
Floating-point compare greater than or equal
vcge_s64neon
Compare signed greater than or equal
vcge_u64neon
Compare unsigned greater than or equal
vcged_f64neon
Floating-point compare greater than or equal
vcged_s64neon
Compare greater than or equal
vcged_u64neon
Compare greater than or equal
vcgeq_f64neon
Floating-point compare greater than or equal
vcgeq_s64neon
Compare signed greater than or equal
vcgeq_u64neon
Compare unsigned greater than or equal
vcges_f32neon
Floating-point compare greater than or equal
vcgez_f32neon
Floating-point compare greater than or equal to zero
vcgez_f64neon
Floating-point compare greater than or equal to zero
vcgez_s8neon
Compare signed greater than or equal to zero
vcgez_s16neon
Compare signed greater than or equal to zero
vcgez_s32neon
Compare signed greater than or equal to zero
vcgez_s64neon
Compare signed greater than or equal to zero
vcgezd_f64neon
Floating-point compare greater than or equal to zero
vcgezd_s64neon
Compare signed greater than or equal to zero
vcgezq_f32neon
Floating-point compare greater than or equal to zero
vcgezq_f64neon
Floating-point compare greater than or equal to zero
vcgezq_s8neon
Compare signed greater than or equal to zero
vcgezq_s16neon
Compare signed greater than or equal to zero
vcgezq_s32neon
Compare signed greater than or equal to zero
vcgezq_s64neon
Compare signed greater than or equal to zero
vcgezs_f32neon
Floating-point compare greater than or equal to zero
vcgt_f64neon
Floating-point compare greater than
vcgt_s64neon
Compare signed greater than
vcgt_u64neon
Compare unsigned greater than
vcgtd_f64neon
Floating-point compare greater than
vcgtd_s64neon
Compare greater than
vcgtd_u64neon
Compare greater than
vcgtq_f64neon
Floating-point compare greater than
vcgtq_s64neon
Compare signed greater than
vcgtq_u64neon
Compare unsigned greater than
vcgts_f32neon
Floating-point compare greater than
vcgtz_f32neon
Floating-point compare greater than zero
vcgtz_f64neon
Floating-point compare greater than zero
vcgtz_s8neon
Compare signed greater than zero
vcgtz_s16neon
Compare signed greater than zero
vcgtz_s32neon
Compare signed greater than zero
vcgtz_s64neon
Compare signed greater than zero
vcgtzd_f64neon
Floating-point compare greater than zero
vcgtzd_s64neon
Compare signed greater than zero
vcgtzq_f32neon
Floating-point compare greater than zero
vcgtzq_f64neon
Floating-point compare greater than zero
vcgtzq_s8neon
Compare signed greater than zero
vcgtzq_s16neon
Compare signed greater than zero
vcgtzq_s32neon
Compare signed greater than zero
vcgtzq_s64neon
Compare signed greater than zero
vcgtzs_f32neon
Floating-point compare greater than zero
vcle_f64neon
Floating-point compare less than or equal
vcle_s64neon
Compare signed less than or equal
vcle_u64neon
Compare unsigned less than or equal
vcled_f64neon
Floating-point compare less than or equal
vcled_s64neon
Compare less than or equal
vcled_u64neon
Compare less than or equal
vcleq_f64neon
Floating-point compare less than or equal
vcleq_s64neon
Compare signed less than or equal
vcleq_u64neon
Compare unsigned less than or equal
vcles_f32neon
Floating-point compare less than or equal
vclez_f32neon
Floating-point compare less than or equal to zero
vclez_f64neon
Floating-point compare less than or equal to zero
vclez_s8neon
Compare signed less than or equal to zero
vclez_s16neon
Compare signed less than or equal to zero
vclez_s32neon
Compare signed less than or equal to zero
vclez_s64neon
Compare signed less than or equal to zero
vclezd_f64neon
Floating-point compare less than or equal to zero
vclezd_s64neon
Compare less than or equal to zero
vclezq_f32neon
Floating-point compare less than or equal to zero
vclezq_f64neon
Floating-point compare less than or equal to zero
vclezq_s8neon
Compare signed less than or equal to zero
vclezq_s16neon
Compare signed less than or equal to zero
vclezq_s32neon
Compare signed less than or equal to zero
vclezq_s64neon
Compare signed less than or equal to zero
vclezs_f32neon
Floating-point compare less than or equal to zero
vclt_f64neon
Floating-point compare less than
vclt_s64neon
Compare signed less than
vclt_u64neon
Compare unsigned less than
vcltd_f64neon
Floating-point compare less than
vcltd_s64neon
Compare less than
vcltd_u64neon
Compare less than
vcltq_f64neon
Floating-point compare less than
vcltq_s64neon
Compare signed less than
vcltq_u64neon
Compare unsigned less than
vclts_f32neon
Floating-point compare less than
vcltz_f32neon
Floating-point compare less than zero
vcltz_f64neon
Floating-point compare less than zero
vcltz_s8neon
Compare signed less than zero
vcltz_s16neon
Compare signed less than zero
vcltz_s32neon
Compare signed less than zero
vcltz_s64neon
Compare signed less than zero
vcltzd_f64neon
Floating-point compare less than zero
vcltzd_s64neon
Compare less than zero
vcltzq_f32neon
Floating-point compare less than zero
vcltzq_f64neon
Floating-point compare less than zero
vcltzq_s8neon
Compare signed less than zero
vcltzq_s16neon
Compare signed less than zero
vcltzq_s32neon
Compare signed less than zero
vcltzq_s64neon
Compare signed less than zero
vcltzs_f32neon
Floating-point compare less than zero
vcombine_f64neon
Vector combine
vcopy_lane_f32neon
Insert vector element from another vector element
vcopy_lane_f64neon
Duplicate vector element to vector or scalar
vcopy_lane_p8neon
Insert vector element from another vector element
vcopy_lane_p16neon
Insert vector element from another vector element
vcopy_lane_p64neon
Duplicate vector element to vector or scalar
vcopy_lane_s8neon
Insert vector element from another vector element
vcopy_lane_s16neon
Insert vector element from another vector element
vcopy_lane_s32neon
Insert vector element from another vector element
vcopy_lane_s64neon
Duplicate vector element to vector or scalar
vcopy_lane_u8neon
Insert vector element from another vector element
vcopy_lane_u16neon
Insert vector element from another vector element
vcopy_lane_u32neon
Insert vector element from another vector element
vcopy_lane_u64neon
Duplicate vector element to vector or scalar
vcopy_laneq_f32neon
Insert vector element from another vector element
vcopy_laneq_f64neon
Duplicate vector element to vector or scalar
vcopy_laneq_p8neon
Insert vector element from another vector element
vcopy_laneq_p16neon
Insert vector element from another vector element
vcopy_laneq_p64neon
Duplicate vector element to vector or scalar
vcopy_laneq_s8neon
Insert vector element from another vector element
vcopy_laneq_s16neon
Insert vector element from another vector element
vcopy_laneq_s32neon
Insert vector element from another vector element
vcopy_laneq_s64neon
Duplicate vector element to vector or scalar
vcopy_laneq_u8neon
Insert vector element from another vector element
vcopy_laneq_u16neon
Insert vector element from another vector element
vcopy_laneq_u32neon
Insert vector element from another vector element
vcopy_laneq_u64neon
Duplicate vector element to vector or scalar
vcopyq_lane_f32neon
Insert vector element from another vector element
vcopyq_lane_f64neon
Insert vector element from another vector element
vcopyq_lane_p8neon
Insert vector element from another vector element
vcopyq_lane_p16neon
Insert vector element from another vector element
vcopyq_lane_p64neon
Insert vector element from another vector element
vcopyq_lane_s8neon
Insert vector element from another vector element
vcopyq_lane_s16neon
Insert vector element from another vector element
vcopyq_lane_s32neon
Insert vector element from another vector element
vcopyq_lane_s64neon
Insert vector element from another vector element
vcopyq_lane_u8neon
Insert vector element from another vector element
vcopyq_lane_u16neon
Insert vector element from another vector element
vcopyq_lane_u32neon
Insert vector element from another vector element
vcopyq_lane_u64neon
Insert vector element from another vector element
vcopyq_laneq_f32neon
Insert vector element from another vector element
vcopyq_laneq_f64neon
Insert vector element from another vector element
vcopyq_laneq_p8neon
Insert vector element from another vector element
vcopyq_laneq_p16neon
Insert vector element from another vector element
vcopyq_laneq_p64neon
Insert vector element from another vector element
vcopyq_laneq_s8neon
Insert vector element from another vector element
vcopyq_laneq_s16neon
Insert vector element from another vector element
vcopyq_laneq_s32neon
Insert vector element from another vector element
vcopyq_laneq_s64neon
Insert vector element from another vector element
vcopyq_laneq_u8neon
Insert vector element from another vector element
vcopyq_laneq_u16neon
Insert vector element from another vector element
vcopyq_laneq_u32neon
Insert vector element from another vector element
vcopyq_laneq_u64neon
Insert vector element from another vector element
vcreate_f64neon
Insert vector element from another vector element
vcvt_f32_f64neon
Floating-point convert to lower precision narrow
vcvt_f64_f32neon
Floating-point convert to higher precision long
vcvt_f64_s64neon
Fixed-point convert to floating-point
vcvt_f64_u64neon
Fixed-point convert to floating-point
vcvt_high_f32_f64neon
Floating-point convert to lower precision narrow
vcvt_high_f64_f32neon
Floating-point convert to higher precision long
vcvt_n_f64_s64neon
Fixed-point convert to floating-point
vcvt_n_f64_u64neon
Fixed-point convert to floating-point
vcvt_n_s64_f64neon
Floating-point convert to fixed-point, rounding toward zero
vcvt_n_u64_f64neon
Floating-point convert to fixed-point, rounding toward zero
vcvt_s64_f64neon
Floating-point convert to signed fixed-point, rounding toward zero
vcvt_u64_f64neon
Floating-point convert to unsigned fixed-point, rounding toward zero
vcvta_s32_f32neon
Floating-point convert to signed integer, rounding to nearest with ties to away
vcvta_s64_f64neon
Floating-point convert to signed integer, rounding to nearest with ties to away
vcvta_u32_f32neon
Floating-point convert to unsigned integer, rounding to nearest with ties to away
vcvta_u64_f64neon
Floating-point convert to unsigned integer, rounding to nearest with ties to away
vcvtad_s64_f64neon
Floating-point convert to integer, rounding to nearest with ties to away
vcvtad_u64_f64neon
Floating-point convert to integer, rounding to nearest with ties to away
vcvtaq_s32_f32neon
Floating-point convert to signed integer, rounding to nearest with ties to away
vcvtaq_s64_f64neon
Floating-point convert to signed integer, rounding to nearest with ties to away
vcvtaq_u32_f32neon
Floating-point convert to unsigned integer, rounding to nearest with ties to away
vcvtaq_u64_f64neon
Floating-point convert to unsigned integer, rounding to nearest with ties to away
vcvtas_s32_f32neon
Floating-point convert to integer, rounding to nearest with ties to away
vcvtas_u32_f32neon
Floating-point convert to integer, rounding to nearest with ties to away
vcvtd_f64_s64neon
Fixed-point convert to floating-point
vcvtd_f64_u64neon
Fixed-point convert to floating-point
vcvtd_n_f64_s64neon
Fixed-point convert to floating-point
vcvtd_n_f64_u64neon
Fixed-point convert to floating-point
vcvtd_n_s64_f64neon
Floating-point convert to fixed-point, rounding toward zero
vcvtd_n_u64_f64neon
Floating-point convert to fixed-point, rounding toward zero
vcvtd_s64_f64neon
Fixed-point convert to floating-point
vcvtd_u64_f64neon
Fixed-point convert to floating-point
vcvtm_s32_f32neon
Floating-point convert to signed integer, rounding toward minus infinity
vcvtm_s64_f64neon
Floating-point convert to signed integer, rounding toward minus infinity
vcvtm_u32_f32neon
Floating-point convert to unsigned integer, rounding toward minus infinity
vcvtm_u64_f64neon
Floating-point convert to unsigned integer, rounding toward minus infinity
vcvtmd_s64_f64neon
Floating-point convert to signed integer, rounding toward minus infinity
vcvtmd_u64_f64neon
Floating-point convert to unsigned integer, rounding toward minus infinity
vcvtmq_s32_f32neon
Floating-point convert to signed integer, rounding toward minus infinity
vcvtmq_s64_f64neon
Floating-point convert to signed integer, rounding toward minus infinity
vcvtmq_u32_f32neon
Floating-point convert to unsigned integer, rounding toward minus infinity
vcvtmq_u64_f64neon
Floating-point convert to unsigned integer, rounding toward minus infinity
vcvtms_s32_f32neon
Floating-point convert to signed integer, rounding toward minus infinity
vcvtms_u32_f32neon
Floating-point convert to unsigned integer, rounding toward minus infinity
vcvtn_s32_f32neon
Floating-point convert to signed integer, rounding to nearest with ties to even
vcvtn_s64_f64neon
Floating-point convert to signed integer, rounding to nearest with ties to even
vcvtn_u32_f32neon
Floating-point convert to unsigned integer, rounding to nearest with ties to even
vcvtn_u64_f64neon
Floating-point convert to unsigned integer, rounding to nearest with ties to even
vcvtnd_s64_f64neon
Floating-point convert to signed integer, rounding to nearest with ties to even
vcvtnd_u64_f64neon
Floating-point convert to unsigned integer, rounding to nearest with ties to even
vcvtnq_s32_f32neon
Floating-point convert to signed integer, rounding to nearest with ties to even
vcvtnq_s64_f64neon
Floating-point convert to signed integer, rounding to nearest with ties to even
vcvtnq_u32_f32neon
Floating-point convert to unsigned integer, rounding to nearest with ties to even
vcvtnq_u64_f64neon
Floating-point convert to unsigned integer, rounding to nearest with ties to even
vcvtns_s32_f32neon
Floating-point convert to signed integer, rounding to nearest with ties to even
vcvtns_u32_f32neon
Floating-point convert to unsigned integer, rounding to nearest with ties to even
vcvtp_s32_f32neon
Floating-point convert to signed integer, rounding toward plus infinity
vcvtp_s64_f64neon
Floating-point convert to signed integer, rounding toward plus infinity
vcvtp_u32_f32neon
Floating-point convert to unsigned integer, rounding toward plus infinity
vcvtp_u64_f64neon
Floating-point convert to unsigned integer, rounding toward plus infinity
vcvtpd_s64_f64neon
Floating-point convert to signed integer, rounding toward plus infinity
vcvtpd_u64_f64neon
Floating-point convert to unsigned integer, rounding toward plus infinity
vcvtpq_s32_f32neon
Floating-point convert to signed integer, rounding toward plus infinity
vcvtpq_s64_f64neon
Floating-point convert to signed integer, rounding toward plus infinity
vcvtpq_u32_f32neon
Floating-point convert to unsigned integer, rounding toward plus infinity
vcvtpq_u64_f64neon
Floating-point convert to unsigned integer, rounding toward plus infinity
vcvtps_s32_f32neon
Floating-point convert to signed integer, rounding toward plus infinity
vcvtps_u32_f32neon
Floating-point convert to unsigned integer, rounding toward plus infinity
vcvtq_f64_s64neon
Fixed-point convert to floating-point
vcvtq_f64_u64neon
Fixed-point convert to floating-point
vcvtq_n_f64_s64neon
Fixed-point convert to floating-point
vcvtq_n_f64_u64neon
Fixed-point convert to floating-point
vcvtq_n_s64_f64neon
Floating-point convert to fixed-point, rounding toward zero
vcvtq_n_u64_f64neon
Floating-point convert to fixed-point, rounding toward zero
vcvtq_s64_f64neon
Floating-point convert to signed fixed-point, rounding toward zero
vcvtq_u64_f64neon
Floating-point convert to unsigned fixed-point, rounding toward zero
vcvts_f32_s32neon
Fixed-point convert to floating-point
vcvts_f32_u32neon
Fixed-point convert to floating-point
vcvts_n_f32_s32neon
Fixed-point convert to floating-point
vcvts_n_f32_u32neon
Fixed-point convert to floating-point
vcvts_n_s32_f32neon
Floating-point convert to fixed-point, rounding toward zero
vcvts_n_u32_f32neon
Floating-point convert to fixed-point, rounding toward zero
vcvts_s32_f32neon
Fixed-point convert to floating-point
vcvts_u32_f32neon
Fixed-point convert to floating-point
vcvtx_f32_f64neon
Floating-point convert to lower precision narrow, rounding to odd
vcvtx_high_f32_f64neon
Floating-point convert to lower precision narrow, rounding to odd
vcvtxd_f32_f64neon
Floating-point convert to lower precision narrow, rounding to odd
vdiv_f32neon
Divide
vdiv_f64neon
Divide
vdivq_f32neon
Divide
vdivq_f64neon
Divide
vdup_lane_f64neon
Set all vector lanes to the same value
vdup_lane_p64neon
Set all vector lanes to the same value
vdup_laneq_f64neon
Set all vector lanes to the same value
vdup_laneq_p64neon
Set all vector lanes to the same value
vdup_n_f64neon
Duplicate vector element to vector or scalar
vdup_n_p64neon
Duplicate vector element to vector or scalar
vdupb_lane_p8neon
Set all vector lanes to the same value
vdupb_lane_s8neon
Set all vector lanes to the same value
vdupb_lane_u8neon
Set all vector lanes to the same value
vdupb_laneq_p8neon
Set all vector lanes to the same value
vdupb_laneq_s8neon
Set all vector lanes to the same value
vdupb_laneq_u8neon
Set all vector lanes to the same value
vdupd_lane_f64neon
Set all vector lanes to the same value
vdupd_lane_s64neon
Set all vector lanes to the same value
vdupd_lane_u64neon
Set all vector lanes to the same value
vdupd_laneq_f64neon
Set all vector lanes to the same value
vdupd_laneq_s64neon
Set all vector lanes to the same value
vdupd_laneq_u64neon
Set all vector lanes to the same value
vduph_lane_p16neon
Set all vector lanes to the same value
vduph_lane_s16neon
Set all vector lanes to the same value
vduph_lane_u16neon
Set all vector lanes to the same value
vduph_laneq_p16neon
Set all vector lanes to the same value
vduph_laneq_s16neon
Set all vector lanes to the same value
vduph_laneq_u16neon
Set all vector lanes to the same value
vdupq_lane_f64neon
Set all vector lanes to the same value
vdupq_lane_p64neon
Set all vector lanes to the same value
vdupq_laneq_f64neon
Set all vector lanes to the same value
vdupq_laneq_p64neon
Set all vector lanes to the same value
vdupq_n_f64neon
Duplicate vector element to vector or scalar
vdupq_n_p64neon
Duplicate vector element to vector or scalar
vdups_lane_f32neon
Set all vector lanes to the same value
vdups_lane_s32neon
Set all vector lanes to the same value
vdups_lane_u32neon
Set all vector lanes to the same value
vdups_laneq_f32neon
Set all vector lanes to the same value
vdups_laneq_s32neon
Set all vector lanes to the same value
vdups_laneq_u32neon
Set all vector lanes to the same value
veor3q_s8neon,sha3
Three-way exclusive OR
veor3q_s16neon,sha3
Three-way exclusive OR
veor3q_s32neon,sha3
Three-way exclusive OR
veor3q_s64neon,sha3
Three-way exclusive OR
veor3q_u8neon,sha3
Three-way exclusive OR
veor3q_u16neon,sha3
Three-way exclusive OR
veor3q_u32neon,sha3
Three-way exclusive OR
veor3q_u64neon,sha3
Three-way exclusive OR
vext_f64neon
Extract vector from pair of vectors
vext_p64neon
Extract vector from pair of vectors
vextq_f64neon
Extract vector from pair of vectors
vextq_p64neon
Extract vector from pair of vectors
vfma_f64neon
Floating-point fused Multiply-Add to accumulator(vector)
vfma_lane_f32neon
Floating-point fused multiply-add to accumulator
vfma_lane_f64neon
Floating-point fused multiply-add to accumulator
vfma_laneq_f32neon
Floating-point fused multiply-add to accumulator
vfma_laneq_f64neon
Floating-point fused multiply-add to accumulator
vfma_n_f64neon
Floating-point fused Multiply-Add to accumulator(vector)
vfmad_lane_f64neon
Floating-point fused multiply-add to accumulator
vfmad_laneq_f64neon
Floating-point fused multiply-add to accumulator
vfmaq_f64neon
Floating-point fused Multiply-Add to accumulator(vector)
vfmaq_lane_f32neon
Floating-point fused multiply-add to accumulator
vfmaq_lane_f64neon
Floating-point fused multiply-add to accumulator
vfmaq_laneq_f32neon
Floating-point fused multiply-add to accumulator
vfmaq_laneq_f64neon
Floating-point fused multiply-add to accumulator
vfmaq_n_f64neon
Floating-point fused Multiply-Add to accumulator(vector)
vfmas_lane_f32neon
Floating-point fused multiply-add to accumulator
vfmas_laneq_f32neon
Floating-point fused multiply-add to accumulator
vfms_f64neon
Floating-point fused multiply-subtract from accumulator
vfms_lane_f32neon
Floating-point fused multiply-subtract to accumulator
vfms_lane_f64neon
Floating-point fused multiply-subtract to accumulator
vfms_laneq_f32neon
Floating-point fused multiply-subtract to accumulator
vfms_laneq_f64neon
Floating-point fused multiply-subtract to accumulator
vfms_n_f64neon
Floating-point fused Multiply-subtract to accumulator(vector)
vfmsd_lane_f64neon
Floating-point fused multiply-subtract to accumulator
vfmsd_laneq_f64neon
Floating-point fused multiply-subtract to accumulator
vfmsq_f64neon
Floating-point fused multiply-subtract from accumulator
vfmsq_lane_f32neon
Floating-point fused multiply-subtract to accumulator
vfmsq_lane_f64neon
Floating-point fused multiply-subtract to accumulator
vfmsq_laneq_f32neon
Floating-point fused multiply-subtract to accumulator
vfmsq_laneq_f64neon
Floating-point fused multiply-subtract to accumulator
vfmsq_n_f64neon
Floating-point fused Multiply-subtract to accumulator(vector)
vfmss_lane_f32neon
Floating-point fused multiply-subtract to accumulator
vfmss_laneq_f32neon
Floating-point fused multiply-subtract to accumulator
vget_high_f64neon
Duplicate vector element to vector or scalar
vget_high_p64neon
Duplicate vector element to vector or scalar
vget_lane_f64neon
Duplicate vector element to vector or scalar
vget_low_f64neon
Duplicate vector element to vector or scalar
vget_low_p64neon
Duplicate vector element to vector or scalar
vgetq_lane_f64neon
Duplicate vector element to vector or scalar
vld1_dup_f64neon
Load multiple single-element structures to one, two, three, or four registers
vld1_f32neon
Load multiple single-element structures to one, two, three, or four registers.
vld1_f64neon
Load multiple single-element structures to one, two, three, or four registers.
vld1_f64_x2neon
Load multiple single-element structures to one, two, three, or four registers
vld1_f64_x3neon
Load multiple single-element structures to one, two, three, or four registers
vld1_f64_x4neon
Load multiple single-element structures to one, two, three, or four registers
vld1_lane_f64neon
Load one single-element structure to one lane of one register.
vld1_p8neon
Load multiple single-element structures to one, two, three, or four registers.
vld1_p16neon
Load multiple single-element structures to one, two, three, or four registers.
vld1_p64neon,aes
Load multiple single-element structures to one, two, three, or four registers.
vld1_s8neon
Load multiple single-element structures to one, two, three, or four registers.
vld1_s16neon
Load multiple single-element structures to one, two, three, or four registers.
vld1_s32neon
Load multiple single-element structures to one, two, three, or four registers.
vld1_s64neon
Load multiple single-element structures to one, two, three, or four registers.
vld1_u8neon
Load multiple single-element structures to one, two, three, or four registers.
vld1_u16neon
Load multiple single-element structures to one, two, three, or four registers.
vld1_u32neon
Load multiple single-element structures to one, two, three, or four registers.
vld1_u64neon
Load multiple single-element structures to one, two, three, or four registers.
vld1q_dup_f64neon
Load multiple single-element structures to one, two, three, or four registers
vld1q_f32neon
Load multiple single-element structures to one, two, three, or four registers.
vld1q_f64neon
Load multiple single-element structures to one, two, three, or four registers.
vld1q_f64_x2neon
Load multiple single-element structures to one, two, three, or four registers
vld1q_f64_x3neon
Load multiple single-element structures to one, two, three, or four registers
vld1q_f64_x4neon
Load multiple single-element structures to one, two, three, or four registers
vld1q_lane_f64neon
Load one single-element structure to one lane of one register.
vld1q_p8neon
Load multiple single-element structures to one, two, three, or four registers.
vld1q_p16neon
Load multiple single-element structures to one, two, three, or four registers.
vld1q_p64neon,aes
Load multiple single-element structures to one, two, three, or four registers.
vld1q_s8neon
Load multiple single-element structures to one, two, three, or four registers.
vld1q_s16neon
Load multiple single-element structures to one, two, three, or four registers.
vld1q_s32neon
Load multiple single-element structures to one, two, three, or four registers.
vld1q_s64neon
Load multiple single-element structures to one, two, three, or four registers.
vld1q_u8neon
Load multiple single-element structures to one, two, three, or four registers.
vld1q_u16neon
Load multiple single-element structures to one, two, three, or four registers.
vld1q_u32neon
Load multiple single-element structures to one, two, three, or four registers.
vld1q_u64neon
Load multiple single-element structures to one, two, three, or four registers.
vld2_dup_f64neon
Load single 2-element structure and replicate to all lanes of two registers
vld2_f64neon
Load multiple 2-element structures to two registers
vld2_lane_f64neon
Load multiple 2-element structures to two registers
vld2_lane_p64neon,aes
Load multiple 2-element structures to two registers
vld2_lane_s64neon
Load multiple 2-element structures to two registers
vld2_lane_u64neon
Load multiple 2-element structures to two registers
vld2q_dup_f64neon
Load single 2-element structure and replicate to all lanes of two registers
vld2q_dup_p64neon,aes
Load single 2-element structure and replicate to all lanes of two registers
vld2q_dup_s64neon
Load single 2-element structure and replicate to all lanes of two registers
vld2q_dup_u64neon
Load single 2-element structure and replicate to all lanes of two registers
vld2q_f64neon
Load multiple 2-element structures to two registers
vld2q_lane_f64neon
Load multiple 2-element structures to two registers
vld2q_lane_p8neon
Load multiple 2-element structures to two registers
vld2q_lane_p64neon,aes
Load multiple 2-element structures to two registers
vld2q_lane_s8neon
Load multiple 2-element structures to two registers
vld2q_lane_s64neon
Load multiple 2-element structures to two registers
vld2q_lane_u8neon
Load multiple 2-element structures to two registers
vld2q_lane_u64neon
Load multiple 2-element structures to two registers
vld2q_p64neon,aes
Load multiple 2-element structures to two registers
vld2q_s64neon
Load multiple 2-element structures to two registers
vld2q_u64neon
Load multiple 2-element structures to two registers
vld3_dup_f64neon
Load single 3-element structure and replicate to all lanes of three registers
vld3_f64neon
Load multiple 3-element structures to three registers
vld3_lane_f64neon
Load multiple 3-element structures to three registers
vld3_lane_p64neon,aes
Load multiple 3-element structures to three registers
vld3_lane_s64neon
Load multiple 3-element structures to two registers
vld3_lane_u64neon
Load multiple 3-element structures to three registers
vld3q_dup_f64neon
Load single 3-element structure and replicate to all lanes of three registers
vld3q_dup_p64neon,aes
Load single 3-element structure and replicate to all lanes of three registers
vld3q_dup_s64neon
Load single 3-element structure and replicate to all lanes of three registers
vld3q_dup_u64neon
Load single 3-element structure and replicate to all lanes of three registers
vld3q_f64neon
Load multiple 3-element structures to three registers
vld3q_lane_f64neon
Load multiple 3-element structures to three registers
vld3q_lane_p8neon
Load multiple 3-element structures to three registers
vld3q_lane_p64neon,aes
Load multiple 3-element structures to three registers
vld3q_lane_s8neon
Load multiple 3-element structures to two registers
vld3q_lane_s64neon
Load multiple 3-element structures to two registers
vld3q_lane_u8neon
Load multiple 3-element structures to three registers
vld3q_lane_u64neon
Load multiple 3-element structures to three registers
vld3q_p64neon,aes
Load multiple 3-element structures to three registers
vld3q_s64neon
Load multiple 3-element structures to three registers
vld3q_u64neon
Load multiple 3-element structures to three registers
vld4_dup_f64neon
Load single 4-element structure and replicate to all lanes of four registers
vld4_f64neon
Load multiple 4-element structures to four registers
vld4_lane_f64neon
Load multiple 4-element structures to four registers
vld4_lane_p64neon,aes
Load multiple 4-element structures to four registers
vld4_lane_s64neon
Load multiple 4-element structures to four registers
vld4_lane_u64neon
Load multiple 4-element structures to four registers
vld4q_dup_f64neon
Load single 4-element structure and replicate to all lanes of four registers
vld4q_dup_p64neon,aes
Load single 4-element structure and replicate to all lanes of four registers
vld4q_dup_s64neon
Load single 4-element structure and replicate to all lanes of four registers
vld4q_dup_u64neon
Load single 4-element structure and replicate to all lanes of four registers
vld4q_f64neon
Load multiple 4-element structures to four registers
vld4q_lane_f64neon
Load multiple 4-element structures to four registers
vld4q_lane_p8neon
Load multiple 4-element structures to four registers
vld4q_lane_p64neon,aes
Load multiple 4-element structures to four registers
vld4q_lane_s8neon
Load multiple 4-element structures to four registers
vld4q_lane_s64neon
Load multiple 4-element structures to four registers
vld4q_lane_u8neon
Load multiple 4-element structures to four registers
vld4q_lane_u64neon
Load multiple 4-element structures to four registers
vld4q_p64neon,aes
Load multiple 4-element structures to four registers
vld4q_s64neon
Load multiple 4-element structures to four registers
vld4q_u64neon
Load multiple 4-element structures to four registers
vmax_f64neon
Maximum (vector)
vmaxnm_f64neon
Floating-point Maximum Number (vector)
vmaxnmq_f64neon
Floating-point Maximum Number (vector)
vmaxnmv_f32neon
Floating-point maximum number across vector
vmaxnmvq_f32neon
Floating-point maximum number across vector
vmaxnmvq_f64neon
Floating-point maximum number across vector
vmaxq_f64neon
Maximum (vector)
vmaxv_f32neon
Horizontal vector max.
vmaxv_s8neon
Horizontal vector max.
vmaxv_s16neon
Horizontal vector max.
vmaxv_s32neon
Horizontal vector max.
vmaxv_u8neon
Horizontal vector max.
vmaxv_u16neon
Horizontal vector max.
vmaxv_u32neon
Horizontal vector max.
vmaxvq_f32neon
Horizontal vector max.
vmaxvq_f64neon
Horizontal vector max.
vmaxvq_s8neon
Horizontal vector max.
vmaxvq_s16neon
Horizontal vector max.
vmaxvq_s32neon
Horizontal vector max.
vmaxvq_u8neon
Horizontal vector max.
vmaxvq_u16neon
Horizontal vector max.
vmaxvq_u32neon
Horizontal vector max.
vmin_f64neon
Minimum (vector)
vminnm_f64neon
Floating-point Minimum Number (vector)
vminnmq_f64neon
Floating-point Minimum Number (vector)
vminnmv_f32neon
Floating-point minimum number across vector
vminnmvq_f32neon
Floating-point minimum number across vector
vminnmvq_f64neon
Floating-point minimum number across vector
vminq_f64neon
Minimum (vector)
vminv_f32neon
Horizontal vector min.
vminv_s8neon
Horizontal vector min.
vminv_s16neon
Horizontal vector min.
vminv_s32neon
Horizontal vector min.
vminv_u8neon
Horizontal vector min.
vminv_u16neon
Horizontal vector min.
vminv_u32neon
Horizontal vector min.
vminvq_f32neon
Horizontal vector min.
vminvq_f64neon
Horizontal vector min.
vminvq_s8neon
Horizontal vector min.
vminvq_s16neon
Horizontal vector min.
vminvq_s32neon
Horizontal vector min.
vminvq_u8neon
Horizontal vector min.
vminvq_u16neon
Horizontal vector min.
vminvq_u32neon
Horizontal vector min.
vmla_f64neon
Floating-point multiply-add to accumulator
vmlal_high_lane_s16neon
Multiply-add long
vmlal_high_lane_s32neon
Multiply-add long
vmlal_high_lane_u16neon
Multiply-add long
vmlal_high_lane_u32neon
Multiply-add long
vmlal_high_laneq_s16neon
Multiply-add long
vmlal_high_laneq_s32neon
Multiply-add long
vmlal_high_laneq_u16neon
Multiply-add long
vmlal_high_laneq_u32neon
Multiply-add long
vmlal_high_n_s16neon
Multiply-add long
vmlal_high_n_s32neon
Multiply-add long
vmlal_high_n_u16neon
Multiply-add long
vmlal_high_n_u32neon
Multiply-add long
vmlal_high_s8neon
Signed multiply-add long
vmlal_high_s16neon
Signed multiply-add long
vmlal_high_s32neon
Signed multiply-add long
vmlal_high_u8neon
Unsigned multiply-add long
vmlal_high_u16neon
Unsigned multiply-add long
vmlal_high_u32neon
Unsigned multiply-add long
vmlaq_f64neon
Floating-point multiply-add to accumulator
vmls_f64neon
Floating-point multiply-subtract from accumulator
vmlsl_high_lane_s16neon
Multiply-subtract long
vmlsl_high_lane_s32neon
Multiply-subtract long
vmlsl_high_lane_u16neon
Multiply-subtract long
vmlsl_high_lane_u32neon
Multiply-subtract long
vmlsl_high_laneq_s16neon
Multiply-subtract long
vmlsl_high_laneq_s32neon
Multiply-subtract long
vmlsl_high_laneq_u16neon
Multiply-subtract long
vmlsl_high_laneq_u32neon
Multiply-subtract long
vmlsl_high_n_s16neon
Multiply-subtract long
vmlsl_high_n_s32neon
Multiply-subtract long
vmlsl_high_n_u16neon
Multiply-subtract long
vmlsl_high_n_u32neon
Multiply-subtract long
vmlsl_high_s8neon
Signed multiply-subtract long
vmlsl_high_s16neon
Signed multiply-subtract long
vmlsl_high_s32neon
Signed multiply-subtract long
vmlsl_high_u8neon
Unsigned multiply-subtract long
vmlsl_high_u16neon
Unsigned multiply-subtract long
vmlsl_high_u32neon
Unsigned multiply-subtract long
vmlsq_f64neon
Floating-point multiply-subtract from accumulator
vmov_n_f64neon
Duplicate vector element to vector or scalar
vmov_n_p64neon
Duplicate vector element to vector or scalar
vmovl_high_s8neon
Vector move
vmovl_high_s16neon
Vector move
vmovl_high_s32neon
Vector move
vmovl_high_u8neon
Vector move
vmovl_high_u16neon
Vector move
vmovl_high_u32neon
Vector move
vmovn_high_s16neon
Extract narrow
vmovn_high_s32neon
Extract narrow
vmovn_high_s64neon
Extract narrow
vmovn_high_u16neon
Extract narrow
vmovn_high_u32neon
Extract narrow
vmovn_high_u64neon
Extract narrow
vmovq_n_f64neon
Duplicate vector element to vector or scalar
vmovq_n_p64neon
Duplicate vector element to vector or scalar
vmul_f64neon
Multiply
vmul_lane_f64neon
Floating-point multiply
vmul_laneq_f64neon
Floating-point multiply
vmul_n_f64neon
Vector multiply by scalar
vmuld_lane_f64neon
Floating-point multiply
vmuld_laneq_f64neon
Floating-point multiply
vmull_high_lane_s16neon
Multiply long
vmull_high_lane_s32neon
Multiply long
vmull_high_lane_u16neon
Multiply long
vmull_high_lane_u32neon
Multiply long
vmull_high_laneq_s16neon
Multiply long
vmull_high_laneq_s32neon
Multiply long
vmull_high_laneq_u16neon
Multiply long
vmull_high_laneq_u32neon
Multiply long
vmull_high_n_s16neon
Multiply long
vmull_high_n_s32neon
Multiply long
vmull_high_n_u16neon
Multiply long
vmull_high_n_u32neon
Multiply long
vmull_high_p8neon
Polynomial multiply long
vmull_high_p64neon,aes
Polynomial multiply long
vmull_high_s8neon
Signed multiply long
vmull_high_s16neon
Signed multiply long
vmull_high_s32neon
Signed multiply long
vmull_high_u8neon
Unsigned multiply long
vmull_high_u16neon
Unsigned multiply long
vmull_high_u32neon
Unsigned multiply long
vmull_p64neon,aes
Polynomial multiply long
vmulq_f64neon
Multiply
vmulq_lane_f64neon
Floating-point multiply
vmulq_laneq_f64neon
Floating-point multiply
vmulq_n_f64neon
Vector multiply by scalar
vmuls_lane_f32neon
Floating-point multiply
vmuls_laneq_f32neon
Floating-point multiply
vmulx_f32neon
Floating-point multiply extended
vmulx_f64neon
Floating-point multiply extended
vmulx_lane_f32neon
Floating-point multiply extended
vmulx_lane_f64neon
Floating-point multiply extended
vmulx_laneq_f32neon
Floating-point multiply extended
vmulx_laneq_f64neon
Floating-point multiply extended
vmulxd_f64neon
Floating-point multiply extended
vmulxd_lane_f64neon
Floating-point multiply extended
vmulxd_laneq_f64neon
Floating-point multiply extended
vmulxq_f32neon
Floating-point multiply extended
vmulxq_f64neon
Floating-point multiply extended
vmulxq_lane_f32neon
Floating-point multiply extended
vmulxq_lane_f64neon
Floating-point multiply extended
vmulxq_laneq_f32neon
Floating-point multiply extended
vmulxq_laneq_f64neon
Floating-point multiply extended
vmulxs_f32neon
Floating-point multiply extended
vmulxs_lane_f32neon
Floating-point multiply extended
vmulxs_laneq_f32neon
Floating-point multiply extended
vneg_f64neon
Negate
vneg_s64neon
Negate
vnegd_s64neon
Negate
vnegq_f64neon
Negate
vnegq_s64neon
Negate
vpaddd_f64neon
Floating-point add pairwise
vpaddd_s64neon
Add pairwise
vpaddd_u64neon
Add pairwise
vpaddq_f32neon
Floating-point add pairwise
vpaddq_f64neon
Floating-point add pairwise
vpaddq_s8neon
Add pairwise
vpaddq_s16neon
Add pairwise
vpaddq_s32neon
Add pairwise
vpaddq_s64neon
Add pairwise
vpaddq_u8neon
Add pairwise
vpaddq_u16neon
Add pairwise
vpaddq_u32neon
Add pairwise
vpaddq_u64neon
Add pairwise
vpadds_f32neon
Floating-point add pairwise
vpmaxnm_f32neon
Floating-point Maximum Number Pairwise (vector).
vpmaxnmq_f32neon
Floating-point Maximum Number Pairwise (vector).
vpmaxnmq_f64neon
Floating-point Maximum Number Pairwise (vector).
vpmaxnmqd_f64neon
Floating-point maximum number pairwise
vpmaxnms_f32neon
Floating-point maximum number pairwise
vpmaxq_f32neon
Folding maximum of adjacent pairs
vpmaxq_f64neon
Folding maximum of adjacent pairs
vpmaxq_s8neon
Folding maximum of adjacent pairs
vpmaxq_s16neon
Folding maximum of adjacent pairs
vpmaxq_s32neon
Folding maximum of adjacent pairs
vpmaxq_u8neon
Folding maximum of adjacent pairs
vpmaxq_u16neon
Folding maximum of adjacent pairs
vpmaxq_u32neon
Folding maximum of adjacent pairs
vpmaxqd_f64neon
Floating-point maximum pairwise
vpmaxs_f32neon
Floating-point maximum pairwise
vpminnm_f32neon
Floating-point Minimum Number Pairwise (vector).
vpminnmq_f32neon
Floating-point Minimum Number Pairwise (vector).
vpminnmq_f64neon
Floating-point Minimum Number Pairwise (vector).
vpminnmqd_f64neon
Floating-point minimum number pairwise
vpminnms_f32neon
Floating-point minimum number pairwise
vpminq_f32neon
Folding minimum of adjacent pairs
vpminq_f64neon
Folding minimum of adjacent pairs
vpminq_s8neon
Folding minimum of adjacent pairs
vpminq_s16neon
Folding minimum of adjacent pairs
vpminq_s32neon
Folding minimum of adjacent pairs
vpminq_u8neon
Folding minimum of adjacent pairs
vpminq_u16neon
Folding minimum of adjacent pairs
vpminq_u32neon
Folding minimum of adjacent pairs
vpminqd_f64neon
Floating-point minimum pairwise
vpmins_f32neon
Floating-point minimum pairwise
vqabs_s64neon
Signed saturating Absolute value
vqabsb_s8neon
Signed saturating absolute value
vqabsd_s64neon
Signed saturating absolute value
vqabsh_s16neon
Signed saturating absolute value
vqabsq_s64neon
Signed saturating Absolute value
vqabss_s32neon
Signed saturating absolute value
vqaddb_s8neon
Saturating add
vqaddb_u8neon
Saturating add
vqaddd_s64neon
Saturating add
vqaddd_u64neon
Saturating add
vqaddh_s16neon
Saturating add
vqaddh_u16neon
Saturating add
vqadds_s32neon
Saturating add
vqadds_u32neon
Saturating add
vqdmlal_high_lane_s16neon
Signed saturating doubling multiply-add long
vqdmlal_high_lane_s32neon
Signed saturating doubling multiply-add long
vqdmlal_high_laneq_s16neon
Signed saturating doubling multiply-add long
vqdmlal_high_laneq_s32neon
Signed saturating doubling multiply-add long
vqdmlal_high_n_s16neon
Signed saturating doubling multiply-add long
vqdmlal_high_n_s32neon
Signed saturating doubling multiply-add long
vqdmlal_high_s16neon
Signed saturating doubling multiply-add long
vqdmlal_high_s32neon
Signed saturating doubling multiply-add long
vqdmlal_laneq_s16neon
Vector widening saturating doubling multiply accumulate with scalar
vqdmlal_laneq_s32neon
Vector widening saturating doubling multiply accumulate with scalar
vqdmlalh_lane_s16neon
Signed saturating doubling multiply-add long
vqdmlalh_laneq_s16neon
Signed saturating doubling multiply-add long
vqdmlalh_s16neon
Signed saturating doubling multiply-add long
vqdmlals_lane_s32neon
Signed saturating doubling multiply-add long
vqdmlals_laneq_s32neon
Signed saturating doubling multiply-add long
vqdmlals_s32neon
Signed saturating doubling multiply-add long
vqdmlsl_high_lane_s16neon
Signed saturating doubling multiply-subtract long
vqdmlsl_high_lane_s32neon
Signed saturating doubling multiply-subtract long
vqdmlsl_high_laneq_s16neon
Signed saturating doubling multiply-subtract long
vqdmlsl_high_laneq_s32neon
Signed saturating doubling multiply-subtract long
vqdmlsl_high_n_s16neon
Signed saturating doubling multiply-subtract long
vqdmlsl_high_n_s32neon
Signed saturating doubling multiply-subtract long
vqdmlsl_high_s16neon
Signed saturating doubling multiply-subtract long
vqdmlsl_high_s32neon
Signed saturating doubling multiply-subtract long
vqdmlsl_laneq_s16neon
Vector widening saturating doubling multiply subtract with scalar
vqdmlsl_laneq_s32neon
Vector widening saturating doubling multiply subtract with scalar
vqdmlslh_lane_s16neon
Signed saturating doubling multiply-subtract long
vqdmlslh_laneq_s16neon
Signed saturating doubling multiply-subtract long
vqdmlslh_s16neon
Signed saturating doubling multiply-subtract long
vqdmlsls_lane_s32neon
Signed saturating doubling multiply-subtract long
vqdmlsls_laneq_s32neon
Signed saturating doubling multiply-subtract long
vqdmlsls_s32neon
Signed saturating doubling multiply-subtract long
vqdmulh_lane_s16neon
Vector saturating doubling multiply high by scalar
vqdmulh_lane_s32neon
Vector saturating doubling multiply high by scalar
vqdmulhh_lane_s16neon
Signed saturating doubling multiply returning high half
vqdmulhh_laneq_s16neon
Signed saturating doubling multiply returning high half
vqdmulhh_s16neon
Signed saturating doubling multiply returning high half
vqdmulhq_lane_s16neon
Vector saturating doubling multiply high by scalar
vqdmulhq_lane_s32neon
Vector saturating doubling multiply high by scalar
vqdmulhs_lane_s32neon
Signed saturating doubling multiply returning high half
vqdmulhs_laneq_s32neon
Signed saturating doubling multiply returning high half
vqdmulhs_s32neon
Signed saturating doubling multiply returning high half
vqdmull_high_lane_s16neon
Signed saturating doubling multiply long
vqdmull_high_lane_s32neon
Signed saturating doubling multiply long
vqdmull_high_laneq_s16neon
Signed saturating doubling multiply long
vqdmull_high_laneq_s32neon
Signed saturating doubling multiply long
vqdmull_high_n_s16neon
Signed saturating doubling multiply long
vqdmull_high_n_s32neon
Signed saturating doubling multiply long
vqdmull_high_s16neon
Signed saturating doubling multiply long
vqdmull_high_s32neon
Signed saturating doubling multiply long
vqdmull_laneq_s16neon
Vector saturating doubling long multiply by scalar
vqdmull_laneq_s32neon
Vector saturating doubling long multiply by scalar
vqdmullh_lane_s16neon
Signed saturating doubling multiply long
vqdmullh_laneq_s16neon
Signed saturating doubling multiply long
vqdmullh_s16neon
Signed saturating doubling multiply long
vqdmulls_lane_s32neon
Signed saturating doubling multiply long
vqdmulls_laneq_s32neon
Signed saturating doubling multiply long
vqdmulls_s32neon
Signed saturating doubling multiply long
vqmovn_high_s16neon
Signed saturating extract narrow
vqmovn_high_s32neon
Signed saturating extract narrow
vqmovn_high_s64neon
Signed saturating extract narrow
vqmovn_high_u16neon
Signed saturating extract narrow
vqmovn_high_u32neon
Signed saturating extract narrow
vqmovn_high_u64neon
Signed saturating extract narrow
vqmovnd_s64neon
Saturating extract narrow
vqmovnd_u64neon
Saturating extract narrow
vqmovnh_s16neon
Saturating extract narrow
vqmovnh_u16neon
Saturating extract narrow
vqmovns_s32neon
Saturating extract narrow
vqmovns_u32neon
Saturating extract narrow
vqmovun_high_s16neon
Signed saturating extract unsigned narrow
vqmovun_high_s32neon
Signed saturating extract unsigned narrow
vqmovun_high_s64neon
Signed saturating extract unsigned narrow
vqmovund_s64neon
Signed saturating extract unsigned narrow
vqmovunh_s16neon
Signed saturating extract unsigned narrow
vqmovuns_s32neon
Signed saturating extract unsigned narrow
vqneg_s64neon
Signed saturating negate
vqnegb_s8neon
Signed saturating negate
vqnegd_s64neon
Signed saturating negate
vqnegh_s16neon
Signed saturating negate
vqnegq_s64neon
Signed saturating negate
vqnegs_s32neon
Signed saturating negate
vqrdmlah_lane_s16rdm
Signed saturating rounding doubling multiply accumulate returning high half
vqrdmlah_lane_s32rdm
Signed saturating rounding doubling multiply accumulate returning high half
vqrdmlah_laneq_s16rdm
Signed saturating rounding doubling multiply accumulate returning high half
vqrdmlah_laneq_s32rdm
Signed saturating rounding doubling multiply accumulate returning high half
vqrdmlah_s16rdm
Signed saturating rounding doubling multiply accumulate returning high half
vqrdmlah_s32rdm
Signed saturating rounding doubling multiply accumulate returning high half
vqrdmlahh_lane_s16rdm
Signed saturating rounding doubling multiply accumulate returning high half
vqrdmlahh_laneq_s16rdm
Signed saturating rounding doubling multiply accumulate returning high half
vqrdmlahh_s16rdm
Signed saturating rounding doubling multiply accumulate returning high half
vqrdmlahq_lane_s16rdm
Signed saturating rounding doubling multiply accumulate returning high half
vqrdmlahq_lane_s32rdm
Signed saturating rounding doubling multiply accumulate returning high half
vqrdmlahq_laneq_s16rdm
Signed saturating rounding doubling multiply accumulate returning high half
vqrdmlahq_laneq_s32rdm
Signed saturating rounding doubling multiply accumulate returning high half
vqrdmlahq_s16rdm
Signed saturating rounding doubling multiply accumulate returning high half
vqrdmlahq_s32rdm
Signed saturating rounding doubling multiply accumulate returning high half
vqrdmlahs_lane_s32rdm
Signed saturating rounding doubling multiply accumulate returning high half
vqrdmlahs_laneq_s32rdm
Signed saturating rounding doubling multiply accumulate returning high half
vqrdmlahs_s32rdm
Signed saturating rounding doubling multiply accumulate returning high half
vqrdmlsh_lane_s16rdm
Signed saturating rounding doubling multiply subtract returning high half
vqrdmlsh_lane_s32rdm
Signed saturating rounding doubling multiply subtract returning high half
vqrdmlsh_laneq_s16rdm
Signed saturating rounding doubling multiply subtract returning high half
vqrdmlsh_laneq_s32rdm
Signed saturating rounding doubling multiply subtract returning high half
vqrdmlsh_s16rdm
Signed saturating rounding doubling multiply subtract returning high half
vqrdmlsh_s32rdm
Signed saturating rounding doubling multiply subtract returning high half
vqrdmlshh_lane_s16rdm
Signed saturating rounding doubling multiply subtract returning high half
vqrdmlshh_laneq_s16rdm
Signed saturating rounding doubling multiply subtract returning high half
vqrdmlshh_s16rdm
Signed saturating rounding doubling multiply subtract returning high half
vqrdmlshq_lane_s16rdm
Signed saturating rounding doubling multiply subtract returning high half
vqrdmlshq_lane_s32rdm
Signed saturating rounding doubling multiply subtract returning high half
vqrdmlshq_laneq_s16rdm
Signed saturating rounding doubling multiply subtract returning high half
vqrdmlshq_laneq_s32rdm
Signed saturating rounding doubling multiply subtract returning high half
vqrdmlshq_s16rdm
Signed saturating rounding doubling multiply subtract returning high half
vqrdmlshq_s32rdm
Signed saturating rounding doubling multiply subtract returning high half
vqrdmlshs_lane_s32rdm
Signed saturating rounding doubling multiply subtract returning high half
vqrdmlshs_laneq_s32rdm
Signed saturating rounding doubling multiply subtract returning high half
vqrdmlshs_s32rdm
Signed saturating rounding doubling multiply subtract returning high half
vqrdmulhh_lane_s16neon
Signed saturating rounding doubling multiply returning high half
vqrdmulhh_laneq_s16neon
Signed saturating rounding doubling multiply returning high half
vqrdmulhh_s16neon
Signed saturating rounding doubling multiply returning high half
vqrdmulhs_lane_s32neon
Signed saturating rounding doubling multiply returning high half
vqrdmulhs_laneq_s32neon
Signed saturating rounding doubling multiply returning high half
vqrdmulhs_s32neon
Signed saturating rounding doubling multiply returning high half
vqrshlb_s8neon
Signed saturating rounding shift left
vqrshlb_u8neon
Unsigned signed saturating rounding shift left
vqrshld_s64neon
Signed saturating rounding shift left
vqrshld_u64neon
Unsigned signed saturating rounding shift left
vqrshlh_s16neon
Signed saturating rounding shift left
vqrshlh_u16neon
Unsigned signed saturating rounding shift left
vqrshls_s32neon
Signed saturating rounding shift left
vqrshls_u32neon
Unsigned signed saturating rounding shift left
vqrshrn_high_n_s16neon
Signed saturating rounded shift right narrow
vqrshrn_high_n_s32neon
Signed saturating rounded shift right narrow
vqrshrn_high_n_s64neon
Signed saturating rounded shift right narrow
vqrshrn_high_n_u16neon
Unsigned saturating rounded shift right narrow
vqrshrn_high_n_u32neon
Unsigned saturating rounded shift right narrow
vqrshrn_high_n_u64neon
Unsigned saturating rounded shift right narrow
vqrshrnd_n_s64neon
Signed saturating rounded shift right narrow
vqrshrnd_n_u64neon
Unsigned saturating rounded shift right narrow
vqrshrnh_n_s16neon
Signed saturating rounded shift right narrow
vqrshrnh_n_u16neon
Unsigned saturating rounded shift right narrow
vqrshrns_n_s32neon
Signed saturating rounded shift right narrow
vqrshrns_n_u32neon
Unsigned saturating rounded shift right narrow
vqrshrun_high_n_s16neon
Signed saturating rounded shift right unsigned narrow
vqrshrun_high_n_s32neon
Signed saturating rounded shift right unsigned narrow
vqrshrun_high_n_s64neon
Signed saturating rounded shift right unsigned narrow
vqrshrund_n_s64neon
Signed saturating rounded shift right unsigned narrow
vqrshrunh_n_s16neon
Signed saturating rounded shift right unsigned narrow
vqrshruns_n_s32neon
Signed saturating rounded shift right unsigned narrow
vqshlb_n_s8neon
Signed saturating shift left
vqshlb_n_u8neon
Unsigned saturating shift left
vqshlb_s8neon
Signed saturating shift left
vqshlb_u8neon
Unsigned saturating shift left
vqshld_n_s64neon
Signed saturating shift left
vqshld_n_u64neon
Unsigned saturating shift left
vqshld_s64neon
Signed saturating shift left
vqshld_u64neon
Unsigned saturating shift left
vqshlh_n_s16neon
Signed saturating shift left
vqshlh_n_u16neon
Unsigned saturating shift left
vqshlh_s16neon
Signed saturating shift left
vqshlh_u16neon
Unsigned saturating shift left
vqshls_n_s32neon
Signed saturating shift left
vqshls_n_u32neon
Unsigned saturating shift left
vqshls_s32neon
Signed saturating shift left
vqshls_u32neon
Unsigned saturating shift left
vqshlub_n_s8neon
Signed saturating shift left unsigned
vqshlud_n_s64neon
Signed saturating shift left unsigned
vqshluh_n_s16neon
Signed saturating shift left unsigned
vqshlus_n_s32neon
Signed saturating shift left unsigned
vqshrn_high_n_s16neon
Signed saturating shift right narrow
vqshrn_high_n_s32neon
Signed saturating shift right narrow
vqshrn_high_n_s64neon
Signed saturating shift right narrow
vqshrn_high_n_u16neon
Unsigned saturating shift right narrow
vqshrn_high_n_u32neon
Unsigned saturating shift right narrow
vqshrn_high_n_u64neon
Unsigned saturating shift right narrow
vqshrnd_n_s64neon
Signed saturating shift right narrow
vqshrnd_n_u64neon
Unsigned saturating shift right narrow
vqshrnh_n_s16neon
Signed saturating shift right narrow
vqshrnh_n_u16neon
Unsigned saturating shift right narrow
vqshrns_n_s32neon
Signed saturating shift right narrow
vqshrns_n_u32neon
Unsigned saturating shift right narrow
vqshrun_high_n_s16neon
Signed saturating shift right unsigned narrow
vqshrun_high_n_s32neon
Signed saturating shift right unsigned narrow
vqshrun_high_n_s64neon
Signed saturating shift right unsigned narrow
vqshrund_n_s64neon
Signed saturating shift right unsigned narrow
vqshrunh_n_s16neon
Signed saturating shift right unsigned narrow
vqshruns_n_s32neon
Signed saturating shift right unsigned narrow
vqsubb_s8neon
Saturating subtract
vqsubb_u8neon
Saturating subtract
vqsubd_s64neon
Saturating subtract
vqsubd_u64neon
Saturating subtract
vqsubh_s16neon
Saturating subtract
vqsubh_u16neon
Saturating subtract
vqsubs_s32neon
Saturating subtract
vqsubs_u32neon
Saturating subtract
vqtbl1_p8neon
Table look-up
vqtbl1_s8neon
Table look-up
vqtbl1_u8neon
Table look-up
vqtbl1q_p8neon
Table look-up
vqtbl1q_s8neon
Table look-up
vqtbl1q_u8neon
Table look-up
vqtbl2_p8neon
Table look-up
vqtbl2_s8neon
Table look-up
vqtbl2_u8neon
Table look-up
vqtbl2q_p8neon
Table look-up
vqtbl2q_s8neon
Table look-up
vqtbl2q_u8neon
Table look-up
vqtbl3_p8neon
Table look-up
vqtbl3_s8neon
Table look-up
vqtbl3_u8neon
Table look-up
vqtbl3q_p8neon
Table look-up
vqtbl3q_s8neon
Table look-up
vqtbl3q_u8neon
Table look-up
vqtbl4_p8neon
Table look-up
vqtbl4_s8neon
Table look-up
vqtbl4_u8neon
Table look-up
vqtbl4q_p8neon
Table look-up
vqtbl4q_s8neon
Table look-up
vqtbl4q_u8neon
Table look-up
vqtbx1_p8neon
Extended table look-up
vqtbx1_s8neon
Extended table look-up
vqtbx1_u8neon
Extended table look-up
vqtbx1q_p8neon
Extended table look-up
vqtbx1q_s8neon
Extended table look-up
vqtbx1q_u8neon
Extended table look-up
vqtbx2_p8neon
Extended table look-up
vqtbx2_s8neon
Extended table look-up
vqtbx2_u8neon
Extended table look-up
vqtbx2q_p8neon
Extended table look-up
vqtbx2q_s8neon
Extended table look-up
vqtbx2q_u8neon
Extended table look-up
vqtbx3_p8neon
Extended table look-up
vqtbx3_s8neon
Extended table look-up
vqtbx3_u8neon
Extended table look-up
vqtbx3q_p8neon
Extended table look-up
vqtbx3q_s8neon
Extended table look-up
vqtbx3q_u8neon
Extended table look-up
vqtbx4_p8neon
Extended table look-up
vqtbx4_s8neon
Extended table look-up
vqtbx4_u8neon
Extended table look-up
vqtbx4q_p8neon
Extended table look-up
vqtbx4q_s8neon
Extended table look-up
vqtbx4q_u8neon
Extended table look-up
vrax1q_u64neon,sha3
Rotate and exclusive OR
vrbit_p8neon
Reverse bit order
vrbit_s8neon
Reverse bit order
vrbit_u8neon
Reverse bit order
vrbitq_p8neon
Reverse bit order
vrbitq_s8neon
Reverse bit order
vrbitq_u8neon
Reverse bit order
vrecpe_f64neon
Reciprocal estimate.
vrecped_f64neon
Reciprocal estimate.
vrecpeq_f64neon
Reciprocal estimate.
vrecpes_f32neon
Reciprocal estimate.
vrecps_f64neon
Floating-point reciprocal step
vrecpsd_f64neon
Floating-point reciprocal step
vrecpsq_f64neon
Floating-point reciprocal step
vrecpss_f32neon
Floating-point reciprocal step
vrecpxd_f64neon
Floating-point reciprocal exponent
vrecpxs_f32neon
Floating-point reciprocal exponent
vreinterpret_f32_f64neon
Vector reinterpret cast operation
vreinterpret_f32_p64neon
Vector reinterpret cast operation
vreinterpret_f64_f32neon
Vector reinterpret cast operation
vreinterpret_f64_p8neon
Vector reinterpret cast operation
vreinterpret_f64_p16neon
Vector reinterpret cast operation
vreinterpret_f64_p64neon
Vector reinterpret cast operation
vreinterpret_f64_s8neon
Vector reinterpret cast operation
vreinterpret_f64_s16neon
Vector reinterpret cast operation
vreinterpret_f64_s32neon
Vector reinterpret cast operation
vreinterpret_f64_s64neon
Vector reinterpret cast operation
vreinterpret_f64_u8neon
Vector reinterpret cast operation
vreinterpret_f64_u16neon
Vector reinterpret cast operation
vreinterpret_f64_u32neon
Vector reinterpret cast operation
vreinterpret_f64_u64neon
Vector reinterpret cast operation
vreinterpret_p8_f64neon
Vector reinterpret cast operation
vreinterpret_p16_f64neon
Vector reinterpret cast operation
vreinterpret_p64_f32neon
Vector reinterpret cast operation
vreinterpret_p64_f64neon
Vector reinterpret cast operation
vreinterpret_p64_s64neon
Vector reinterpret cast operation
vreinterpret_p64_u64neon
Vector reinterpret cast operation
vreinterpret_s8_f64neon
Vector reinterpret cast operation
vreinterpret_s16_f64neon
Vector reinterpret cast operation
vreinterpret_s32_f64neon
Vector reinterpret cast operation
vreinterpret_s64_f64neon
Vector reinterpret cast operation
vreinterpret_s64_p64neon
Vector reinterpret cast operation
vreinterpret_u8_f64neon
Vector reinterpret cast operation
vreinterpret_u16_f64neon
Vector reinterpret cast operation
vreinterpret_u32_f64neon
Vector reinterpret cast operation
vreinterpret_u64_f64neon
Vector reinterpret cast operation
vreinterpret_u64_p64neon
Vector reinterpret cast operation
vreinterpretq_f32_f64neon
Vector reinterpret cast operation
vreinterpretq_f32_p64neon
Vector reinterpret cast operation
vreinterpretq_f64_f32neon
Vector reinterpret cast operation
vreinterpretq_f64_p8neon
Vector reinterpret cast operation
vreinterpretq_f64_p16neon
Vector reinterpret cast operation
vreinterpretq_f64_p64neon
Vector reinterpret cast operation
vreinterpretq_f64_p128neon
Vector reinterpret cast operation
vreinterpretq_f64_s8neon
Vector reinterpret cast operation
vreinterpretq_f64_s16neon
Vector reinterpret cast operation
vreinterpretq_f64_s32neon
Vector reinterpret cast operation
vreinterpretq_f64_s64neon
Vector reinterpret cast operation
vreinterpretq_f64_u8neon
Vector reinterpret cast operation
vreinterpretq_f64_u16neon
Vector reinterpret cast operation
vreinterpretq_f64_u32neon
Vector reinterpret cast operation
vreinterpretq_f64_u64neon
Vector reinterpret cast operation
vreinterpretq_p8_f64neon
Vector reinterpret cast operation
vreinterpretq_p16_f64neon
Vector reinterpret cast operation
vreinterpretq_p64_f32neon
Vector reinterpret cast operation
vreinterpretq_p64_f64neon
Vector reinterpret cast operation
vreinterpretq_p64_s64neon
Vector reinterpret cast operation
vreinterpretq_p64_u64neon
Vector reinterpret cast operation
vreinterpretq_p128_f64neon
Vector reinterpret cast operation
vreinterpretq_s8_f64neon
Vector reinterpret cast operation
vreinterpretq_s16_f64neon
Vector reinterpret cast operation
vreinterpretq_s32_f64neon
Vector reinterpret cast operation
vreinterpretq_s64_f64neon
Vector reinterpret cast operation
vreinterpretq_s64_p64neon
Vector reinterpret cast operation
vreinterpretq_u8_f64neon
Vector reinterpret cast operation
vreinterpretq_u16_f64neon
Vector reinterpret cast operation
vreinterpretq_u32_f64neon
Vector reinterpret cast operation
vreinterpretq_u64_f64neon
Vector reinterpret cast operation
vreinterpretq_u64_p64neon
Vector reinterpret cast operation
vrnd_f32neon
Floating-point round to integral, toward zero
vrnd_f64neon
Floating-point round to integral, toward zero
vrnda_f32neon
Floating-point round to integral, to nearest with ties to away
vrnda_f64neon
Floating-point round to integral, to nearest with ties to away
vrndaq_f32neon
Floating-point round to integral, to nearest with ties to away
vrndaq_f64neon
Floating-point round to integral, to nearest with ties to away
vrndi_f32neon
Floating-point round to integral, using current rounding mode
vrndi_f64neon
Floating-point round to integral, using current rounding mode
vrndiq_f32neon
Floating-point round to integral, using current rounding mode
vrndiq_f64neon
Floating-point round to integral, using current rounding mode
vrndm_f32neon
Floating-point round to integral, toward minus infinity
vrndm_f64neon
Floating-point round to integral, toward minus infinity
vrndmq_f32neon
Floating-point round to integral, toward minus infinity
vrndmq_f64neon
Floating-point round to integral, toward minus infinity
vrndn_f64neon
Floating-point round to integral, to nearest with ties to even
vrndnq_f64neon
Floating-point round to integral, to nearest with ties to even
vrndns_f32neon
Floating-point round to integral, to nearest with ties to even
vrndp_f32neon
Floating-point round to integral, toward plus infinity
vrndp_f64neon
Floating-point round to integral, toward plus infinity
vrndpq_f32neon
Floating-point round to integral, toward plus infinity
vrndpq_f64neon
Floating-point round to integral, toward plus infinity
vrndq_f32neon
Floating-point round to integral, toward zero
vrndq_f64neon
Floating-point round to integral, toward zero
vrndx_f32neon
Floating-point round to integral exact, using current rounding mode
vrndx_f64neon
Floating-point round to integral exact, using current rounding mode
vrndxq_f32neon
Floating-point round to integral exact, using current rounding mode
vrndxq_f64neon
Floating-point round to integral exact, using current rounding mode
vrshld_s64neon
Signed rounding shift left
vrshld_u64neon
Unsigned rounding shift left
vrshrd_n_s64neon
Signed rounding shift right
vrshrd_n_u64neon
Unsigned rounding shift right
vrshrn_high_n_s16neon
Rounding shift right narrow
vrshrn_high_n_s32neon
Rounding shift right narrow
vrshrn_high_n_s64neon
Rounding shift right narrow
vrshrn_high_n_u16neon
Rounding shift right narrow
vrshrn_high_n_u32neon
Rounding shift right narrow
vrshrn_high_n_u64neon
Rounding shift right narrow
vrsqrte_f64neon
Reciprocal square-root estimate.
vrsqrted_f64neon
Reciprocal square-root estimate.
vrsqrteq_f64neon
Reciprocal square-root estimate.
vrsqrtes_f32neon
Reciprocal square-root estimate.
vrsqrts_f64neon
Floating-point reciprocal square root step
vrsqrtsd_f64neon
Floating-point reciprocal square root step
vrsqrtsq_f64neon
Floating-point reciprocal square root step
vrsqrtss_f32neon
Floating-point reciprocal square root step
vrsrad_n_s64neon
Signed rounding shift right and accumulate.
vrsrad_n_u64neon
Unsigned rounding shift right and accumulate.
vrsubhn_high_s16neon
Rounding subtract returning high narrow
vrsubhn_high_s32neon
Rounding subtract returning high narrow
vrsubhn_high_s64neon
Rounding subtract returning high narrow
vrsubhn_high_u16neon
Rounding subtract returning high narrow
vrsubhn_high_u32neon
Rounding subtract returning high narrow
vrsubhn_high_u64neon
Rounding subtract returning high narrow
vset_lane_f64neon
Insert vector element from another vector element
vsetq_lane_f64neon
Insert vector element from another vector element
vsha512h2q_u64neon,sha3
SHA512 hash update part 2
vsha512hq_u64neon,sha3
SHA512 hash update part 1
vsha512su0q_u64neon,sha3
SHA512 schedule update 0
vsha512su1q_u64neon,sha3
SHA512 schedule update 1
vshld_n_s64neon
Shift left
vshld_n_u64neon
Shift left
vshld_s64neon
Signed Shift left
vshld_u64neon
Unsigned Shift left
vshll_high_n_s8neon
Signed shift left long
vshll_high_n_s16neon
Signed shift left long
vshll_high_n_s32neon
Signed shift left long
vshll_high_n_u8neon
Signed shift left long
vshll_high_n_u16neon
Signed shift left long
vshll_high_n_u32neon
Signed shift left long
vshrd_n_s64neon
Signed shift right
vshrd_n_u64neon
Unsigned shift right
vshrn_high_n_s16neon
Shift right narrow
vshrn_high_n_s32neon
Shift right narrow
vshrn_high_n_s64neon
Shift right narrow
vshrn_high_n_u16neon
Shift right narrow
vshrn_high_n_u32neon
Shift right narrow
vshrn_high_n_u64neon
Shift right narrow
vsli_n_p8neon
Shift Left and Insert (immediate)
vsli_n_p16neon
Shift Left and Insert (immediate)
vsli_n_p64neon,aes
Shift Left and Insert (immediate)
vsli_n_s8neon
Shift Left and Insert (immediate)
vsli_n_s16neon
Shift Left and Insert (immediate)
vsli_n_s32neon
Shift Left and Insert (immediate)
vsli_n_s64neon
Shift Left and Insert (immediate)
vsli_n_u8neon
Shift Left and Insert (immediate)
vsli_n_u16neon
Shift Left and Insert (immediate)
vsli_n_u32neon
Shift Left and Insert (immediate)
vsli_n_u64neon
Shift Left and Insert (immediate)
vslid_n_s64neon
Shift left and insert
vslid_n_u64neon
Shift left and insert
vsliq_n_p8neon
Shift Left and Insert (immediate)
vsliq_n_p16neon
Shift Left and Insert (immediate)
vsliq_n_p64neon,aes
Shift Left and Insert (immediate)
vsliq_n_s8neon
Shift Left and Insert (immediate)
vsliq_n_s16neon
Shift Left and Insert (immediate)
vsliq_n_s32neon
Shift Left and Insert (immediate)
vsliq_n_s64neon
Shift Left and Insert (immediate)
vsliq_n_u8neon
Shift Left and Insert (immediate)
vsliq_n_u16neon
Shift Left and Insert (immediate)
vsliq_n_u32neon
Shift Left and Insert (immediate)
vsliq_n_u64neon
Shift Left and Insert (immediate)
vsqadd_u8neon
Unsigned saturating Accumulate of Signed value.
vsqadd_u16neon
Unsigned saturating Accumulate of Signed value.
vsqadd_u32neon
Unsigned saturating Accumulate of Signed value.
vsqadd_u64neon
Unsigned saturating Accumulate of Signed value.
vsqaddb_u8neon
Unsigned saturating accumulate of signed value
vsqaddd_u64neon
Unsigned saturating accumulate of signed value
vsqaddh_u16neon
Unsigned saturating accumulate of signed value
vsqaddq_u8neon
Unsigned saturating Accumulate of Signed value.
vsqaddq_u16neon
Unsigned saturating Accumulate of Signed value.
vsqaddq_u32neon
Unsigned saturating Accumulate of Signed value.
vsqaddq_u64neon
Unsigned saturating Accumulate of Signed value.
vsqadds_u32neon
Unsigned saturating accumulate of signed value
vsqrt_f32neon
Calculates the square root of each lane.
vsqrt_f64neon
Calculates the square root of each lane.
vsqrtq_f32neon
Calculates the square root of each lane.
vsqrtq_f64neon
Calculates the square root of each lane.
vsrad_n_s64neon
Signed shift right and accumulate
vsrad_n_u64neon
Unsigned shift right and accumulate
vsri_n_p8neon
Shift Right and Insert (immediate)
vsri_n_p16neon
Shift Right and Insert (immediate)
vsri_n_p64neon,aes
Shift Right and Insert (immediate)
vsri_n_s8neon
Shift Right and Insert (immediate)
vsri_n_s16neon
Shift Right and Insert (immediate)
vsri_n_s32neon
Shift Right and Insert (immediate)
vsri_n_s64neon
Shift Right and Insert (immediate)
vsri_n_u8neon
Shift Right and Insert (immediate)
vsri_n_u16neon
Shift Right and Insert (immediate)
vsri_n_u32neon
Shift Right and Insert (immediate)
vsri_n_u64neon
Shift Right and Insert (immediate)
vsrid_n_s64neon
Shift right and insert
vsrid_n_u64neon
Shift right and insert
vsriq_n_p8neon
Shift Right and Insert (immediate)
vsriq_n_p16neon
Shift Right and Insert (immediate)
vsriq_n_p64neon,aes
Shift Right and Insert (immediate)
vsriq_n_s8neon
Shift Right and Insert (immediate)
vsriq_n_s16neon
Shift Right and Insert (immediate)
vsriq_n_s32neon
Shift Right and Insert (immediate)
vsriq_n_s64neon
Shift Right and Insert (immediate)
vsriq_n_u8neon
Shift Right and Insert (immediate)
vsriq_n_u16neon
Shift Right and Insert (immediate)
vsriq_n_u32neon
Shift Right and Insert (immediate)
vsriq_n_u64neon
Shift Right and Insert (immediate)
vst1_f32neon
vst1_f64neon
vst1_f64_x2neon
Store multiple single-element structures to one, two, three, or four registers
vst1_f64_x3neon
Store multiple single-element structures to one, two, three, or four registers
vst1_f64_x4neon
Store multiple single-element structures to one, two, three, or four registers
vst1_lane_f64neon
Store multiple single-element structures from one, two, three, or four registers
vst1_p8neon
Store multiple single-element structures from one, two, three, or four registers.
vst1_p16neon
Store multiple single-element structures from one, two, three, or four registers.
vst1_p64neon,aes
Arm’s documentation
vst1_s8neon
Store multiple single-element structures from one, two, three, or four registers.
vst1_s16neon
Store multiple single-element structures from one, two, three, or four registers.
vst1_s32neon
Store multiple single-element structures from one, two, three, or four registers.
vst1_s64neon
Store multiple single-element structures from one, two, three, or four registers.
vst1_u8neon
Store multiple single-element structures from one, two, three, or four registers.
vst1_u16neon
Store multiple single-element structures from one, two, three, or four registers.
vst1_u32neon
Store multiple single-element structures from one, two, three, or four registers.
vst1_u64neon
Store multiple single-element structures from one, two, three, or four registers.
vst1q_f32neon
vst1q_f64neon
vst1q_f64_x2neon
Store multiple single-element structures to one, two, three, or four registers
vst1q_f64_x3neon
Store multiple single-element structures to one, two, three, or four registers
vst1q_f64_x4neon
Store multiple single-element structures to one, two, three, or four registers
vst1q_lane_f64neon
Store multiple single-element structures from one, two, three, or four registers
vst1q_p8neon
Store multiple single-element structures from one, two, three, or four registers.
vst1q_p16neon
Store multiple single-element structures from one, two, three, or four registers.
vst1q_p64neon,aes
Arm’s documentation
vst1q_s8neon
Store multiple single-element structures from one, two, three, or four registers.
vst1q_s16neon
Store multiple single-element structures from one, two, three, or four registers.
vst1q_s32neon
Store multiple single-element structures from one, two, three, or four registers.
vst1q_s64neon
Store multiple single-element structures from one, two, three, or four registers.
vst1q_u8neon
Store multiple single-element structures from one, two, three, or four registers.
vst1q_u16neon
Store multiple single-element structures from one, two, three, or four registers.
vst1q_u32neon
Store multiple single-element structures from one, two, three, or four registers.
vst1q_u64neon
Store multiple single-element structures from one, two, three, or four registers.
vst2_f64neon
Store multiple 2-element structures from two registers
vst2_lane_f64neon
Store multiple 2-element structures from two registers
vst2_lane_p64neon,aes
Store multiple 2-element structures from two registers
vst2_lane_s64neon
Store multiple 2-element structures from two registers
vst2_lane_u64neon
Store multiple 2-element structures from two registers
vst2q_f64neon
Store multiple 2-element structures from two registers
vst2q_lane_f64neon
Store multiple 2-element structures from two registers
vst2q_lane_p8neon
Store multiple 2-element structures from two registers
vst2q_lane_p64neon,aes
Store multiple 2-element structures from two registers
vst2q_lane_s8neon
Store multiple 2-element structures from two registers
vst2q_lane_s64neon
Store multiple 2-element structures from two registers
vst2q_lane_u8neon
Store multiple 2-element structures from two registers
vst2q_lane_u64neon
Store multiple 2-element structures from two registers
vst2q_p64neon,aes
Store multiple 2-element structures from two registers
vst2q_s64neon
Store multiple 2-element structures from two registers
vst2q_u64neon
Store multiple 2-element structures from two registers
vst3_f64neon
Store multiple 3-element structures from three registers
vst3_lane_f64neon
Store multiple 3-element structures from three registers
vst3_lane_p64neon,aes
Store multiple 3-element structures from three registers
vst3_lane_s64neon
Store multiple 3-element structures from three registers
vst3_lane_u64neon
Store multiple 3-element structures from three registers
vst3q_f64neon
Store multiple 3-element structures from three registers
vst3q_lane_f64neon
Store multiple 3-element structures from three registers
vst3q_lane_p8neon
Store multiple 3-element structures from three registers
vst3q_lane_p64neon,aes
Store multiple 3-element structures from three registers
vst3q_lane_s8neon
Store multiple 3-element structures from three registers
vst3q_lane_s64neon
Store multiple 3-element structures from three registers
vst3q_lane_u8neon
Store multiple 3-element structures from three registers
vst3q_lane_u64neon
Store multiple 3-element structures from three registers
vst3q_p64neon,aes
Store multiple 3-element structures from three registers
vst3q_s64neon
Store multiple 3-element structures from three registers
vst3q_u64neon
Store multiple 3-element structures from three registers
vst4_f64neon
Store multiple 4-element structures from four registers
vst4_lane_f64neon
Store multiple 4-element structures from four registers
vst4_lane_p64neon,aes
Store multiple 4-element structures from four registers
vst4_lane_s64neon
Store multiple 4-element structures from four registers
vst4_lane_u64neon
Store multiple 4-element structures from four registers
vst4q_f64neon
Store multiple 4-element structures from four registers
vst4q_lane_f64neon
Store multiple 4-element structures from four registers
vst4q_lane_p8neon
Store multiple 4-element structures from four registers
vst4q_lane_p64neon,aes
Store multiple 4-element structures from four registers
vst4q_lane_s8neon
Store multiple 4-element structures from four registers
vst4q_lane_s64neon
Store multiple 4-element structures from four registers
vst4q_lane_u8neon
Store multiple 4-element structures from four registers
vst4q_lane_u64neon
Store multiple 4-element structures from four registers
vst4q_p64neon,aes
Store multiple 4-element structures from four registers
vst4q_s64neon
Store multiple 4-element structures from four registers
vst4q_u64neon
Store multiple 4-element structures from four registers
vsub_f64neon
Subtract
vsubd_s64neon
Subtract
vsubd_u64neon
Subtract
vsubl_high_s8neon
Signed Subtract Long
vsubl_high_s16neon
Signed Subtract Long
vsubl_high_s32neon
Signed Subtract Long
vsubl_high_u8neon
Unsigned Subtract Long
vsubl_high_u16neon
Unsigned Subtract Long
vsubl_high_u32neon
Unsigned Subtract Long
vsubq_f64neon
Subtract
vsubw_high_s8neon
Signed Subtract Wide
vsubw_high_s16neon
Signed Subtract Wide
vsubw_high_s32neon
Signed Subtract Wide
vsubw_high_u8neon
Unsigned Subtract Wide
vsubw_high_u16neon
Unsigned Subtract Wide
vsubw_high_u32neon
Unsigned Subtract Wide
vtbl1_p8neon
Table look-up
vtbl1_s8neon
Table look-up
vtbl1_u8neon
Table look-up
vtbl2_p8neon
Table look-up
vtbl2_s8neon
Table look-up
vtbl2_u8neon
Table look-up
vtbl3_p8neon
Table look-up
vtbl3_s8neon
Table look-up
vtbl3_u8neon
Table look-up
vtbl4_p8neon
Table look-up
vtbl4_s8neon
Table look-up
vtbl4_u8neon
Table look-up
vtbx1_p8neon
Extended table look-up
vtbx1_s8neon
Extended table look-up
vtbx1_u8neon
Extended table look-up
vtbx2_p8neon
Extended table look-up
vtbx2_s8neon
Extended table look-up
vtbx2_u8neon
Extended table look-up
vtbx3_p8neon
Extended table look-up
vtbx3_s8neon
Extended table look-up
vtbx3_u8neon
Extended table look-up
vtbx4_p8neon
Extended table look-up
vtbx4_s8neon
Extended table look-up
vtbx4_u8neon
Extended table look-up
vtrn1_f32neon
Transpose vectors
vtrn1_p8neon
Transpose vectors
vtrn1_p16neon
Transpose vectors
vtrn1_s8neon
Transpose vectors
vtrn1_s16neon
Transpose vectors
vtrn1_s32neon
Transpose vectors
vtrn1_u8neon
Transpose vectors
vtrn1_u16neon
Transpose vectors
vtrn1_u32neon
Transpose vectors
vtrn1q_f32neon
Transpose vectors
vtrn1q_f64neon
Transpose vectors
vtrn1q_p8neon
Transpose vectors
vtrn1q_p16neon
Transpose vectors
vtrn1q_p64neon
Transpose vectors
vtrn1q_s8neon
Transpose vectors
vtrn1q_s16neon
Transpose vectors
vtrn1q_s32neon
Transpose vectors
vtrn1q_s64neon
Transpose vectors
vtrn1q_u8neon
Transpose vectors
vtrn1q_u16neon
Transpose vectors
vtrn1q_u32neon
Transpose vectors
vtrn1q_u64neon
Transpose vectors
vtrn2_f32neon
Transpose vectors
vtrn2_p8neon
Transpose vectors
vtrn2_p16neon
Transpose vectors
vtrn2_s8neon
Transpose vectors
vtrn2_s16neon
Transpose vectors
vtrn2_s32neon
Transpose vectors
vtrn2_u8neon
Transpose vectors
vtrn2_u16neon
Transpose vectors
vtrn2_u32neon
Transpose vectors
vtrn2q_f32neon
Transpose vectors
vtrn2q_f64neon
Transpose vectors
vtrn2q_p8neon
Transpose vectors
vtrn2q_p16neon
Transpose vectors
vtrn2q_p64neon
Transpose vectors
vtrn2q_s8neon
Transpose vectors
vtrn2q_s16neon
Transpose vectors
vtrn2q_s32neon
Transpose vectors
vtrn2q_s64neon
Transpose vectors
vtrn2q_u8neon
Transpose vectors
vtrn2q_u16neon
Transpose vectors
vtrn2q_u32neon
Transpose vectors
vtrn2q_u64neon
Transpose vectors
vtst_p64neon
Signed compare bitwise Test bits nonzero
vtst_s64neon
Signed compare bitwise Test bits nonzero
vtst_u64neon
Unsigned compare bitwise Test bits nonzero
vtstd_s64neon
Compare bitwise test bits nonzero
vtstd_u64neon
Compare bitwise test bits nonzero
vtstq_p64neon
Signed compare bitwise Test bits nonzero
vtstq_s64neon
Signed compare bitwise Test bits nonzero
vtstq_u64neon
Unsigned compare bitwise Test bits nonzero
vuqadd_s8neon
Signed saturating Accumulate of Unsigned value.
vuqadd_s16neon
Signed saturating Accumulate of Unsigned value.
vuqadd_s32neon
Signed saturating Accumulate of Unsigned value.
vuqadd_s64neon
Signed saturating Accumulate of Unsigned value.
vuqaddb_s8neon
Signed saturating accumulate of unsigned value
vuqaddd_s64neon
Signed saturating accumulate of unsigned value
vuqaddh_s16neon
Signed saturating accumulate of unsigned value
vuqaddq_s8neon
Signed saturating Accumulate of Unsigned value.
vuqaddq_s16neon
Signed saturating Accumulate of Unsigned value.
vuqaddq_s32neon
Signed saturating Accumulate of Unsigned value.
vuqaddq_s64neon
Signed saturating Accumulate of Unsigned value.
vuqadds_s32neon
Signed saturating accumulate of unsigned value
vuzp1_f32neon
Unzip vectors
vuzp1_p8neon
Unzip vectors
vuzp1_p16neon
Unzip vectors
vuzp1_s8neon
Unzip vectors
vuzp1_s16neon
Unzip vectors
vuzp1_s32neon
Unzip vectors
vuzp1_u8neon
Unzip vectors
vuzp1_u16neon
Unzip vectors
vuzp1_u32neon
Unzip vectors
vuzp1q_f32neon
Unzip vectors
vuzp1q_f64neon
Unzip vectors
vuzp1q_p8neon
Unzip vectors
vuzp1q_p16neon
Unzip vectors
vuzp1q_p64neon
Unzip vectors
vuzp1q_s8neon
Unzip vectors
vuzp1q_s16neon
Unzip vectors
vuzp1q_s32neon
Unzip vectors
vuzp1q_s64neon
Unzip vectors
vuzp1q_u8neon
Unzip vectors
vuzp1q_u16neon
Unzip vectors
vuzp1q_u32neon
Unzip vectors
vuzp1q_u64neon
Unzip vectors
vuzp2_f32neon
Unzip vectors
vuzp2_p8neon
Unzip vectors
vuzp2_p16neon
Unzip vectors
vuzp2_s8neon
Unzip vectors
vuzp2_s16neon
Unzip vectors
vuzp2_s32neon
Unzip vectors
vuzp2_u8neon
Unzip vectors
vuzp2_u16neon
Unzip vectors
vuzp2_u32neon
Unzip vectors
vuzp2q_f32neon
Unzip vectors
vuzp2q_f64neon
Unzip vectors
vuzp2q_p8neon
Unzip vectors
vuzp2q_p16neon
Unzip vectors
vuzp2q_p64neon
Unzip vectors
vuzp2q_s8neon
Unzip vectors
vuzp2q_s16neon
Unzip vectors
vuzp2q_s32neon
Unzip vectors
vuzp2q_s64neon
Unzip vectors
vuzp2q_u8neon
Unzip vectors
vuzp2q_u16neon
Unzip vectors
vuzp2q_u32neon
Unzip vectors
vuzp2q_u64neon
Unzip vectors
vxarq_u64neon,sha3
Exclusive OR and rotate
vzip1_f32neon
Zip vectors
vzip1_p8neon
Zip vectors
vzip1_p16neon
Zip vectors
vzip1_s8neon
Zip vectors
vzip1_s16neon
Zip vectors
vzip1_s32neon
Zip vectors
vzip1_u8neon
Zip vectors
vzip1_u16neon
Zip vectors
vzip1_u32neon
Zip vectors
vzip1q_f32neon
Zip vectors
vzip1q_f64neon
Zip vectors
vzip1q_p8neon
Zip vectors
vzip1q_p16neon
Zip vectors
vzip1q_p64neon
Zip vectors
vzip1q_s8neon
Zip vectors
vzip1q_s16neon
Zip vectors
vzip1q_s32neon
Zip vectors
vzip1q_s64neon
Zip vectors
vzip1q_u8neon
Zip vectors
vzip1q_u16neon
Zip vectors
vzip1q_u32neon
Zip vectors
vzip1q_u64neon
Zip vectors
vzip2_f32neon
Zip vectors
vzip2_p8neon
Zip vectors
vzip2_p16neon
Zip vectors
vzip2_s8neon
Zip vectors
vzip2_s16neon
Zip vectors
vzip2_s32neon
Zip vectors
vzip2_u8neon
Zip vectors
vzip2_u16neon
Zip vectors
vzip2_u32neon
Zip vectors
vzip2q_f32neon
Zip vectors
vzip2q_f64neon
Zip vectors
vzip2q_p8neon
Zip vectors
vzip2q_p16neon
Zip vectors
vzip2q_p64neon
Zip vectors
vzip2q_s8neon
Zip vectors
vzip2q_s16neon
Zip vectors
vzip2q_s32neon
Zip vectors
vzip2q_s64neon
Zip vectors
vzip2q_u8neon
Zip vectors
vzip2q_u16neon
Zip vectors
vzip2q_u32neon
Zip vectors
vzip2q_u64neon
Zip vectors
__arm_mte_create_random_tagExperimentalmte
Return a pointer containing a randomly generated logical address tag.
__arm_mte_exclude_tagExperimentalmte
Add a logical tag to the set of excluded logical tags.
__arm_mte_get_tagExperimentalmte
Load an allocation tag from memory, returning a new pointer with the corresponding logical tag.
__arm_mte_increment_tagExperimentalmte
Return a pointer with the logical address tag offset by a value.
__arm_mte_ptrdiffExperimentalmte
Calculate the difference between the address parts of two pointers, ignoring the tags, and sign-extending the result.
__arm_mte_set_tagExperimentalmte
Store an allocation tag for the 16-byte granule of memory.
__crc32bExperimentalcrc and v8
CRC32 single round checksum for bytes (8 bits).
__crc32cbExperimentalcrc and v8
CRC32-C single round checksum for bytes (8 bits).
__crc32cdExperimentalcrc
CRC32 single round checksum for quad words (64 bits).
__crc32chExperimentalcrc and v8
CRC32-C single round checksum for half words (16 bits).
__crc32cwExperimentalcrc and v8
CRC32-C single round checksum for words (32 bits).
__crc32dExperimentalcrc
CRC32 single round checksum for quad words (64 bits).
__crc32hExperimentalcrc and v8
CRC32 single round checksum for half words (16 bits).
__crc32wExperimentalcrc and v8
CRC32 single round checksum for words (32 bits).
__dmbExperimental
Generates a DMB (data memory barrier) instruction or equivalent CP15 instruction.
__dsbExperimental
Generates a DSB (data synchronization barrier) instruction or equivalent CP15 instruction.
__isbExperimental
Generates an ISB (instruction synchronization barrier) instruction or equivalent CP15 instruction.
__nopExperimental
Generates an unspecified no-op instruction.
__sevExperimental
Generates a SEV (send a global event) hint instruction.
__sevlExperimental
Generates a send a local event hint instruction.
__tcancelExperimentaltme
Cancels the current transaction and discards all state modifications that were performed transactionally.
__tcommitExperimentaltme
Commits the current transaction. For a nested transaction, the only effect is that the transactional nesting depth is decreased. For an outer transaction, the state modifications performed transactionally are committed to the architectural state.
__tstartExperimentaltme
Starts a new transaction. When the transaction starts successfully the return value is 0. If the transaction fails, all state modifications are discarded and a cause of the failure is encoded in the return value.
__ttestExperimentaltme
Tests if executing inside a transaction. If no transaction is currently executing, the return value is 0. Otherwise, this intrinsic returns the depth of the transaction.
__wfeExperimental
Generates a WFE (wait for event) hint instruction, or nothing.
__wfiExperimental
Generates a WFI (wait for interrupt) hint instruction, or nothing.
__yieldExperimental
Generates a YIELD hint instruction.
_prefetchExperimental
Fetch the cache line that contains address p using the given RW and LOCALITY.
vaba_s8Experimentalneon and v7
vaba_s16Experimentalneon and v7
vaba_s32Experimentalneon and v7
vaba_u8Experimentalneon and v7
vaba_u16Experimentalneon and v7
vaba_u32Experimentalneon and v7
vabal_s8Experimentalneon and v7
Signed Absolute difference and Accumulate Long
vabal_s16Experimentalneon and v7
Signed Absolute difference and Accumulate Long
vabal_s32Experimentalneon and v7
Signed Absolute difference and Accumulate Long
vabal_u8Experimentalneon and v7
Unsigned Absolute difference and Accumulate Long
vabal_u16Experimentalneon and v7
Unsigned Absolute difference and Accumulate Long
vabal_u32Experimentalneon and v7
Unsigned Absolute difference and Accumulate Long
vabaq_s8Experimentalneon and v7
vabaq_s16Experimentalneon and v7
vabaq_s32Experimentalneon and v7
vabaq_u8Experimentalneon and v7
vabaq_u16Experimentalneon and v7
vabaq_u32Experimentalneon and v7
vabd_f32Experimentalneon and v7
Absolute difference between the arguments of Floating
vabd_s8Experimentalneon and v7
Absolute difference between the arguments
vabd_s16Experimentalneon and v7
Absolute difference between the arguments
vabd_s32Experimentalneon and v7
Absolute difference between the arguments
vabd_u8Experimentalneon and v7
Absolute difference between the arguments
vabd_u16Experimentalneon and v7
Absolute difference between the arguments
vabd_u32Experimentalneon and v7
Absolute difference between the arguments
vabdl_s8Experimentalneon and v7
Signed Absolute difference Long
vabdl_s16Experimentalneon and v7
Signed Absolute difference Long
vabdl_s32Experimentalneon and v7
Signed Absolute difference Long
vabdl_u8Experimentalneon and v7
Unsigned Absolute difference Long
vabdl_u16Experimentalneon and v7
Unsigned Absolute difference Long
vabdl_u32Experimentalneon and v7
Unsigned Absolute difference Long
vabdq_f32Experimentalneon and v7
Absolute difference between the arguments of Floating
vabdq_s8Experimentalneon and v7
Absolute difference between the arguments
vabdq_s16Experimentalneon and v7
Absolute difference between the arguments
vabdq_s32Experimentalneon and v7
Absolute difference between the arguments
vabdq_u8Experimentalneon and v7
Absolute difference between the arguments
vabdq_u16Experimentalneon and v7
Absolute difference between the arguments
vabdq_u32Experimentalneon and v7
Absolute difference between the arguments
vabs_f32Experimentalneon and v7
Floating-point absolute value
vabs_s8Experimentalneon and v7
Absolute value (wrapping).
vabs_s16Experimentalneon and v7
Absolute value (wrapping).
vabs_s32Experimentalneon and v7
Absolute value (wrapping).
vabsq_f32Experimentalneon and v7
Floating-point absolute value
vabsq_s8Experimentalneon and v7
Absolute value (wrapping).
vabsq_s16Experimentalneon and v7
Absolute value (wrapping).
vabsq_s32Experimentalneon and v7
Absolute value (wrapping).
vadd_f32Experimentalneon and v7
Vector add.
vadd_p8Experimentalneon and v7
Bitwise exclusive OR
vadd_p16Experimentalneon and v7
Bitwise exclusive OR
vadd_p64Experimentalneon and v7
Bitwise exclusive OR
vadd_s8Experimentalneon and v7
Vector add.
vadd_s16Experimentalneon and v7
Vector add.
vadd_s32Experimentalneon and v7
Vector add.
vadd_u8Experimentalneon and v7
Vector add.
vadd_u16Experimentalneon and v7
Vector add.
vadd_u32Experimentalneon and v7
Vector add.
vaddhn_high_s16Experimentalneon and v7
Add returning High Narrow (high half).
vaddhn_high_s32Experimentalneon and v7
Add returning High Narrow (high half).
vaddhn_high_s64Experimentalneon and v7
Add returning High Narrow (high half).
vaddhn_high_u16Experimentalneon and v7
Add returning High Narrow (high half).
vaddhn_high_u32Experimentalneon and v7
Add returning High Narrow (high half).
vaddhn_high_u64Experimentalneon and v7
Add returning High Narrow (high half).
vaddhn_s16Experimentalneon and v7
Add returning High Narrow.
vaddhn_s32Experimentalneon and v7
Add returning High Narrow.
vaddhn_s64Experimentalneon and v7
Add returning High Narrow.
vaddhn_u16Experimentalneon and v7
Add returning High Narrow.
vaddhn_u32Experimentalneon and v7
Add returning High Narrow.
vaddhn_u64Experimentalneon and v7
Add returning High Narrow.
vaddl_high_s8Experimentalneon and v7
Signed Add Long (vector, high half).
vaddl_high_s16Experimentalneon and v7
Signed Add Long (vector, high half).
vaddl_high_s32Experimentalneon and v7
Signed Add Long (vector, high half).
vaddl_high_u8Experimentalneon and v7
Unsigned Add Long (vector, high half).
vaddl_high_u16Experimentalneon and v7
Unsigned Add Long (vector, high half).
vaddl_high_u32Experimentalneon and v7
Unsigned Add Long (vector, high half).
vaddl_s8Experimentalneon and v7
Signed Add Long (vector).
vaddl_s16Experimentalneon and v7
Signed Add Long (vector).
vaddl_s32Experimentalneon and v7
Signed Add Long (vector).
vaddl_u8Experimentalneon and v7
Unsigned Add Long (vector).
vaddl_u16Experimentalneon and v7
Unsigned Add Long (vector).
vaddl_u32Experimentalneon and v7
Unsigned Add Long (vector).
vaddq_f32Experimentalneon and v7
Vector add.
vaddq_p8Experimentalneon and v7
Bitwise exclusive OR
vaddq_p16Experimentalneon and v7
Bitwise exclusive OR
vaddq_p64Experimentalneon and v7
Bitwise exclusive OR
vaddq_p128Experimentalneon and v7
Bitwise exclusive OR
vaddq_s8Experimentalneon and v7
Vector add.
vaddq_s16Experimentalneon and v7
Vector add.
vaddq_s32Experimentalneon and v7
Vector add.
vaddq_s64Experimentalneon and v7
Vector add.
vaddq_u8Experimentalneon and v7
Vector add.
vaddq_u16Experimentalneon and v7
Vector add.
vaddq_u32Experimentalneon and v7
Vector add.
vaddq_u64Experimentalneon and v7
Vector add.
vaddw_high_s8Experimentalneon and v7
Signed Add Wide (high half).
vaddw_high_s16Experimentalneon and v7
Signed Add Wide (high half).
vaddw_high_s32Experimentalneon and v7
Signed Add Wide (high half).
vaddw_high_u8Experimentalneon and v7
Unsigned Add Wide (high half).
vaddw_high_u16Experimentalneon and v7
Unsigned Add Wide (high half).
vaddw_high_u32Experimentalneon and v7
Unsigned Add Wide (high half).
vaddw_s8Experimentalneon and v7
Signed Add Wide.
vaddw_s16Experimentalneon and v7
Signed Add Wide.
vaddw_s32Experimentalneon and v7
Signed Add Wide.
vaddw_u8Experimentalneon and v7
Unsigned Add Wide.
vaddw_u16Experimentalneon and v7
Unsigned Add Wide.
vaddw_u32Experimentalneon and v7
Unsigned Add Wide.
vaesdq_u8Experimentalaes and v8
AES single round decryption.
vaeseq_u8Experimentalaes and v8
AES single round encryption.
vaesimcq_u8Experimentalaes and v8
AES inverse mix columns.
vaesmcq_u8Experimentalaes and v8
AES mix columns.
vand_s8Experimentalneon and v7
Vector bitwise and
vand_s16Experimentalneon and v7
Vector bitwise and
vand_s32Experimentalneon and v7
Vector bitwise and
vand_s64Experimentalneon and v7
Vector bitwise and
vand_u8Experimentalneon and v7
Vector bitwise and
vand_u16Experimentalneon and v7
Vector bitwise and
vand_u32Experimentalneon and v7
Vector bitwise and
vand_u64Experimentalneon and v7
Vector bitwise and
vandq_s8Experimentalneon and v7
Vector bitwise and
vandq_s16Experimentalneon and v7
Vector bitwise and
vandq_s32Experimentalneon and v7
Vector bitwise and
vandq_s64Experimentalneon and v7
Vector bitwise and
vandq_u8Experimentalneon and v7
Vector bitwise and
vandq_u16Experimentalneon and v7
Vector bitwise and
vandq_u32Experimentalneon and v7
Vector bitwise and
vandq_u64Experimentalneon and v7
Vector bitwise and
vbic_s8Experimentalneon and v7
Vector bitwise bit clear
vbic_s16Experimentalneon and v7
Vector bitwise bit clear
vbic_s32Experimentalneon and v7
Vector bitwise bit clear
vbic_s64Experimentalneon and v7
Vector bitwise bit clear
vbic_u8Experimentalneon and v7
Vector bitwise bit clear
vbic_u16Experimentalneon and v7
Vector bitwise bit clear
vbic_u32Experimentalneon and v7
Vector bitwise bit clear
vbic_u64Experimentalneon and v7
Vector bitwise bit clear
vbicq_s8Experimentalneon and v7
Vector bitwise bit clear
vbicq_s16Experimentalneon and v7
Vector bitwise bit clear
vbicq_s32Experimentalneon and v7
Vector bitwise bit clear
vbicq_s64Experimentalneon and v7
Vector bitwise bit clear
vbicq_u8Experimentalneon and v7
Vector bitwise bit clear
vbicq_u16Experimentalneon and v7
Vector bitwise bit clear
vbicq_u32Experimentalneon and v7
Vector bitwise bit clear
vbicq_u64Experimentalneon and v7
Vector bitwise bit clear
vbsl_f32Experimentalneon and v7
Bitwise Select.
vbsl_p8Experimentalneon and v7
Bitwise Select.
vbsl_p16Experimentalneon and v7
Bitwise Select.
vbsl_s8Experimentalneon and v7
Bitwise Select instructions. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register. Bitwise Select.
vbsl_s16Experimentalneon and v7
Bitwise Select.
vbsl_s32Experimentalneon and v7
Bitwise Select.
vbsl_s64Experimentalneon and v7
Bitwise Select.
vbsl_u8Experimentalneon and v7
Bitwise Select.
vbsl_u16Experimentalneon and v7
Bitwise Select.
vbsl_u32Experimentalneon and v7
Bitwise Select.
vbsl_u64Experimentalneon and v7
Bitwise Select.
vbslq_f32Experimentalneon and v7
Bitwise Select. (128-bit)
vbslq_p8Experimentalneon and v7
Bitwise Select. (128-bit)
vbslq_p16Experimentalneon and v7
Bitwise Select. (128-bit)
vbslq_s8Experimentalneon and v7
Bitwise Select. (128-bit)
vbslq_s16Experimentalneon and v7
Bitwise Select. (128-bit)
vbslq_s32Experimentalneon and v7
Bitwise Select. (128-bit)
vbslq_s64Experimentalneon and v7
Bitwise Select. (128-bit)
vbslq_u8Experimentalneon and v7
Bitwise Select. (128-bit)
vbslq_u16Experimentalneon and v7
Bitwise Select. (128-bit)
vbslq_u32Experimentalneon and v7
Bitwise Select. (128-bit)
vbslq_u64Experimentalneon and v7
Bitwise Select. (128-bit)
vcadd_rot90_f32Experimentalneon,fcma
Floating-point complex add
vcadd_rot270_f32Experimentalneon,fcma
Floating-point complex add
vcaddq_rot90_f32Experimentalneon,fcma
Floating-point complex add
vcaddq_rot90_f64Experimentalneon,fcma
Floating-point complex add
vcaddq_rot270_f32Experimentalneon,fcma
Floating-point complex add
vcaddq_rot270_f64Experimentalneon,fcma
Floating-point complex add
vcage_f32Experimentalneon and v7
Floating-point absolute compare greater than or equal
vcageq_f32Experimentalneon and v7
Floating-point absolute compare greater than or equal
vcagt_f32Experimentalneon and v7
Floating-point absolute compare greater than
vcagtq_f32Experimentalneon and v7
Floating-point absolute compare greater than
vcale_f32Experimentalneon and v7
Floating-point absolute compare less than or equal
vcaleq_f32Experimentalneon and v7
Floating-point absolute compare less than or equal
vcalt_f32Experimentalneon and v7
Floating-point absolute compare less than
vcaltq_f32Experimentalneon and v7
Floating-point absolute compare less than
vceq_f32Experimentalneon and v7
Floating-point compare equal
vceq_p8Experimentalneon and v7
Compare bitwise Equal (vector)
vceq_s8Experimentalneon and v7
Compare bitwise Equal (vector)
vceq_s16Experimentalneon and v7
Compare bitwise Equal (vector)
vceq_s32Experimentalneon and v7
Compare bitwise Equal (vector)
vceq_u8Experimentalneon and v7
Compare bitwise Equal (vector)
vceq_u16Experimentalneon and v7
Compare bitwise Equal (vector)
vceq_u32Experimentalneon and v7
Compare bitwise Equal (vector)
vceqq_f32Experimentalneon and v7
Floating-point compare equal
vceqq_p8Experimentalneon and v7
Compare bitwise Equal (vector)
vceqq_s8Experimentalneon and v7
Compare bitwise Equal (vector)
vceqq_s16Experimentalneon and v7
Compare bitwise Equal (vector)
vceqq_s32Experimentalneon and v7
Compare bitwise Equal (vector)
vceqq_u8Experimentalneon and v7
Compare bitwise Equal (vector)
vceqq_u16Experimentalneon and v7
Compare bitwise Equal (vector)
vceqq_u32Experimentalneon and v7
Compare bitwise Equal (vector)
vcge_f32Experimentalneon and v7
Floating-point compare greater than or equal
vcge_s8Experimentalneon and v7
Compare signed greater than or equal
vcge_s16Experimentalneon and v7
Compare signed greater than or equal
vcge_s32Experimentalneon and v7
Compare signed greater than or equal
vcge_u8Experimentalneon and v7
Compare unsigned greater than or equal
vcge_u16Experimentalneon and v7
Compare unsigned greater than or equal
vcge_u32Experimentalneon and v7
Compare unsigned greater than or equal
vcgeq_f32Experimentalneon and v7
Floating-point compare greater than or equal
vcgeq_s8Experimentalneon and v7
Compare signed greater than or equal
vcgeq_s16Experimentalneon and v7
Compare signed greater than or equal
vcgeq_s32Experimentalneon and v7
Compare signed greater than or equal
vcgeq_u8Experimentalneon and v7
Compare unsigned greater than or equal
vcgeq_u16Experimentalneon and v7
Compare unsigned greater than or equal
vcgeq_u32Experimentalneon and v7
Compare unsigned greater than or equal
vcgt_f32Experimentalneon and v7
Floating-point compare greater than
vcgt_s8Experimentalneon and v7
Compare signed greater than
vcgt_s16Experimentalneon and v7
Compare signed greater than
vcgt_s32Experimentalneon and v7
Compare signed greater than
vcgt_u8Experimentalneon and v7
Compare unsigned greater than
vcgt_u16Experimentalneon and v7
Compare unsigned greater than
vcgt_u32Experimentalneon and v7
Compare unsigned greater than
vcgtq_f32Experimentalneon and v7
Floating-point compare greater than
vcgtq_s8Experimentalneon and v7
Compare signed greater than
vcgtq_s16Experimentalneon and v7
Compare signed greater than
vcgtq_s32Experimentalneon and v7
Compare signed greater than
vcgtq_u8Experimentalneon and v7
Compare unsigned greater than
vcgtq_u16Experimentalneon and v7
Compare unsigned greater than
vcgtq_u32Experimentalneon and v7
Compare unsigned greater than
vcle_f32Experimentalneon and v7
Floating-point compare less than or equal
vcle_s8Experimentalneon and v7
Compare signed less than or equal
vcle_s16Experimentalneon and v7
Compare signed less than or equal
vcle_s32Experimentalneon and v7
Compare signed less than or equal
vcle_u8Experimentalneon and v7
Compare unsigned less than or equal
vcle_u16Experimentalneon and v7
Compare unsigned less than or equal
vcle_u32Experimentalneon and v7
Compare unsigned less than or equal
vcleq_f32Experimentalneon and v7
Floating-point compare less than or equal
vcleq_s8Experimentalneon and v7
Compare signed less than or equal
vcleq_s16Experimentalneon and v7
Compare signed less than or equal
vcleq_s32Experimentalneon and v7
Compare signed less than or equal
vcleq_u8Experimentalneon and v7
Compare unsigned less than or equal
vcleq_u16Experimentalneon and v7
Compare unsigned less than or equal
vcleq_u32Experimentalneon and v7
Compare unsigned less than or equal
vcls_s8Experimentalneon and v7
Count leading sign bits
vcls_s16Experimentalneon and v7
Count leading sign bits
vcls_s32Experimentalneon and v7
Count leading sign bits
vcls_u8Experimentalneon and v7
Count leading sign bits
vcls_u16Experimentalneon and v7
Count leading sign bits
vcls_u32Experimentalneon and v7
Count leading sign bits
vclsq_s8Experimentalneon and v7
Count leading sign bits
vclsq_s16Experimentalneon and v7
Count leading sign bits
vclsq_s32Experimentalneon and v7
Count leading sign bits
vclsq_u8Experimentalneon and v7
Count leading sign bits
vclsq_u16Experimentalneon and v7
Count leading sign bits
vclsq_u32Experimentalneon and v7
Count leading sign bits
vclt_f32Experimentalneon and v7
Floating-point compare less than
vclt_s8Experimentalneon and v7
Compare signed less than
vclt_s16Experimentalneon and v7
Compare signed less than
vclt_s32Experimentalneon and v7
Compare signed less than
vclt_u8Experimentalneon and v7
Compare unsigned less than
vclt_u16Experimentalneon and v7
Compare unsigned less than
vclt_u32Experimentalneon and v7
Compare unsigned less than
vcltq_f32Experimentalneon and v7
Floating-point compare less than
vcltq_s8Experimentalneon and v7
Compare signed less than
vcltq_s16Experimentalneon and v7
Compare signed less than
vcltq_s32Experimentalneon and v7
Compare signed less than
vcltq_u8Experimentalneon and v7
Compare unsigned less than
vcltq_u16Experimentalneon and v7
Compare unsigned less than
vcltq_u32Experimentalneon and v7
Compare unsigned less than
vclz_s8Experimentalneon and v7
Count leading zero bits
vclz_s16Experimentalneon and v7
Count leading zero bits
vclz_s32Experimentalneon and v7
Count leading zero bits
vclz_u8Experimentalneon and v7
Count leading zero bits
vclz_u16Experimentalneon and v7
Count leading zero bits
vclz_u32Experimentalneon and v7
Count leading zero bits
vclzq_s8Experimentalneon and v7
Count leading zero bits
vclzq_s16Experimentalneon and v7
Count leading zero bits
vclzq_s32Experimentalneon and v7
Count leading zero bits
vclzq_u8Experimentalneon and v7
Count leading zero bits
vclzq_u16Experimentalneon and v7
Count leading zero bits
vclzq_u32Experimentalneon and v7
Count leading zero bits
vcmla_f32Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmla_lane_f32Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmla_laneq_f32Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmla_rot90_f32Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmla_rot90_lane_f32Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmla_rot90_laneq_f32Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmla_rot180_f32Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmla_rot180_lane_f32Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmla_rot180_laneq_f32Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmla_rot270_f32Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmla_rot270_lane_f32Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmla_rot270_laneq_f32Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmlaq_f32Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmlaq_f64Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmlaq_lane_f32Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmlaq_laneq_f32Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmlaq_rot90_f32Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmlaq_rot90_f64Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmlaq_rot90_lane_f32Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmlaq_rot90_laneq_f32Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmlaq_rot180_f32Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmlaq_rot180_f64Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmlaq_rot180_lane_f32Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmlaq_rot180_laneq_f32Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmlaq_rot270_f32Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmlaq_rot270_f64Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmlaq_rot270_lane_f32Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmlaq_rot270_laneq_f32Experimentalneon,fcma
Floating-point complex multiply accumulate
vcnt_p8Experimentalneon and v7
Population count per byte.
vcnt_s8Experimentalneon and v7
Population count per byte.
vcnt_u8Experimentalneon and v7
Population count per byte.
vcntq_p8Experimentalneon and v7
Population count per byte.
vcntq_s8Experimentalneon and v7
Population count per byte.
vcntq_u8Experimentalneon and v7
Population count per byte.
vcombine_f32Experimentalneon and v7
Vector combine
vcombine_p8Experimentalneon and v7
Vector combine
vcombine_p16Experimentalneon and v7
Vector combine
vcombine_p64Experimentalneon and v7
Vector combine
vcombine_s8Experimentalneon and v7
Vector combine
vcombine_s16Experimentalneon and v7
Vector combine
vcombine_s32Experimentalneon and v7
Vector combine
vcombine_s64Experimentalneon and v7
Vector combine
vcombine_u8Experimentalneon and v7
Vector combine
vcombine_u16Experimentalneon and v7
Vector combine
vcombine_u32Experimentalneon and v7
Vector combine
vcombine_u64Experimentalneon and v7
Vector combine
vcreate_f32Experimentalneon and v7
Insert vector element from another vector element
vcreate_p8Experimentalneon and v7
Insert vector element from another vector element
vcreate_p16Experimentalneon and v7
Insert vector element from another vector element
vcreate_p64Experimentalneon,aes and v8
Insert vector element from another vector element
vcreate_s8Experimentalneon and v7
Insert vector element from another vector element
vcreate_s16Experimentalneon and v7
Insert vector element from another vector element
vcreate_s32Experimentalneon and v7
Insert vector element from another vector element
vcreate_s64Experimentalneon and v7
Insert vector element from another vector element
vcreate_u8Experimentalneon and v7
Insert vector element from another vector element
vcreate_u16Experimentalneon and v7
Insert vector element from another vector element
vcreate_u32Experimentalneon and v7
Insert vector element from another vector element
vcreate_u64Experimentalneon and v7
Insert vector element from another vector element
vcvt_f32_s32Experimentalneon and v7
Fixed-point convert to floating-point
vcvt_f32_u32Experimentalneon and v7
Fixed-point convert to floating-point
vcvt_n_f32_s32Experimentalneon,v7
Fixed-point convert to floating-point
vcvt_n_f32_u32Experimentalneon,v7
Fixed-point convert to floating-point
vcvt_n_s32_f32Experimentalneon,v7
Floating-point convert to fixed-point, rounding toward zero
vcvt_n_u32_f32Experimentalneon,v7
Floating-point convert to fixed-point, rounding toward zero
vcvt_s32_f32Experimentalneon and v7
Floating-point convert to signed fixed-point, rounding toward zero
vcvt_u32_f32Experimentalneon and v7
Floating-point convert to unsigned fixed-point, rounding toward zero
vcvtq_f32_s32Experimentalneon and v7
Fixed-point convert to floating-point
vcvtq_f32_u32Experimentalneon and v7
Fixed-point convert to floating-point
vcvtq_n_f32_s32Experimentalneon,v7
Fixed-point convert to floating-point
vcvtq_n_f32_u32Experimentalneon,v7
Fixed-point convert to floating-point
vcvtq_n_s32_f32Experimentalneon,v7
Floating-point convert to fixed-point, rounding toward zero
vcvtq_n_u32_f32Experimentalneon,v7
Floating-point convert to fixed-point, rounding toward zero
vcvtq_s32_f32Experimentalneon and v7
Floating-point convert to signed fixed-point, rounding toward zero
vcvtq_u32_f32Experimentalneon and v7
Floating-point convert to unsigned fixed-point, rounding toward zero
vdot_lane_s32Experimentalneon,dotprod and v8
Dot product arithmetic (indexed)
vdot_lane_u32Experimentalneon,dotprod and v8
Dot product arithmetic (indexed)
vdot_laneq_s32Experimentalneon,dotprod
Dot product arithmetic (indexed)
vdot_laneq_u32Experimentalneon,dotprod
Dot product arithmetic (indexed)
vdot_s32Experimentalneon,dotprod and v8
Dot product arithmetic (vector)
vdot_u32Experimentalneon,dotprod and v8
Dot product arithmetic (vector)
vdotq_lane_s32Experimentalneon,dotprod and v8
Dot product arithmetic (indexed)
vdotq_lane_u32Experimentalneon,dotprod and v8
Dot product arithmetic (indexed)
vdotq_laneq_s32Experimentalneon,dotprod
Dot product arithmetic (indexed)
vdotq_laneq_u32Experimentalneon,dotprod
Dot product arithmetic (indexed)
vdotq_s32Experimentalneon,dotprod and v8
Dot product arithmetic (vector)
vdotq_u32Experimentalneon,dotprod and v8
Dot product arithmetic (vector)
vdup_lane_f32Experimentalneon and v7
Set all vector lanes to the same value
vdup_lane_p8Experimentalneon and v7
Set all vector lanes to the same value
vdup_lane_p16Experimentalneon and v7
Set all vector lanes to the same value
vdup_lane_s8Experimentalneon and v7
Set all vector lanes to the same value
vdup_lane_s16Experimentalneon and v7
Set all vector lanes to the same value
vdup_lane_s32Experimentalneon and v7
Set all vector lanes to the same value
vdup_lane_s64Experimentalneon and v7
Set all vector lanes to the same value
vdup_lane_u8Experimentalneon and v7
Set all vector lanes to the same value
vdup_lane_u16Experimentalneon and v7
Set all vector lanes to the same value
vdup_lane_u32Experimentalneon and v7
Set all vector lanes to the same value
vdup_lane_u64Experimentalneon and v7
Set all vector lanes to the same value
vdup_laneq_f32Experimentalneon and v7
Set all vector lanes to the same value
vdup_laneq_p8Experimentalneon and v7
Set all vector lanes to the same value
vdup_laneq_p16Experimentalneon and v7
Set all vector lanes to the same value
vdup_laneq_s8Experimentalneon and v7
Set all vector lanes to the same value
vdup_laneq_s16Experimentalneon and v7
Set all vector lanes to the same value
vdup_laneq_s32Experimentalneon and v7
Set all vector lanes to the same value
vdup_laneq_s64Experimentalneon and v7
Set all vector lanes to the same value
vdup_laneq_u8Experimentalneon and v7
Set all vector lanes to the same value
vdup_laneq_u16Experimentalneon and v7
Set all vector lanes to the same value
vdup_laneq_u32Experimentalneon and v7
Set all vector lanes to the same value
vdup_laneq_u64Experimentalneon and v7
Set all vector lanes to the same value
vdup_n_f32Experimentalneon and v7
Duplicate vector element to vector or scalar
vdup_n_p8Experimentalneon and v7
Duplicate vector element to vector or scalar
vdup_n_p16Experimentalneon and v7
Duplicate vector element to vector or scalar
vdup_n_s8Experimentalneon and v7
Duplicate vector element to vector or scalar
vdup_n_s16Experimentalneon and v7
Duplicate vector element to vector or scalar
vdup_n_s32Experimentalneon and v7
Duplicate vector element to vector or scalar
vdup_n_s64Experimentalneon and v7
Duplicate vector element to vector or scalar
vdup_n_u8Experimentalneon and v7
Duplicate vector element to vector or scalar
vdup_n_u16Experimentalneon and v7
Duplicate vector element to vector or scalar
vdup_n_u32Experimentalneon and v7
Duplicate vector element to vector or scalar
vdup_n_u64Experimentalneon and v7
Duplicate vector element to vector or scalar
vdupq_lane_f32Experimentalneon and v7
Set all vector lanes to the same value
vdupq_lane_p8Experimentalneon and v7
Set all vector lanes to the same value
vdupq_lane_p16Experimentalneon and v7
Set all vector lanes to the same value
vdupq_lane_s8Experimentalneon and v7
Set all vector lanes to the same value
vdupq_lane_s16Experimentalneon and v7
Set all vector lanes to the same value
vdupq_lane_s32Experimentalneon and v7
Set all vector lanes to the same value
vdupq_lane_s64Experimentalneon and v7
Set all vector lanes to the same value
vdupq_lane_u8Experimentalneon and v7
Set all vector lanes to the same value
vdupq_lane_u16Experimentalneon and v7
Set all vector lanes to the same value
vdupq_lane_u32Experimentalneon and v7
Set all vector lanes to the same value
vdupq_lane_u64Experimentalneon and v7
Set all vector lanes to the same value
vdupq_laneq_f32Experimentalneon and v7
Set all vector lanes to the same value
vdupq_laneq_p8Experimentalneon and v7
Set all vector lanes to the same value
vdupq_laneq_p16Experimentalneon and v7
Set all vector lanes to the same value
vdupq_laneq_s8Experimentalneon and v7
Set all vector lanes to the same value
vdupq_laneq_s16Experimentalneon and v7
Set all vector lanes to the same value
vdupq_laneq_s32Experimentalneon and v7
Set all vector lanes to the same value
vdupq_laneq_s64Experimentalneon and v7
Set all vector lanes to the same value
vdupq_laneq_u8Experimentalneon and v7
Set all vector lanes to the same value
vdupq_laneq_u16Experimentalneon and v7
Set all vector lanes to the same value
vdupq_laneq_u32Experimentalneon and v7
Set all vector lanes to the same value
vdupq_laneq_u64Experimentalneon and v7
Set all vector lanes to the same value
vdupq_n_f32Experimentalneon and v7
Duplicate vector element to vector or scalar
vdupq_n_p8Experimentalneon and v7
Duplicate vector element to vector or scalar
vdupq_n_p16Experimentalneon and v7
Duplicate vector element to vector or scalar
vdupq_n_s8Experimentalneon and v7
Duplicate vector element to vector or scalar
vdupq_n_s16Experimentalneon and v7
Duplicate vector element to vector or scalar
vdupq_n_s32Experimentalneon and v7
Duplicate vector element to vector or scalar
vdupq_n_s64Experimentalneon and v7
Duplicate vector element to vector or scalar
vdupq_n_u8Experimentalneon and v7
Duplicate vector element to vector or scalar
vdupq_n_u16Experimentalneon and v7
Duplicate vector element to vector or scalar
vdupq_n_u32Experimentalneon and v7
Duplicate vector element to vector or scalar
vdupq_n_u64Experimentalneon and v7
Duplicate vector element to vector or scalar
veor_s8Experimentalneon and v7
Vector bitwise exclusive or (vector)
veor_s16Experimentalneon and v7
Vector bitwise exclusive or (vector)
veor_s32Experimentalneon and v7
Vector bitwise exclusive or (vector)
veor_s64Experimentalneon and v7
Vector bitwise exclusive or (vector)
veor_u8Experimentalneon and v7
Vector bitwise exclusive or (vector)
veor_u16Experimentalneon and v7
Vector bitwise exclusive or (vector)
veor_u32Experimentalneon and v7
Vector bitwise exclusive or (vector)
veor_u64Experimentalneon and v7
Vector bitwise exclusive or (vector)
veorq_s8Experimentalneon and v7
Vector bitwise exclusive or (vector)
veorq_s16Experimentalneon and v7
Vector bitwise exclusive or (vector)
veorq_s32Experimentalneon and v7
Vector bitwise exclusive or (vector)
veorq_s64Experimentalneon and v7
Vector bitwise exclusive or (vector)
veorq_u8Experimentalneon and v7
Vector bitwise exclusive or (vector)
veorq_u16Experimentalneon and v7
Vector bitwise exclusive or (vector)
veorq_u32Experimentalneon and v7
Vector bitwise exclusive or (vector)
veorq_u64Experimentalneon and v7
Vector bitwise exclusive or (vector)
vext_f32Experimentalneon and v7
Extract vector from pair of vectors
vext_p8Experimentalneon and v7
Extract vector from pair of vectors
vext_p16Experimentalneon and v7
Extract vector from pair of vectors
vext_s8Experimentalneon and v7
Extract vector from pair of vectors
vext_s16Experimentalneon and v7
Extract vector from pair of vectors
vext_s32Experimentalneon and v7
Extract vector from pair of vectors
vext_s64Experimentalneon and v7
Extract vector from pair of vectors
vext_u8Experimentalneon and v7
Extract vector from pair of vectors
vext_u16Experimentalneon and v7
Extract vector from pair of vectors
vext_u32Experimentalneon and v7
Extract vector from pair of vectors
vext_u64Experimentalneon and v7
Extract vector from pair of vectors
vextq_f32Experimentalneon and v7
Extract vector from pair of vectors
vextq_p8Experimentalneon and v7
Extract vector from pair of vectors
vextq_p16Experimentalneon and v7
Extract vector from pair of vectors
vextq_s8Experimentalneon and v7
Extract vector from pair of vectors
vextq_s16Experimentalneon and v7
Extract vector from pair of vectors
vextq_s32Experimentalneon and v7
Extract vector from pair of vectors
vextq_s64Experimentalneon and v7
Extract vector from pair of vectors
vextq_u8Experimentalneon and v7
Extract vector from pair of vectors
vextq_u16Experimentalneon and v7
Extract vector from pair of vectors
vextq_u32Experimentalneon and v7
Extract vector from pair of vectors
vextq_u64Experimentalneon and v7
Extract vector from pair of vectors
vfma_f32Experimentalneon and vfp4
Floating-point fused Multiply-Add to accumulator(vector)
vfma_n_f32Experimentalneon and vfp4
Floating-point fused Multiply-Add to accumulator(vector)
vfmaq_f32Experimentalneon and vfp4
Floating-point fused Multiply-Add to accumulator(vector)
vfmaq_n_f32Experimentalneon and vfp4
Floating-point fused Multiply-Add to accumulator(vector)
vfms_f32Experimentalneon and vfp4
Floating-point fused multiply-subtract from accumulator
vfms_n_f32Experimentalneon and vfp4
Floating-point fused Multiply-subtract to accumulator(vector)
vfmsq_f32Experimentalneon and vfp4
Floating-point fused multiply-subtract from accumulator
vfmsq_n_f32Experimentalneon and vfp4
Floating-point fused Multiply-subtract to accumulator(vector)
vget_high_f32Experimentalneon and v7
Duplicate vector element to vector or scalar
vget_high_p8Experimentalneon and v7
Duplicate vector element to vector or scalar
vget_high_p16Experimentalneon and v7
Duplicate vector element to vector or scalar
vget_high_s8Experimentalneon and v7
Duplicate vector element to vector or scalar
vget_high_s16Experimentalneon and v7
Duplicate vector element to vector or scalar
vget_high_s32Experimentalneon and v7
Duplicate vector element to vector or scalar
vget_high_s64Experimentalneon and v7
Duplicate vector element to vector or scalar
vget_high_u8Experimentalneon and v7
Duplicate vector element to vector or scalar
vget_high_u16Experimentalneon and v7
Duplicate vector element to vector or scalar
vget_high_u32Experimentalneon and v7
Duplicate vector element to vector or scalar
vget_high_u64Experimentalneon and v7
Duplicate vector element to vector or scalar
vget_lane_f32Experimentalneon and v7
Duplicate vector element to vector or scalar
vget_lane_p8Experimentalneon and v7
Move vector element to general-purpose register
vget_lane_p16Experimentalneon and v7
Move vector element to general-purpose register
vget_lane_p64Experimentalneon and v7
Move vector element to general-purpose register
vget_lane_s8Experimentalneon and v7
Move vector element to general-purpose register
vget_lane_s16Experimentalneon and v7
Move vector element to general-purpose register
vget_lane_s32Experimentalneon and v7
Move vector element to general-purpose register
vget_lane_s64Experimentalneon and v7
Move vector element to general-purpose register
vget_lane_u8Experimentalneon and v7
Move vector element to general-purpose register
vget_lane_u16Experimentalneon and v7
Move vector element to general-purpose register
vget_lane_u32Experimentalneon and v7
Move vector element to general-purpose register
vget_lane_u64Experimentalneon and v7
Move vector element to general-purpose register
vget_low_f32Experimentalneon and v7
Duplicate vector element to vector or scalar
vget_low_p8Experimentalneon and v7
Duplicate vector element to vector or scalar
vget_low_p16Experimentalneon and v7
Duplicate vector element to vector or scalar
vget_low_s8Experimentalneon and v7
Duplicate vector element to vector or scalar
vget_low_s16Experimentalneon and v7
Duplicate vector element to vector or scalar
vget_low_s32Experimentalneon and v7
Duplicate vector element to vector or scalar
vget_low_s64Experimentalneon and v7
Duplicate vector element to vector or scalar
vget_low_u8Experimentalneon and v7
Duplicate vector element to vector or scalar
vget_low_u16Experimentalneon and v7
Duplicate vector element to vector or scalar
vget_low_u32Experimentalneon and v7
Duplicate vector element to vector or scalar
vget_low_u64Experimentalneon and v7
Duplicate vector element to vector or scalar
vgetq_lane_f32Experimentalneon and v7
Duplicate vector element to vector or scalar
vgetq_lane_p8Experimentalneon and v7
Move vector element to general-purpose register
vgetq_lane_p16Experimentalneon and v7
Move vector element to general-purpose register
vgetq_lane_p64Experimentalneon and v7
Move vector element to general-purpose register
vgetq_lane_s8Experimentalneon and v7
Move vector element to general-purpose register
vgetq_lane_s16Experimentalneon and v7
Move vector element to general-purpose register
vgetq_lane_s32Experimentalneon and v7
Move vector element to general-purpose register
vgetq_lane_s64Experimentalneon and v7
Move vector element to general-purpose register
vgetq_lane_u8Experimentalneon and v7
Move vector element to general-purpose register
vgetq_lane_u16Experimentalneon and v7
Move vector element to general-purpose register
vgetq_lane_u32Experimentalneon and v7
Move vector element to general-purpose register
vgetq_lane_u64Experimentalneon and v7
Move vector element to general-purpose register
vhadd_s8Experimentalneon and v7
Halving add
vhadd_s16Experimentalneon and v7
Halving add
vhadd_s32Experimentalneon and v7
Halving add
vhadd_u8Experimentalneon and v7
Halving add
vhadd_u16Experimentalneon and v7
Halving add
vhadd_u32Experimentalneon and v7
Halving add
vhaddq_s8Experimentalneon and v7
Halving add
vhaddq_s16Experimentalneon and v7
Halving add
vhaddq_s32Experimentalneon and v7
Halving add
vhaddq_u8Experimentalneon and v7
Halving add
vhaddq_u16Experimentalneon and v7
Halving add
vhaddq_u32Experimentalneon and v7
Halving add
vhsub_s8Experimentalneon and v7
Signed halving subtract
vhsub_s16Experimentalneon and v7
Signed halving subtract
vhsub_s32Experimentalneon and v7
Signed halving subtract
vhsub_u8Experimentalneon and v7
Signed halving subtract
vhsub_u16Experimentalneon and v7
Signed halving subtract
vhsub_u32Experimentalneon and v7
Signed halving subtract
vhsubq_s8Experimentalneon and v7
Signed halving subtract
vhsubq_s16Experimentalneon and v7
Signed halving subtract
vhsubq_s32Experimentalneon and v7
Signed halving subtract
vhsubq_u8Experimentalneon and v7
Signed halving subtract
vhsubq_u16Experimentalneon and v7
Signed halving subtract
vhsubq_u32Experimentalneon and v7
Signed halving subtract
vld1_dup_f32Experimentalneon and v7
Load one single-element structure and Replicate to all lanes (of one register).
vld1_dup_p8Experimentalneon and v7
Load one single-element structure and Replicate to all lanes (of one register).
vld1_dup_p16Experimentalneon and v7
Load one single-element structure and Replicate to all lanes (of one register).
vld1_dup_p64Experimentalneon,aes and v7
Load one single-element structure and Replicate to all lanes (of one register).
vld1_dup_s8Experimentalneon and v7
Load one single-element structure and Replicate to all lanes (of one register).
vld1_dup_s16Experimentalneon and v7
Load one single-element structure and Replicate to all lanes (of one register).
vld1_dup_s32Experimentalneon and v7
Load one single-element structure and Replicate to all lanes (of one register).
vld1_dup_s64Experimentalneon and v7
Load one single-element structure and Replicate to all lanes (of one register).
vld1_dup_u8Experimentalneon and v7
Load one single-element structure and Replicate to all lanes (of one register).
vld1_dup_u16Experimentalneon and v7
Load one single-element structure and Replicate to all lanes (of one register).
vld1_dup_u32Experimentalneon and v7
Load one single-element structure and Replicate to all lanes (of one register).
vld1_dup_u64Experimentalneon and v7
Load one single-element structure and Replicate to all lanes (of one register).
vld1_f32_x2Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1_f32_x3Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1_f32_x4Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1_lane_f32Experimentalneon and v7
Load one single-element structure to one lane of one register.
vld1_lane_p8Experimentalneon and v7
Load one single-element structure to one lane of one register.
vld1_lane_p16Experimentalneon and v7
Load one single-element structure to one lane of one register.
vld1_lane_p64Experimentalneon,aes and v7
Load one single-element structure to one lane of one register.
vld1_lane_s8Experimentalneon and v7
Load one single-element structure to one lane of one register.
vld1_lane_s16Experimentalneon and v7
Load one single-element structure to one lane of one register.
vld1_lane_s32Experimentalneon and v7
Load one single-element structure to one lane of one register.
vld1_lane_s64Experimentalneon and v7
Load one single-element structure to one lane of one register.
vld1_lane_u8Experimentalneon and v7
Load one single-element structure to one lane of one register.
vld1_lane_u16Experimentalneon and v7
Load one single-element structure to one lane of one register.
vld1_lane_u32Experimentalneon and v7
Load one single-element structure to one lane of one register.
vld1_lane_u64Experimentalneon and v7
Load one single-element structure to one lane of one register.
vld1_p8_x2Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1_p8_x3Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1_p8_x4Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1_p16_x2Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1_p16_x3Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1_p16_x4Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1_p64_x2Experimentalneon,aes and v8
Load multiple single-element structures to one, two, three, or four registers
vld1_p64_x3Experimentalneon,aes and v8
Load multiple single-element structures to one, two, three, or four registers
vld1_p64_x4Experimentalneon,aes and v8
Load multiple single-element structures to one, two, three, or four registers
vld1_s8_x2Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1_s8_x3Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1_s8_x4Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1_s16_x2Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1_s16_x3Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1_s16_x4Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1_s32_x2Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1_s32_x3Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1_s32_x4Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1_s64_x2Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1_s64_x3Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1_s64_x4Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1_u8_x2Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1_u8_x3Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1_u8_x4Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1_u16_x2Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1_u16_x3Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1_u16_x4Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1_u32_x2Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1_u32_x3Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1_u32_x4Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1_u64_x2Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1_u64_x3Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1_u64_x4Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1q_dup_f32Experimentalneon and v7
Load one single-element structure and Replicate to all lanes (of one register).
vld1q_dup_p8Experimentalneon and v7
Load one single-element structure and Replicate to all lanes (of one register).
vld1q_dup_p16Experimentalneon and v7
Load one single-element structure and Replicate to all lanes (of one register).
vld1q_dup_p64Experimentalneon,aes and v7
Load one single-element structure and Replicate to all lanes (of one register).
vld1q_dup_s8Experimentalneon and v7
Load one single-element structure and Replicate to all lanes (of one register).
vld1q_dup_s16Experimentalneon and v7
Load one single-element structure and Replicate to all lanes (of one register).
vld1q_dup_s32Experimentalneon and v7
Load one single-element structure and Replicate to all lanes (of one register).
vld1q_dup_s64Experimentalneon and v7
Load one single-element structure and Replicate to all lanes (of one register).
vld1q_dup_u8Experimentalneon and v7
Load one single-element structure and Replicate to all lanes (of one register).
vld1q_dup_u16Experimentalneon and v7
Load one single-element structure and Replicate to all lanes (of one register).
vld1q_dup_u32Experimentalneon and v7
Load one single-element structure and Replicate to all lanes (of one register).
vld1q_dup_u64Experimentalneon and v7
Load one single-element structure and Replicate to all lanes (of one register).
vld1q_f32_x2Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1q_f32_x3Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1q_f32_x4Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1q_lane_f32Experimentalneon and v7
Load one single-element structure to one lane of one register.
vld1q_lane_p8Experimentalneon and v7
Load one single-element structure to one lane of one register.
vld1q_lane_p16Experimentalneon and v7
Load one single-element structure to one lane of one register.
vld1q_lane_p64Experimentalneon,aes and v7
Load one single-element structure to one lane of one register.
vld1q_lane_s8Experimentalneon and v7
Load one single-element structure to one lane of one register.
vld1q_lane_s16Experimentalneon and v7
Load one single-element structure to one lane of one register.
vld1q_lane_s32Experimentalneon and v7
Load one single-element structure to one lane of one register.
vld1q_lane_s64Experimentalneon and v7
Load one single-element structure to one lane of one register.
vld1q_lane_u8Experimentalneon and v7
Load one single-element structure to one lane of one register.
vld1q_lane_u16Experimentalneon and v7
Load one single-element structure to one lane of one register.
vld1q_lane_u32Experimentalneon and v7
Load one single-element structure to one lane of one register.
vld1q_lane_u64Experimentalneon and v7
Load one single-element structure to one lane of one register.
vld1q_p8_x2Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1q_p8_x3Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1q_p8_x4Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1q_p16_x2Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1q_p16_x3Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1q_p16_x4Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1q_p64_x2Experimentalneon,aes and v8
Load multiple single-element structures to one, two, three, or four registers
vld1q_p64_x3Experimentalneon,aes and v8
Load multiple single-element structures to one, two, three, or four registers
vld1q_p64_x4Experimentalneon,aes and v8
Load multiple single-element structures to one, two, three, or four registers
vld1q_s8_x2Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1q_s8_x3Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1q_s8_x4Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1q_s16_x2Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1q_s16_x3Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1q_s16_x4Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1q_s32_x2Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1q_s32_x3Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1q_s32_x4Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1q_s64_x2Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1q_s64_x3Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1q_s64_x4Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1q_u8_x2Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1q_u8_x3Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1q_u8_x4Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1q_u16_x2Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1q_u16_x3Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1q_u16_x4Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1q_u32_x2Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1q_u32_x3Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1q_u32_x4Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1q_u64_x2Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1q_u64_x3Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld1q_u64_x4Experimentalneon and v7
Load multiple single-element structures to one, two, three, or four registers
vld2_dup_f32Experimentalneon,v7
Load single 2-element structure and replicate to all lanes of two registers
vld2_dup_p8Experimentalneon and v7
Load single 2-element structure and replicate to all lanes of two registers
vld2_dup_p16Experimentalneon and v7
Load single 2-element structure and replicate to all lanes of two registers
vld2_dup_p64Experimentalneon,aes and v8
Load single 2-element structure and replicate to all lanes of two registers
vld2_dup_s8Experimentalneon,v7
Load single 2-element structure and replicate to all lanes of two registers
vld2_dup_s16Experimentalneon,v7
Load single 2-element structure and replicate to all lanes of two registers
vld2_dup_s32Experimentalneon,v7
Load single 2-element structure and replicate to all lanes of two registers
vld2_dup_s64Experimentalneon,v7
Load single 2-element structure and replicate to all lanes of two registers
vld2_dup_u8Experimentalneon and v7
Load single 2-element structure and replicate to all lanes of two registers
vld2_dup_u16Experimentalneon and v7
Load single 2-element structure and replicate to all lanes of two registers
vld2_dup_u32Experimentalneon and v7
Load single 2-element structure and replicate to all lanes of two registers
vld2_dup_u64Experimentalneon and v7
Load single 2-element structure and replicate to all lanes of two registers
vld2_f32Experimentalneon,v7
Load multiple 2-element structures to two registers
vld2_lane_f32Experimentalneon,v7
Load multiple 2-element structures to two registers
vld2_lane_p8Experimentalneon and v7
Load multiple 2-element structures to two registers
vld2_lane_p16Experimentalneon and v7
Load multiple 2-element structures to two registers
vld2_lane_s8Experimentalneon,v7
Load multiple 2-element structures to two registers
vld2_lane_s16Experimentalneon,v7
Load multiple 2-element structures to two registers
vld2_lane_s32Experimentalneon,v7
Load multiple 2-element structures to two registers
vld2_lane_u8Experimentalneon and v7
Load multiple 2-element structures to two registers
vld2_lane_u16Experimentalneon and v7
Load multiple 2-element structures to two registers
vld2_lane_u32Experimentalneon and v7
Load multiple 2-element structures to two registers
vld2_p8Experimentalneon and v7
Load multiple 2-element structures to two registers
vld2_p16Experimentalneon and v7
Load multiple 2-element structures to two registers
vld2_p64Experimentalneon,aes and v8
Load multiple 2-element structures to two registers
vld2_s8Experimentalneon,v7
Load multiple 2-element structures to two registers
vld2_s16Experimentalneon,v7
Load multiple 2-element structures to two registers
vld2_s32Experimentalneon,v7
Load multiple 2-element structures to two registers
vld2_s64Experimentalneon,v7
Load multiple 2-element structures to two registers
vld2_u8Experimentalneon and v7
Load multiple 2-element structures to two registers
vld2_u16Experimentalneon and v7
Load multiple 2-element structures to two registers
vld2_u32Experimentalneon and v7
Load multiple 2-element structures to two registers
vld2_u64Experimentalneon and v7
Load multiple 2-element structures to two registers
vld2q_dup_f32Experimentalneon,v7
Load single 2-element structure and replicate to all lanes of two registers
vld2q_dup_p8Experimentalneon and v7
Load single 2-element structure and replicate to all lanes of two registers
vld2q_dup_p16Experimentalneon and v7
Load single 2-element structure and replicate to all lanes of two registers
vld2q_dup_s8Experimentalneon,v7
Load single 2-element structure and replicate to all lanes of two registers
vld2q_dup_s16Experimentalneon,v7
Load single 2-element structure and replicate to all lanes of two registers
vld2q_dup_s32Experimentalneon,v7
Load single 2-element structure and replicate to all lanes of two registers
vld2q_dup_u8Experimentalneon and v7
Load single 2-element structure and replicate to all lanes of two registers
vld2q_dup_u16Experimentalneon and v7
Load single 2-element structure and replicate to all lanes of two registers
vld2q_dup_u32Experimentalneon and v7
Load single 2-element structure and replicate to all lanes of two registers
vld2q_f32Experimentalneon,v7
Load multiple 2-element structures to two registers
vld2q_lane_f32Experimentalneon,v7
Load multiple 2-element structures to two registers
vld2q_lane_p16Experimentalneon and v7
Load multiple 2-element structures to two registers
vld2q_lane_s16Experimentalneon,v7
Load multiple 2-element structures to two registers
vld2q_lane_s32Experimentalneon,v7
Load multiple 2-element structures to two registers
vld2q_lane_u16Experimentalneon and v7
Load multiple 2-element structures to two registers
vld2q_lane_u32Experimentalneon and v7
Load multiple 2-element structures to two registers
vld2q_p8Experimentalneon and v7
Load multiple 2-element structures to two registers
vld2q_p16Experimentalneon and v7
Load multiple 2-element structures to two registers
vld2q_s8Experimentalneon,v7
Load multiple 2-element structures to two registers
vld2q_s16Experimentalneon,v7
Load multiple 2-element structures to two registers
vld2q_s32Experimentalneon,v7
Load multiple 2-element structures to two registers
vld2q_u8Experimentalneon and v7
Load multiple 2-element structures to two registers
vld2q_u16Experimentalneon and v7
Load multiple 2-element structures to two registers
vld2q_u32Experimentalneon and v7
Load multiple 2-element structures to two registers
vld3_dup_f32Experimentalneon,v7
Load single 3-element structure and replicate to all lanes of three registers
vld3_dup_p8Experimentalneon and v7
Load single 3-element structure and replicate to all lanes of three registers
vld3_dup_p16Experimentalneon and v7
Load single 3-element structure and replicate to all lanes of three registers
vld3_dup_p64Experimentalneon,aes and v8
Load single 3-element structure and replicate to all lanes of three registers
vld3_dup_s8Experimentalneon,v7
Load single 3-element structure and replicate to all lanes of three registers
vld3_dup_s16Experimentalneon,v7
Load single 3-element structure and replicate to all lanes of three registers
vld3_dup_s32Experimentalneon,v7
Load single 3-element structure and replicate to all lanes of three registers
vld3_dup_s64Experimentalneon,v7
Load single 3-element structure and replicate to all lanes of three registers
vld3_dup_u8Experimentalneon and v7
Load single 3-element structure and replicate to all lanes of three registers
vld3_dup_u16Experimentalneon and v7
Load single 3-element structure and replicate to all lanes of three registers
vld3_dup_u32Experimentalneon and v7
Load single 3-element structure and replicate to all lanes of three registers
vld3_dup_u64Experimentalneon and v7
Load single 3-element structure and replicate to all lanes of three registers
vld3_f32Experimentalneon,v7
Load multiple 3-element structures to three registers
vld3_lane_f32Experimentalneon,v7
Load multiple 3-element structures to three registers
vld3_lane_p8Experimentalneon and v7
Load multiple 3-element structures to three registers
vld3_lane_p16Experimentalneon and v7
Load multiple 3-element structures to three registers
vld3_lane_s8Experimentalneon,v7
Load multiple 3-element structures to two registers
vld3_lane_s16Experimentalneon,v7
Load multiple 3-element structures to two registers
vld3_lane_s32Experimentalneon,v7
Load multiple 3-element structures to two registers
vld3_lane_u8Experimentalneon and v7
Load multiple 3-element structures to three registers
vld3_lane_u16Experimentalneon and v7
Load multiple 3-element structures to three registers
vld3_lane_u32Experimentalneon and v7
Load multiple 3-element structures to three registers
vld3_p8Experimentalneon and v7
Load multiple 3-element structures to three registers
vld3_p16Experimentalneon and v7
Load multiple 3-element structures to three registers
vld3_p64Experimentalneon,aes and v8
Load multiple 3-element structures to three registers
vld3_s8Experimentalneon,v7
Load multiple 3-element structures to three registers
vld3_s16Experimentalneon,v7
Load multiple 3-element structures to three registers
vld3_s32Experimentalneon,v7
Load multiple 3-element structures to three registers
vld3_s64Experimentalneon,v7
Load multiple 3-element structures to three registers
vld3_u8Experimentalneon and v7
Load multiple 3-element structures to three registers
vld3_u16Experimentalneon and v7
Load multiple 3-element structures to three registers
vld3_u32Experimentalneon and v7
Load multiple 3-element structures to three registers
vld3_u64Experimentalneon and v7
Load multiple 3-element structures to three registers
vld3q_dup_f32Experimentalneon,v7
Load single 3-element structure and replicate to all lanes of three registers
vld3q_dup_p8Experimentalneon and v7
Load single 3-element structure and replicate to all lanes of three registers
vld3q_dup_p16Experimentalneon and v7
Load single 3-element structure and replicate to all lanes of three registers
vld3q_dup_s8Experimentalneon,v7
Load single 3-element structure and replicate to all lanes of three registers
vld3q_dup_s16Experimentalneon,v7
Load single 3-element structure and replicate to all lanes of three registers
vld3q_dup_s32Experimentalneon,v7
Load single 3-element structure and replicate to all lanes of three registers
vld3q_dup_u8Experimentalneon and v7
Load single 3-element structure and replicate to all lanes of three registers
vld3q_dup_u16Experimentalneon and v7
Load single 3-element structure and replicate to all lanes of three registers
vld3q_dup_u32Experimentalneon and v7
Load single 3-element structure and replicate to all lanes of three registers
vld3q_f32Experimentalneon,v7
Load multiple 3-element structures to three registers
vld3q_lane_f32Experimentalneon,v7
Load multiple 3-element structures to three registers
vld3q_lane_p16Experimentalneon and v7
Load multiple 3-element structures to three registers
vld3q_lane_s16Experimentalneon,v7
Load multiple 3-element structures to two registers
vld3q_lane_s32Experimentalneon,v7
Load multiple 3-element structures to two registers
vld3q_lane_u16Experimentalneon and v7
Load multiple 3-element structures to three registers
vld3q_lane_u32Experimentalneon and v7
Load multiple 3-element structures to three registers
vld3q_p8Experimentalneon and v7
Load multiple 3-element structures to three registers
vld3q_p16Experimentalneon and v7
Load multiple 3-element structures to three registers
vld3q_s8Experimentalneon,v7
Load multiple 3-element structures to three registers
vld3q_s16Experimentalneon,v7
Load multiple 3-element structures to three registers
vld3q_s32Experimentalneon,v7
Load multiple 3-element structures to three registers
vld3q_u8Experimentalneon and v7
Load multiple 3-element structures to three registers
vld3q_u16Experimentalneon and v7
Load multiple 3-element structures to three registers
vld3q_u32Experimentalneon and v7
Load multiple 3-element structures to three registers
vld4_dup_f32Experimentalneon,v7
Load single 4-element structure and replicate to all lanes of four registers
vld4_dup_p8Experimentalneon and v7
Load single 4-element structure and replicate to all lanes of four registers
vld4_dup_p16Experimentalneon and v7
Load single 4-element structure and replicate to all lanes of four registers
vld4_dup_p64Experimentalneon,aes and v8
Load single 4-element structure and replicate to all lanes of four registers
vld4_dup_s8Experimentalneon,v7
Load single 4-element structure and replicate to all lanes of four registers
vld4_dup_s16Experimentalneon,v7
Load single 4-element structure and replicate to all lanes of four registers
vld4_dup_s32Experimentalneon,v7
Load single 4-element structure and replicate to all lanes of four registers
vld4_dup_s64Experimentalneon,v7
Load single 4-element structure and replicate to all lanes of four registers
vld4_dup_u8Experimentalneon and v7
Load single 4-element structure and replicate to all lanes of four registers
vld4_dup_u16Experimentalneon and v7
Load single 4-element structure and replicate to all lanes of four registers
vld4_dup_u32Experimentalneon and v7
Load single 4-element structure and replicate to all lanes of four registers
vld4_dup_u64Experimentalneon and v7
Load single 4-element structure and replicate to all lanes of four registers
vld4_f32Experimentalneon,v7
Load multiple 4-element structures to four registers
vld4_lane_f32Experimentalneon,v7
Load multiple 4-element structures to four registers
vld4_lane_p8Experimentalneon and v7
Load multiple 4-element structures to four registers
vld4_lane_p16Experimentalneon and v7
Load multiple 4-element structures to four registers
vld4_lane_s8Experimentalneon,v7
Load multiple 4-element structures to four registers
vld4_lane_s16Experimentalneon,v7
Load multiple 4-element structures to four registers
vld4_lane_s32Experimentalneon,v7
Load multiple 4-element structures to four registers
vld4_lane_u8Experimentalneon and v7
Load multiple 4-element structures to four registers
vld4_lane_u16Experimentalneon and v7
Load multiple 4-element structures to four registers
vld4_lane_u32Experimentalneon and v7
Load multiple 4-element structures to four registers
vld4_p8Experimentalneon and v7
Load multiple 4-element structures to four registers
vld4_p16Experimentalneon and v7
Load multiple 4-element structures to four registers
vld4_p64Experimentalneon,aes and v8
Load multiple 4-element structures to four registers
vld4_s8Experimentalneon,v7
Load multiple 4-element structures to four registers
vld4_s16Experimentalneon,v7
Load multiple 4-element structures to four registers
vld4_s32Experimentalneon,v7
Load multiple 4-element structures to four registers
vld4_s64Experimentalneon,v7
Load multiple 4-element structures to four registers
vld4_u8Experimentalneon and v7
Load multiple 4-element structures to four registers
vld4_u16Experimentalneon and v7
Load multiple 4-element structures to four registers
vld4_u32Experimentalneon and v7
Load multiple 4-element structures to four registers
vld4_u64Experimentalneon and v7
Load multiple 4-element structures to four registers
vld4q_dup_f32Experimentalneon,v7
Load single 4-element structure and replicate to all lanes of four registers
vld4q_dup_p8Experimentalneon and v7
Load single 4-element structure and replicate to all lanes of four registers
vld4q_dup_p16Experimentalneon and v7
Load single 4-element structure and replicate to all lanes of four registers
vld4q_dup_s8Experimentalneon,v7
Load single 4-element structure and replicate to all lanes of four registers
vld4q_dup_s16Experimentalneon,v7
Load single 4-element structure and replicate to all lanes of four registers
vld4q_dup_s32Experimentalneon,v7
Load single 4-element structure and replicate to all lanes of four registers
vld4q_dup_u8Experimentalneon and v7
Load single 4-element structure and replicate to all lanes of four registers
vld4q_dup_u16Experimentalneon and v7
Load single 4-element structure and replicate to all lanes of four registers
vld4q_dup_u32Experimentalneon and v7
Load single 4-element structure and replicate to all lanes of four registers
vld4q_f32Experimentalneon,v7
Load multiple 4-element structures to four registers
vld4q_lane_f32Experimentalneon,v7
Load multiple 4-element structures to four registers
vld4q_lane_p16Experimentalneon and v7
Load multiple 4-element structures to four registers
vld4q_lane_s16Experimentalneon,v7
Load multiple 4-element structures to four registers
vld4q_lane_s32Experimentalneon,v7
Load multiple 4-element structures to four registers
vld4q_lane_u16Experimentalneon and v7
Load multiple 4-element structures to four registers
vld4q_lane_u32Experimentalneon and v7
Load multiple 4-element structures to four registers
vld4q_p8Experimentalneon and v7
Load multiple 4-element structures to four registers
vld4q_p16Experimentalneon and v7
Load multiple 4-element structures to four registers
vld4q_s8Experimentalneon,v7
Load multiple 4-element structures to four registers
vld4q_s16Experimentalneon,v7
Load multiple 4-element structures to four registers
vld4q_s32Experimentalneon,v7
Load multiple 4-element structures to four registers
vld4q_u8Experimentalneon and v7
Load multiple 4-element structures to four registers
vld4q_u16Experimentalneon and v7
Load multiple 4-element structures to four registers
vld4q_u32Experimentalneon and v7
Load multiple 4-element structures to four registers
vldrq_p128Experimentalneon and v7
Load SIMD&FP register (immediate offset)
vmax_f32Experimentalneon and v7
Maximum (vector)
vmax_s8Experimentalneon and v7
Maximum (vector)
vmax_s16Experimentalneon and v7
Maximum (vector)
vmax_s32Experimentalneon and v7
Maximum (vector)
vmax_u8Experimentalneon and v7
Maximum (vector)
vmax_u16Experimentalneon and v7
Maximum (vector)
vmax_u32Experimentalneon and v7
Maximum (vector)
vmaxnm_f32Experimentalneon and fp-armv8,v8
Floating-point Maximum Number (vector)
vmaxnmq_f32Experimentalneon and fp-armv8,v8
Floating-point Maximum Number (vector)
vmaxq_f32Experimentalneon and v7
Maximum (vector)
vmaxq_s8Experimentalneon and v7
Maximum (vector)
vmaxq_s16Experimentalneon and v7
Maximum (vector)
vmaxq_s32Experimentalneon and v7
Maximum (vector)
vmaxq_u8Experimentalneon and v7
Maximum (vector)
vmaxq_u16Experimentalneon and v7
Maximum (vector)
vmaxq_u32Experimentalneon and v7
Maximum (vector)
vmin_f32Experimentalneon and v7
Minimum (vector)
vmin_s8Experimentalneon and v7
Minimum (vector)
vmin_s16Experimentalneon and v7
Minimum (vector)
vmin_s32Experimentalneon and v7
Minimum (vector)
vmin_u8Experimentalneon and v7
Minimum (vector)
vmin_u16Experimentalneon and v7
Minimum (vector)
vmin_u32Experimentalneon and v7
Minimum (vector)
vminnm_f32Experimentalneon and fp-armv8,v8
Floating-point Minimum Number (vector)
vminnmq_f32Experimentalneon and fp-armv8,v8
Floating-point Minimum Number (vector)
vminq_f32Experimentalneon and v7
Minimum (vector)
vminq_s8Experimentalneon and v7
Minimum (vector)
vminq_s16Experimentalneon and v7
Minimum (vector)
vminq_s32Experimentalneon and v7
Minimum (vector)
vminq_u8Experimentalneon and v7
Minimum (vector)
vminq_u16Experimentalneon and v7
Minimum (vector)
vminq_u32Experimentalneon and v7
Minimum (vector)
vmla_f32Experimentalneon and v7
Floating-point multiply-add to accumulator
vmla_lane_f32Experimentalneon and v7
Vector multiply accumulate with scalar
vmla_lane_s16Experimentalneon and v7
Vector multiply accumulate with scalar
vmla_lane_s32Experimentalneon and v7
Vector multiply accumulate with scalar
vmla_lane_u16Experimentalneon and v7
Vector multiply accumulate with scalar
vmla_lane_u32Experimentalneon and v7
Vector multiply accumulate with scalar
vmla_laneq_f32Experimentalneon and v7
Vector multiply accumulate with scalar
vmla_laneq_s16Experimentalneon and v7
Vector multiply accumulate with scalar
vmla_laneq_s32Experimentalneon and v7
Vector multiply accumulate with scalar
vmla_laneq_u16Experimentalneon and v7
Vector multiply accumulate with scalar
vmla_laneq_u32Experimentalneon and v7
Vector multiply accumulate with scalar
vmla_n_f32Experimentalneon and v7
Vector multiply accumulate with scalar
vmla_n_s16Experimentalneon and v7
Vector multiply accumulate with scalar
vmla_n_s32Experimentalneon and v7
Vector multiply accumulate with scalar
vmla_n_u16Experimentalneon and v7
Vector multiply accumulate with scalar
vmla_n_u32Experimentalneon and v7
Vector multiply accumulate with scalar
vmla_s8Experimentalneon and v7
Multiply-add to accumulator
vmla_s16Experimentalneon and v7
Multiply-add to accumulator
vmla_s32Experimentalneon and v7
Multiply-add to accumulator
vmla_u8Experimentalneon and v7
Multiply-add to accumulator
vmla_u16Experimentalneon and v7
Multiply-add to accumulator
vmla_u32Experimentalneon and v7
Multiply-add to accumulator
vmlal_lane_s16Experimentalneon and v7
Vector widening multiply accumulate with scalar
vmlal_lane_s32Experimentalneon and v7
Vector widening multiply accumulate with scalar
vmlal_lane_u16Experimentalneon and v7
Vector widening multiply accumulate with scalar
vmlal_lane_u32Experimentalneon and v7
Vector widening multiply accumulate with scalar
vmlal_laneq_s16Experimentalneon and v7
Vector widening multiply accumulate with scalar
vmlal_laneq_s32Experimentalneon and v7
Vector widening multiply accumulate with scalar
vmlal_laneq_u16Experimentalneon and v7
Vector widening multiply accumulate with scalar
vmlal_laneq_u32Experimentalneon and v7
Vector widening multiply accumulate with scalar
vmlal_n_s16Experimentalneon and v7
Vector widening multiply accumulate with scalar
vmlal_n_s32Experimentalneon and v7
Vector widening multiply accumulate with scalar
vmlal_n_u16Experimentalneon and v7
Vector widening multiply accumulate with scalar
vmlal_n_u32Experimentalneon and v7
Vector widening multiply accumulate with scalar
vmlal_s8Experimentalneon and v7
Signed multiply-add long
vmlal_s16Experimentalneon and v7
Signed multiply-add long
vmlal_s32Experimentalneon and v7
Signed multiply-add long
vmlal_u8Experimentalneon and v7
Unsigned multiply-add long
vmlal_u16Experimentalneon and v7
Unsigned multiply-add long
vmlal_u32Experimentalneon and v7
Unsigned multiply-add long
vmlaq_f32Experimentalneon and v7
Floating-point multiply-add to accumulator
vmlaq_lane_f32Experimentalneon and v7
Vector multiply accumulate with scalar
vmlaq_lane_s16Experimentalneon and v7
Vector multiply accumulate with scalar
vmlaq_lane_s32Experimentalneon and v7
Vector multiply accumulate with scalar
vmlaq_lane_u16Experimentalneon and v7
Vector multiply accumulate with scalar
vmlaq_lane_u32Experimentalneon and v7
Vector multiply accumulate with scalar
vmlaq_laneq_f32Experimentalneon and v7
Vector multiply accumulate with scalar
vmlaq_laneq_s16Experimentalneon and v7
Vector multiply accumulate with scalar
vmlaq_laneq_s32Experimentalneon and v7
Vector multiply accumulate with scalar
vmlaq_laneq_u16Experimentalneon and v7
Vector multiply accumulate with scalar
vmlaq_laneq_u32Experimentalneon and v7
Vector multiply accumulate with scalar
vmlaq_n_f32Experimentalneon and v7
Vector multiply accumulate with scalar
vmlaq_n_s16Experimentalneon and v7
Vector multiply accumulate with scalar
vmlaq_n_s32Experimentalneon and v7
Vector multiply accumulate with scalar
vmlaq_n_u16Experimentalneon and v7
Vector multiply accumulate with scalar
vmlaq_n_u32Experimentalneon and v7
Vector multiply accumulate with scalar
vmlaq_s8Experimentalneon and v7
Multiply-add to accumulator
vmlaq_s16Experimentalneon and v7
Multiply-add to accumulator
vmlaq_s32Experimentalneon and v7
Multiply-add to accumulator
vmlaq_u8Experimentalneon and v7
Multiply-add to accumulator
vmlaq_u16Experimentalneon and v7
Multiply-add to accumulator
vmlaq_u32Experimentalneon and v7
Multiply-add to accumulator
vmls_f32Experimentalneon and v7
Floating-point multiply-subtract from accumulator
vmls_lane_f32Experimentalneon and v7
Vector multiply subtract with scalar
vmls_lane_s16Experimentalneon and v7
Vector multiply subtract with scalar
vmls_lane_s32Experimentalneon and v7
Vector multiply subtract with scalar
vmls_lane_u16Experimentalneon and v7
Vector multiply subtract with scalar
vmls_lane_u32Experimentalneon and v7
Vector multiply subtract with scalar
vmls_laneq_f32Experimentalneon and v7
Vector multiply subtract with scalar
vmls_laneq_s16Experimentalneon and v7
Vector multiply subtract with scalar
vmls_laneq_s32Experimentalneon and v7
Vector multiply subtract with scalar
vmls_laneq_u16Experimentalneon and v7
Vector multiply subtract with scalar
vmls_laneq_u32Experimentalneon and v7
Vector multiply subtract with scalar
vmls_n_f32Experimentalneon and v7
Vector multiply subtract with scalar
vmls_n_s16Experimentalneon and v7
Vector multiply subtract with scalar
vmls_n_s32Experimentalneon and v7
Vector multiply subtract with scalar
vmls_n_u16Experimentalneon and v7
Vector multiply subtract with scalar
vmls_n_u32Experimentalneon and v7
Vector multiply subtract with scalar
vmls_s8Experimentalneon and v7
Multiply-subtract from accumulator
vmls_s16Experimentalneon and v7
Multiply-subtract from accumulator
vmls_s32Experimentalneon and v7
Multiply-subtract from accumulator
vmls_u8Experimentalneon and v7
Multiply-subtract from accumulator
vmls_u16Experimentalneon and v7
Multiply-subtract from accumulator
vmls_u32Experimentalneon and v7
Multiply-subtract from accumulator
vmlsl_lane_s16Experimentalneon and v7
Vector widening multiply subtract with scalar
vmlsl_lane_s32Experimentalneon and v7
Vector widening multiply subtract with scalar
vmlsl_lane_u16Experimentalneon and v7
Vector widening multiply subtract with scalar
vmlsl_lane_u32Experimentalneon and v7
Vector widening multiply subtract with scalar
vmlsl_laneq_s16Experimentalneon and v7
Vector widening multiply subtract with scalar
vmlsl_laneq_s32Experimentalneon and v7
Vector widening multiply subtract with scalar
vmlsl_laneq_u16Experimentalneon and v7
Vector widening multiply subtract with scalar
vmlsl_laneq_u32Experimentalneon and v7
Vector widening multiply subtract with scalar
vmlsl_n_s16Experimentalneon and v7
Vector widening multiply subtract with scalar
vmlsl_n_s32Experimentalneon and v7
Vector widening multiply subtract with scalar
vmlsl_n_u16Experimentalneon and v7
Vector widening multiply subtract with scalar
vmlsl_n_u32Experimentalneon and v7
Vector widening multiply subtract with scalar
vmlsl_s8Experimentalneon and v7
Signed multiply-subtract long
vmlsl_s16Experimentalneon and v7
Signed multiply-subtract long
vmlsl_s32Experimentalneon and v7
Signed multiply-subtract long
vmlsl_u8Experimentalneon and v7
Unsigned multiply-subtract long
vmlsl_u16Experimentalneon and v7
Unsigned multiply-subtract long
vmlsl_u32Experimentalneon and v7
Unsigned multiply-subtract long
vmlsq_f32Experimentalneon and v7
Floating-point multiply-subtract from accumulator
vmlsq_lane_f32Experimentalneon and v7
Vector multiply subtract with scalar
vmlsq_lane_s16Experimentalneon and v7
Vector multiply subtract with scalar
vmlsq_lane_s32Experimentalneon and v7
Vector multiply subtract with scalar
vmlsq_lane_u16Experimentalneon and v7
Vector multiply subtract with scalar
vmlsq_lane_u32Experimentalneon and v7
Vector multiply subtract with scalar
vmlsq_laneq_f32Experimentalneon and v7
Vector multiply subtract with scalar
vmlsq_laneq_s16Experimentalneon and v7
Vector multiply subtract with scalar
vmlsq_laneq_s32Experimentalneon and v7
Vector multiply subtract with scalar
vmlsq_laneq_u16Experimentalneon and v7
Vector multiply subtract with scalar
vmlsq_laneq_u32Experimentalneon and v7
Vector multiply subtract with scalar
vmlsq_n_f32Experimentalneon and v7
Vector multiply subtract with scalar
vmlsq_n_s16Experimentalneon and v7
Vector multiply subtract with scalar
vmlsq_n_s32Experimentalneon and v7
Vector multiply subtract with scalar
vmlsq_n_u16Experimentalneon and v7
Vector multiply subtract with scalar
vmlsq_n_u32Experimentalneon and v7
Vector multiply subtract with scalar
vmlsq_s8Experimentalneon and v7
Multiply-subtract from accumulator
vmlsq_s16Experimentalneon and v7
Multiply-subtract from accumulator
vmlsq_s32Experimentalneon and v7
Multiply-subtract from accumulator
vmlsq_u8Experimentalneon and v7
Multiply-subtract from accumulator
vmlsq_u16Experimentalneon and v7
Multiply-subtract from accumulator
vmlsq_u32Experimentalneon and v7
Multiply-subtract from accumulator
vmmlaq_s32Experimentalneon,i8mm and v8
8-bit integer matrix multiply-accumulate
vmmlaq_u32Experimentalneon,i8mm and v8
8-bit integer matrix multiply-accumulate
vmov_n_f32Experimentalneon and v7
Duplicate vector element to vector or scalar
vmov_n_p8Experimentalneon and v7
Duplicate vector element to vector or scalar
vmov_n_p16Experimentalneon and v7
Duplicate vector element to vector or scalar
vmov_n_s8Experimentalneon and v7
Duplicate vector element to vector or scalar
vmov_n_s16Experimentalneon and v7
Duplicate vector element to vector or scalar
vmov_n_s32Experimentalneon and v7
Duplicate vector element to vector or scalar
vmov_n_s64Experimentalneon and v7
Duplicate vector element to vector or scalar
vmov_n_u8Experimentalneon and v7
Duplicate vector element to vector or scalar
vmov_n_u16Experimentalneon and v7
Duplicate vector element to vector or scalar
vmov_n_u32Experimentalneon and v7
Duplicate vector element to vector or scalar
vmov_n_u64Experimentalneon and v7
Duplicate vector element to vector or scalar
vmovl_s8Experimentalneon and v7
Vector long move.
vmovl_s16Experimentalneon and v7
Vector long move.
vmovl_s32Experimentalneon and v7
Vector long move.
vmovl_u8Experimentalneon and v7
Vector long move.
vmovl_u16Experimentalneon and v7
Vector long move.
vmovl_u32Experimentalneon and v7
Vector long move.
vmovn_s16Experimentalneon and v7
Vector narrow integer.
vmovn_s32Experimentalneon and v7
Vector narrow integer.
vmovn_s64Experimentalneon and v7
Vector narrow integer.
vmovn_u16Experimentalneon and v7
Vector narrow integer.
vmovn_u32Experimentalneon and v7
Vector narrow integer.
vmovn_u64Experimentalneon and v7
Vector narrow integer.
vmovq_n_f32Experimentalneon and v7
Duplicate vector element to vector or scalar
vmovq_n_p8Experimentalneon and v7
Duplicate vector element to vector or scalar
vmovq_n_p16Experimentalneon and v7
Duplicate vector element to vector or scalar
vmovq_n_s8Experimentalneon and v7
Duplicate vector element to vector or scalar
vmovq_n_s16Experimentalneon and v7
Duplicate vector element to vector or scalar
vmovq_n_s32Experimentalneon and v7
Duplicate vector element to vector or scalar
vmovq_n_s64Experimentalneon and v7
Duplicate vector element to vector or scalar
vmovq_n_u8Experimentalneon and v7
Duplicate vector element to vector or scalar
vmovq_n_u16Experimentalneon and v7
Duplicate vector element to vector or scalar
vmovq_n_u32Experimentalneon and v7
Duplicate vector element to vector or scalar
vmovq_n_u64Experimentalneon and v7
Duplicate vector element to vector or scalar
vmul_f32Experimentalneon and v7
Multiply
vmul_lane_f32Experimentalneon and v7
Floating-point multiply
vmul_lane_s16Experimentalneon and v7
Multiply
vmul_lane_s32Experimentalneon and v7
Multiply
vmul_lane_u16Experimentalneon and v7
Multiply
vmul_lane_u32Experimentalneon and v7
Multiply
vmul_laneq_f32Experimentalneon and v7
Floating-point multiply
vmul_laneq_s16Experimentalneon and v7
Multiply
vmul_laneq_s32Experimentalneon and v7
Multiply
vmul_laneq_u16Experimentalneon and v7
Multiply
vmul_laneq_u32Experimentalneon and v7
Multiply
vmul_n_f32Experimentalneon and v7
Vector multiply by scalar
vmul_n_s16Experimentalneon and v7
Vector multiply by scalar
vmul_n_s32Experimentalneon and v7
Vector multiply by scalar
vmul_n_u16Experimentalneon and v7
Vector multiply by scalar
vmul_n_u32Experimentalneon and v7
Vector multiply by scalar
vmul_p8Experimentalneon and v7
Polynomial multiply
vmul_s8Experimentalneon and v7
Multiply
vmul_s16Experimentalneon and v7
Multiply
vmul_s32Experimentalneon and v7
Multiply
vmul_u8Experimentalneon and v7
Multiply
vmul_u16Experimentalneon and v7
Multiply
vmul_u32Experimentalneon and v7
Multiply
vmull_lane_s16Experimentalneon and v7
Vector long multiply by scalar
vmull_lane_s32Experimentalneon and v7
Vector long multiply by scalar
vmull_lane_u16Experimentalneon and v7
Vector long multiply by scalar
vmull_lane_u32Experimentalneon and v7
Vector long multiply by scalar
vmull_laneq_s16Experimentalneon and v7
Vector long multiply by scalar
vmull_laneq_s32Experimentalneon and v7
Vector long multiply by scalar
vmull_laneq_u16Experimentalneon and v7
Vector long multiply by scalar
vmull_laneq_u32Experimentalneon and v7
Vector long multiply by scalar
vmull_n_s16Experimentalneon and v7
Vector long multiply with scalar
vmull_n_s32Experimentalneon and v7
Vector long multiply with scalar
vmull_n_u16Experimentalneon and v7
Vector long multiply with scalar
vmull_n_u32Experimentalneon and v7
Vector long multiply with scalar
vmull_p8Experimentalneon and v7
Polynomial multiply long
vmull_s8Experimentalneon and v7
Signed multiply long
vmull_s16Experimentalneon and v7
Signed multiply long
vmull_s32Experimentalneon and v7
Signed multiply long
vmull_u8Experimentalneon and v7
Unsigned multiply long
vmull_u16Experimentalneon and v7
Unsigned multiply long
vmull_u32Experimentalneon and v7
Unsigned multiply long
vmulq_f32Experimentalneon and v7
Multiply
vmulq_lane_f32Experimentalneon and v7
Floating-point multiply
vmulq_lane_s16Experimentalneon and v7
Multiply
vmulq_lane_s32Experimentalneon and v7
Multiply
vmulq_lane_u16Experimentalneon and v7
Multiply
vmulq_lane_u32Experimentalneon and v7
Multiply
vmulq_laneq_f32Experimentalneon and v7
Floating-point multiply
vmulq_laneq_s16Experimentalneon and v7
Multiply
vmulq_laneq_s32Experimentalneon and v7
Multiply
vmulq_laneq_u16Experimentalneon and v7
Multiply
vmulq_laneq_u32Experimentalneon and v7
Multiply
vmulq_n_f32Experimentalneon and v7
Vector multiply by scalar
vmulq_n_s16Experimentalneon and v7
Vector multiply by scalar
vmulq_n_s32Experimentalneon and v7
Vector multiply by scalar
vmulq_n_u16Experimentalneon and v7
Vector multiply by scalar
vmulq_n_u32Experimentalneon and v7
Vector multiply by scalar
vmulq_p8Experimentalneon and v7
Polynomial multiply
vmulq_s8Experimentalneon and v7
Multiply
vmulq_s16Experimentalneon and v7
Multiply
vmulq_s32Experimentalneon and v7
Multiply
vmulq_u8Experimentalneon and v7
Multiply
vmulq_u16Experimentalneon and v7
Multiply
vmulq_u32Experimentalneon and v7
Multiply
vmvn_p8Experimentalneon and v7
Vector bitwise not.
vmvn_s8Experimentalneon and v7
Vector bitwise not.
vmvn_s16Experimentalneon and v7
Vector bitwise not.
vmvn_s32Experimentalneon and v7
Vector bitwise not.
vmvn_u8Experimentalneon and v7
Vector bitwise not.
vmvn_u16Experimentalneon and v7
Vector bitwise not.
vmvn_u32Experimentalneon and v7
Vector bitwise not.
vmvnq_p8Experimentalneon and v7
Vector bitwise not.
vmvnq_s8Experimentalneon and v7
Vector bitwise not.
vmvnq_s16Experimentalneon and v7
Vector bitwise not.
vmvnq_s32Experimentalneon and v7
Vector bitwise not.
vmvnq_u8Experimentalneon and v7
Vector bitwise not.
vmvnq_u16Experimentalneon and v7
Vector bitwise not.
vmvnq_u32Experimentalneon and v7
Vector bitwise not.
vneg_f32Experimentalneon and v7
Negate
vneg_s8Experimentalneon and v7
Negate
vneg_s16Experimentalneon and v7
Negate
vneg_s32Experimentalneon and v7
Negate
vnegq_f32Experimentalneon and v7
Negate
vnegq_s8Experimentalneon and v7
Negate
vnegq_s16Experimentalneon and v7
Negate
vnegq_s32Experimentalneon and v7
Negate
vorn_s8Experimentalneon and v7
Vector bitwise inclusive OR NOT
vorn_s16Experimentalneon and v7
Vector bitwise inclusive OR NOT
vorn_s32Experimentalneon and v7
Vector bitwise inclusive OR NOT
vorn_s64Experimentalneon and v7
Vector bitwise inclusive OR NOT
vorn_u8Experimentalneon and v7
Vector bitwise inclusive OR NOT
vorn_u16Experimentalneon and v7
Vector bitwise inclusive OR NOT
vorn_u32Experimentalneon and v7
Vector bitwise inclusive OR NOT
vorn_u64Experimentalneon and v7
Vector bitwise inclusive OR NOT
vornq_s8Experimentalneon and v7
Vector bitwise inclusive OR NOT
vornq_s16Experimentalneon and v7
Vector bitwise inclusive OR NOT
vornq_s32Experimentalneon and v7
Vector bitwise inclusive OR NOT
vornq_s64Experimentalneon and v7
Vector bitwise inclusive OR NOT
vornq_u8Experimentalneon and v7
Vector bitwise inclusive OR NOT
vornq_u16Experimentalneon and v7
Vector bitwise inclusive OR NOT
vornq_u32Experimentalneon and v7
Vector bitwise inclusive OR NOT
vornq_u64Experimentalneon and v7
Vector bitwise inclusive OR NOT
vorr_s8Experimentalneon and v7
Vector bitwise or (immediate, inclusive)
vorr_s16Experimentalneon and v7
Vector bitwise or (immediate, inclusive)
vorr_s32Experimentalneon and v7
Vector bitwise or (immediate, inclusive)
vorr_s64Experimentalneon and v7
Vector bitwise or (immediate, inclusive)
vorr_u8Experimentalneon and v7
Vector bitwise or (immediate, inclusive)
vorr_u16Experimentalneon and v7
Vector bitwise or (immediate, inclusive)
vorr_u32Experimentalneon and v7
Vector bitwise or (immediate, inclusive)
vorr_u64Experimentalneon and v7
Vector bitwise or (immediate, inclusive)
vorrq_s8Experimentalneon and v7
Vector bitwise or (immediate, inclusive)
vorrq_s16Experimentalneon and v7
Vector bitwise or (immediate, inclusive)
vorrq_s32Experimentalneon and v7
Vector bitwise or (immediate, inclusive)
vorrq_s64Experimentalneon and v7
Vector bitwise or (immediate, inclusive)
vorrq_u8Experimentalneon and v7
Vector bitwise or (immediate, inclusive)
vorrq_u16Experimentalneon and v7
Vector bitwise or (immediate, inclusive)
vorrq_u32Experimentalneon and v7
Vector bitwise or (immediate, inclusive)
vorrq_u64Experimentalneon and v7
Vector bitwise or (immediate, inclusive)
vpadal_s8Experimentalneon and v7
Signed Add and Accumulate Long Pairwise.
vpadal_s16Experimentalneon and v7
Signed Add and Accumulate Long Pairwise.
vpadal_s32Experimentalneon and v7
Signed Add and Accumulate Long Pairwise.
vpadal_u8Experimentalneon and v7
Unsigned Add and Accumulate Long Pairwise.
vpadal_u16Experimentalneon and v7
Unsigned Add and Accumulate Long Pairwise.
vpadal_u32Experimentalneon and v7
Unsigned Add and Accumulate Long Pairwise.
vpadalq_s8Experimentalneon and v7
Signed Add and Accumulate Long Pairwise.
vpadalq_s16Experimentalneon and v7
Signed Add and Accumulate Long Pairwise.
vpadalq_s32Experimentalneon and v7
Signed Add and Accumulate Long Pairwise.
vpadalq_u8Experimentalneon and v7
Unsigned Add and Accumulate Long Pairwise.
vpadalq_u16Experimentalneon and v7
Unsigned Add and Accumulate Long Pairwise.
vpadalq_u32Experimentalneon and v7
Unsigned Add and Accumulate Long Pairwise.
vpadd_f32Experimentalneon and v7
Floating-point add pairwise
vpadd_s8Experimentalneon and v7
Add pairwise.
vpadd_s16Experimentalneon and v7
Add pairwise.
vpadd_s32Experimentalneon and v7
Add pairwise.
vpadd_u8Experimentalneon and v7
Add pairwise.
vpadd_u16Experimentalneon and v7
Add pairwise.
vpadd_u32Experimentalneon and v7
Add pairwise.
vpaddl_s8Experimentalneon and v7
Signed Add Long Pairwise.
vpaddl_s16Experimentalneon and v7
Signed Add Long Pairwise.
vpaddl_s32Experimentalneon and v7
Signed Add Long Pairwise.
vpaddl_u8Experimentalneon and v7
Unsigned Add Long Pairwise.
vpaddl_u16Experimentalneon and v7
Unsigned Add Long Pairwise.
vpaddl_u32Experimentalneon and v7
Unsigned Add Long Pairwise.
vpaddlq_s8Experimentalneon and v7
Signed Add Long Pairwise.
vpaddlq_s16Experimentalneon and v7
Signed Add Long Pairwise.
vpaddlq_s32Experimentalneon and v7
Signed Add Long Pairwise.
vpaddlq_u8Experimentalneon and v7
Unsigned Add Long Pairwise.
vpaddlq_u16Experimentalneon and v7
Unsigned Add Long Pairwise.
vpaddlq_u32Experimentalneon and v7
Unsigned Add Long Pairwise.
vpmax_f32Experimentalneon and v7
Folding maximum of adjacent pairs
vpmax_s8Experimentalneon and v7
Folding maximum of adjacent pairs
vpmax_s16Experimentalneon and v7
Folding maximum of adjacent pairs
vpmax_s32Experimentalneon and v7
Folding maximum of adjacent pairs
vpmax_u8Experimentalneon and v7
Folding maximum of adjacent pairs
vpmax_u16Experimentalneon and v7
Folding maximum of adjacent pairs
vpmax_u32Experimentalneon and v7
Folding maximum of adjacent pairs
vpmin_f32Experimentalneon and v7
Folding minimum of adjacent pairs
vpmin_s8Experimentalneon and v7
Folding minimum of adjacent pairs
vpmin_s16Experimentalneon and v7
Folding minimum of adjacent pairs
vpmin_s32Experimentalneon and v7
Folding minimum of adjacent pairs
vpmin_u8Experimentalneon and v7
Folding minimum of adjacent pairs
vpmin_u16Experimentalneon and v7
Folding minimum of adjacent pairs
vpmin_u32Experimentalneon and v7
Folding minimum of adjacent pairs
vqabs_s8Experimentalneon and v7
Signed saturating Absolute value
vqabs_s16Experimentalneon and v7
Signed saturating Absolute value
vqabs_s32Experimentalneon and v7
Signed saturating Absolute value
vqabsq_s8Experimentalneon and v7
Signed saturating Absolute value
vqabsq_s16Experimentalneon and v7
Signed saturating Absolute value
vqabsq_s32Experimentalneon and v7
Signed saturating Absolute value
vqadd_s8Experimentalneon and v7
Saturating add
vqadd_s16Experimentalneon and v7
Saturating add
vqadd_s32Experimentalneon and v7
Saturating add
vqadd_s64Experimentalneon and v7
Saturating add
vqadd_u8Experimentalneon and v7
Saturating add
vqadd_u16Experimentalneon and v7
Saturating add
vqadd_u32Experimentalneon and v7
Saturating add
vqadd_u64Experimentalneon and v7
Saturating add
vqaddq_s8Experimentalneon and v7
Saturating add
vqaddq_s16Experimentalneon and v7
Saturating add
vqaddq_s32Experimentalneon and v7
Saturating add
vqaddq_s64Experimentalneon and v7
Saturating add
vqaddq_u8Experimentalneon and v7
Saturating add
vqaddq_u16Experimentalneon and v7
Saturating add
vqaddq_u32Experimentalneon and v7
Saturating add
vqaddq_u64Experimentalneon and v7
Saturating add
vqdmlal_lane_s16Experimentalneon and v7
Vector widening saturating doubling multiply accumulate with scalar
vqdmlal_lane_s32Experimentalneon and v7
Vector widening saturating doubling multiply accumulate with scalar
vqdmlal_n_s16Experimentalneon and v7
Vector widening saturating doubling multiply accumulate with scalar
vqdmlal_n_s32Experimentalneon and v7
Vector widening saturating doubling multiply accumulate with scalar
vqdmlal_s16Experimentalneon and v7
Signed saturating doubling multiply-add long
vqdmlal_s32Experimentalneon and v7
Signed saturating doubling multiply-add long
vqdmlsl_lane_s16Experimentalneon and v7
Vector widening saturating doubling multiply subtract with scalar
vqdmlsl_lane_s32Experimentalneon and v7
Vector widening saturating doubling multiply subtract with scalar
vqdmlsl_n_s16Experimentalneon and v7
Vector widening saturating doubling multiply subtract with scalar
vqdmlsl_n_s32Experimentalneon and v7
Vector widening saturating doubling multiply subtract with scalar
vqdmlsl_s16Experimentalneon and v7
Signed saturating doubling multiply-subtract long
vqdmlsl_s32Experimentalneon and v7
Signed saturating doubling multiply-subtract long
vqdmulh_laneq_s16Experimentalneon and v7
Vector saturating doubling multiply high by scalar
vqdmulh_laneq_s32Experimentalneon and v7
Vector saturating doubling multiply high by scalar
vqdmulh_n_s16Experimentalneon and v7
Vector saturating doubling multiply high with scalar
vqdmulh_n_s32Experimentalneon and v7
Vector saturating doubling multiply high with scalar
vqdmulh_s16Experimentalneon and v7
Signed saturating doubling multiply returning high half
vqdmulh_s32Experimentalneon and v7
Signed saturating doubling multiply returning high half
vqdmulhq_laneq_s16Experimentalneon and v7
Vector saturating doubling multiply high by scalar
vqdmulhq_laneq_s32Experimentalneon and v7
Vector saturating doubling multiply high by scalar
vqdmulhq_n_s16Experimentalneon and v7
Vector saturating doubling multiply high with scalar
vqdmulhq_n_s32Experimentalneon and v7
Vector saturating doubling multiply high with scalar
vqdmulhq_s16Experimentalneon and v7
Signed saturating doubling multiply returning high half
vqdmulhq_s32Experimentalneon and v7
Signed saturating doubling multiply returning high half
vqdmull_lane_s16Experimentalneon and v7
Vector saturating doubling long multiply by scalar
vqdmull_lane_s32Experimentalneon and v7
Vector saturating doubling long multiply by scalar
vqdmull_n_s16Experimentalneon and v7
Vector saturating doubling long multiply with scalar
vqdmull_n_s32Experimentalneon and v7
Vector saturating doubling long multiply with scalar
vqdmull_s16Experimentalneon and v7
Signed saturating doubling multiply long
vqdmull_s32Experimentalneon and v7
Signed saturating doubling multiply long
vqmovn_s16Experimentalneon and v7
Signed saturating extract narrow
vqmovn_s32Experimentalneon and v7
Signed saturating extract narrow
vqmovn_s64Experimentalneon and v7
Signed saturating extract narrow
vqmovn_u16Experimentalneon and v7
Unsigned saturating extract narrow
vqmovn_u32Experimentalneon and v7
Unsigned saturating extract narrow
vqmovn_u64Experimentalneon and v7
Unsigned saturating extract narrow
vqmovun_s16Experimentalneon and v7
Signed saturating extract unsigned narrow
vqmovun_s32Experimentalneon and v7
Signed saturating extract unsigned narrow
vqmovun_s64Experimentalneon and v7
Signed saturating extract unsigned narrow
vqneg_s8Experimentalneon and v7
Signed saturating negate
vqneg_s16Experimentalneon and v7
Signed saturating negate
vqneg_s32Experimentalneon and v7
Signed saturating negate
vqnegq_s8Experimentalneon and v7
Signed saturating negate
vqnegq_s16Experimentalneon and v7
Signed saturating negate
vqnegq_s32Experimentalneon and v7
Signed saturating negate
vqrdmulh_lane_s16Experimentalneon and v7
Vector rounding saturating doubling multiply high by scalar
vqrdmulh_lane_s32Experimentalneon and v7
Vector rounding saturating doubling multiply high by scalar
vqrdmulh_laneq_s16Experimentalneon and v7
Vector rounding saturating doubling multiply high by scalar
vqrdmulh_laneq_s32Experimentalneon and v7
Vector rounding saturating doubling multiply high by scalar
vqrdmulh_n_s16Experimentalneon and v7
Vector saturating rounding doubling multiply high with scalar
vqrdmulh_n_s32Experimentalneon and v7
Vector saturating rounding doubling multiply high with scalar
vqrdmulh_s16Experimentalneon and v7
Signed saturating rounding doubling multiply returning high half
vqrdmulh_s32Experimentalneon and v7
Signed saturating rounding doubling multiply returning high half
vqrdmulhq_lane_s16Experimentalneon and v7
Vector rounding saturating doubling multiply high by scalar
vqrdmulhq_lane_s32Experimentalneon and v7
Vector rounding saturating doubling multiply high by scalar
vqrdmulhq_laneq_s16Experimentalneon and v7
Vector rounding saturating doubling multiply high by scalar
vqrdmulhq_laneq_s32Experimentalneon and v7
Vector rounding saturating doubling multiply high by scalar
vqrdmulhq_n_s16Experimentalneon and v7
Vector saturating rounding doubling multiply high with scalar
vqrdmulhq_n_s32Experimentalneon and v7
Vector saturating rounding doubling multiply high with scalar
vqrdmulhq_s16Experimentalneon and v7
Signed saturating rounding doubling multiply returning high half
vqrdmulhq_s32Experimentalneon and v7
Signed saturating rounding doubling multiply returning high half
vqrshl_s8Experimentalneon and v7
Signed saturating rounding shift left
vqrshl_s16Experimentalneon and v7
Signed saturating rounding shift left
vqrshl_s32Experimentalneon and v7
Signed saturating rounding shift left
vqrshl_s64Experimentalneon and v7
Signed saturating rounding shift left
vqrshl_u8Experimentalneon and v7
Unsigned signed saturating rounding shift left
vqrshl_u16Experimentalneon and v7
Unsigned signed saturating rounding shift left
vqrshl_u32Experimentalneon and v7
Unsigned signed saturating rounding shift left
vqrshl_u64Experimentalneon and v7
Unsigned signed saturating rounding shift left
vqrshlq_s8Experimentalneon and v7
Signed saturating rounding shift left
vqrshlq_s16Experimentalneon and v7
Signed saturating rounding shift left
vqrshlq_s32Experimentalneon and v7
Signed saturating rounding shift left
vqrshlq_s64Experimentalneon and v7
Signed saturating rounding shift left
vqrshlq_u8Experimentalneon and v7
Unsigned signed saturating rounding shift left
vqrshlq_u16Experimentalneon and v7
Unsigned signed saturating rounding shift left
vqrshlq_u32Experimentalneon and v7
Unsigned signed saturating rounding shift left
vqrshlq_u64Experimentalneon and v7
Unsigned signed saturating rounding shift left
vqrshrn_n_s16Experimentalneon,v7
Signed saturating rounded shift right narrow
vqrshrn_n_s32Experimentalneon,v7
Signed saturating rounded shift right narrow
vqrshrn_n_s64Experimentalneon,v7
Signed saturating rounded shift right narrow
vqrshrn_n_u16Experimentalneon,v7
Unsigned signed saturating rounded shift right narrow
vqrshrn_n_u32Experimentalneon,v7
Unsigned signed saturating rounded shift right narrow
vqrshrn_n_u64Experimentalneon,v7
Unsigned signed saturating rounded shift right narrow
vqrshrun_n_s16Experimentalneon,v7
Signed saturating rounded shift right unsigned narrow
vqrshrun_n_s32Experimentalneon,v7
Signed saturating rounded shift right unsigned narrow
vqrshrun_n_s64Experimentalneon,v7
Signed saturating rounded shift right unsigned narrow
vqshl_n_s8Experimentalneon and v7
Signed saturating shift left
vqshl_n_s16Experimentalneon and v7
Signed saturating shift left
vqshl_n_s32Experimentalneon and v7
Signed saturating shift left
vqshl_n_s64Experimentalneon and v7
Signed saturating shift left
vqshl_n_u8Experimentalneon and v7
Unsigned saturating shift left
vqshl_n_u16Experimentalneon and v7
Unsigned saturating shift left
vqshl_n_u32Experimentalneon and v7
Unsigned saturating shift left
vqshl_n_u64Experimentalneon and v7
Unsigned saturating shift left
vqshl_s8Experimentalneon and v7
Signed saturating shift left
vqshl_s16Experimentalneon and v7
Signed saturating shift left
vqshl_s32Experimentalneon and v7
Signed saturating shift left
vqshl_s64Experimentalneon and v7
Signed saturating shift left
vqshl_u8Experimentalneon and v7
Unsigned saturating shift left
vqshl_u16Experimentalneon and v7
Unsigned saturating shift left
vqshl_u32Experimentalneon and v7
Unsigned saturating shift left
vqshl_u64Experimentalneon and v7
Unsigned saturating shift left
vqshlq_n_s8Experimentalneon and v7
Signed saturating shift left
vqshlq_n_s16Experimentalneon and v7
Signed saturating shift left
vqshlq_n_s32Experimentalneon and v7
Signed saturating shift left
vqshlq_n_s64Experimentalneon and v7
Signed saturating shift left
vqshlq_n_u8Experimentalneon and v7
Unsigned saturating shift left
vqshlq_n_u16Experimentalneon and v7
Unsigned saturating shift left
vqshlq_n_u32Experimentalneon and v7
Unsigned saturating shift left
vqshlq_n_u64Experimentalneon and v7
Unsigned saturating shift left
vqshlq_s8Experimentalneon and v7
Signed saturating shift left
vqshlq_s16Experimentalneon and v7
Signed saturating shift left
vqshlq_s32Experimentalneon and v7
Signed saturating shift left
vqshlq_s64Experimentalneon and v7
Signed saturating shift left
vqshlq_u8Experimentalneon and v7
Unsigned saturating shift left
vqshlq_u16Experimentalneon and v7
Unsigned saturating shift left
vqshlq_u32Experimentalneon and v7
Unsigned saturating shift left
vqshlq_u64Experimentalneon and v7
Unsigned saturating shift left
vqshlu_n_s8Experimentalneon,v7
Signed saturating shift left unsigned
vqshlu_n_s16Experimentalneon,v7
Signed saturating shift left unsigned
vqshlu_n_s32Experimentalneon,v7
Signed saturating shift left unsigned
vqshlu_n_s64Experimentalneon,v7
Signed saturating shift left unsigned
vqshluq_n_s8Experimentalneon,v7
Signed saturating shift left unsigned
vqshluq_n_s16Experimentalneon,v7
Signed saturating shift left unsigned
vqshluq_n_s32Experimentalneon,v7
Signed saturating shift left unsigned
vqshluq_n_s64Experimentalneon,v7
Signed saturating shift left unsigned
vqshrn_n_s16Experimentalneon,v7
Signed saturating shift right narrow
vqshrn_n_s32Experimentalneon,v7
Signed saturating shift right narrow
vqshrn_n_s64Experimentalneon,v7
Signed saturating shift right narrow
vqshrn_n_u16Experimentalneon,v7
Unsigned saturating shift right narrow
vqshrn_n_u32Experimentalneon,v7
Unsigned saturating shift right narrow
vqshrn_n_u64Experimentalneon,v7
Unsigned saturating shift right narrow
vqshrun_n_s16Experimentalneon,v7
Signed saturating shift right unsigned narrow
vqshrun_n_s32Experimentalneon,v7
Signed saturating shift right unsigned narrow
vqshrun_n_s64Experimentalneon,v7
Signed saturating shift right unsigned narrow
vqsub_s8Experimentalneon and v7
Saturating subtract
vqsub_s16Experimentalneon and v7
Saturating subtract
vqsub_s32Experimentalneon and v7
Saturating subtract
vqsub_s64Experimentalneon and v7
Saturating subtract
vqsub_u8Experimentalneon and v7
Saturating subtract
vqsub_u16Experimentalneon and v7
Saturating subtract
vqsub_u32Experimentalneon and v7
Saturating subtract
vqsub_u64Experimentalneon and v7
Saturating subtract
vqsubq_s8Experimentalneon and v7
Saturating subtract
vqsubq_s16Experimentalneon and v7
Saturating subtract
vqsubq_s32Experimentalneon and v7
Saturating subtract
vqsubq_s64Experimentalneon and v7
Saturating subtract
vqsubq_u8Experimentalneon and v7
Saturating subtract
vqsubq_u16Experimentalneon and v7
Saturating subtract
vqsubq_u32Experimentalneon and v7
Saturating subtract
vqsubq_u64Experimentalneon and v7
Saturating subtract
vraddhn_high_s16Experimentalneon and v7
Rounding Add returning High Narrow (high half).
vraddhn_high_s32Experimentalneon and v7
Rounding Add returning High Narrow (high half).
vraddhn_high_s64Experimentalneon and v7
Rounding Add returning High Narrow (high half).
vraddhn_high_u16Experimentalneon and v7
Rounding Add returning High Narrow (high half).
vraddhn_high_u32Experimentalneon and v7
Rounding Add returning High Narrow (high half).
vraddhn_high_u64Experimentalneon and v7
Rounding Add returning High Narrow (high half).
vraddhn_s16Experimentalneon and v7
Rounding Add returning High Narrow.
vraddhn_s32Experimentalneon and v7
Rounding Add returning High Narrow.
vraddhn_s64Experimentalneon and v7
Rounding Add returning High Narrow.
vraddhn_u16Experimentalneon and v7
Rounding Add returning High Narrow.
vraddhn_u32Experimentalneon and v7
Rounding Add returning High Narrow.
vraddhn_u64Experimentalneon and v7
Rounding Add returning High Narrow.
vrecpe_f32Experimentalneon and v7
Reciprocal estimate.
vrecpe_u32Experimentalneon and v7
Unsigned reciprocal estimate
vrecpeq_f32Experimentalneon and v7
Reciprocal estimate.
vrecpeq_u32Experimentalneon and v7
Unsigned reciprocal estimate
vrecps_f32Experimentalneon and v7
Floating-point reciprocal step
vrecpsq_f32Experimentalneon and v7
Floating-point reciprocal step
vreinterpret_f32_p8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_f32_p16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_f32_s8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_f32_s16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_f32_s32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_f32_s64Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_f32_u8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_f32_u16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_f32_u32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_f32_u64Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_p8_f32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_p8_p16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_p8_p64Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpret_p8_s8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_p8_s16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_p8_s32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_p8_s64Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_p8_u8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_p8_u16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_p8_u32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_p8_u64Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_p16_f32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_p16_p8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_p16_p64Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpret_p16_s8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_p16_s16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_p16_s32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_p16_s64Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_p16_u8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_p16_u16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_p16_u32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_p16_u64Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_p64_p8Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpret_p64_p16Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpret_p64_s8Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpret_p64_s16Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpret_p64_s32Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpret_p64_u8Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpret_p64_u16Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpret_p64_u32Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpret_s8_f32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_s8_p8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_s8_p16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_s8_p64Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpret_s8_s16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_s8_s32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_s8_s64Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_s8_u8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_s8_u16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_s8_u32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_s8_u64Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_s16_f32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_s16_p8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_s16_p16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_s16_p64Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpret_s16_s8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_s16_s32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_s16_s64Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_s16_u8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_s16_u16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_s16_u32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_s16_u64Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_s32_f32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_s32_p8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_s32_p16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_s32_p64Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpret_s32_s8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_s32_s16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_s32_s64Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_s32_u8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_s32_u16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_s32_u32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_s32_u64Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_s64_f32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_s64_p8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_s64_p16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_s64_s8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_s64_s16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_s64_s32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_s64_u8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_s64_u16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_s64_u32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_s64_u64Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_u8_f32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_u8_p8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_u8_p16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_u8_p64Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpret_u8_s8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_u8_s16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_u8_s32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_u8_s64Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_u8_u16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_u8_u32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_u8_u64Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_u16_f32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_u16_p8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_u16_p16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_u16_p64Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpret_u16_s8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_u16_s16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_u16_s32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_u16_s64Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_u16_u8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_u16_u32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_u16_u64Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_u32_f32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_u32_p8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_u32_p16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_u32_p64Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpret_u32_s8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_u32_s16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_u32_s32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_u32_s64Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_u32_u8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_u32_u16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_u32_u64Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_u64_f32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_u64_p8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_u64_p16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_u64_s8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_u64_s16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_u64_s32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_u64_s64Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_u64_u8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_u64_u16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpret_u64_u32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_f32_p8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_f32_p16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_f32_p128Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_f32_s8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_f32_s16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_f32_s32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_f32_s64Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_f32_u8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_f32_u16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_f32_u32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_f32_u64Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_p8_f32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_p8_p16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_p8_p64Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpretq_p8_p128Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpretq_p8_s8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_p8_s16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_p8_s32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_p8_s64Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_p8_u8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_p8_u16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_p8_u32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_p8_u64Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_p16_f32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_p16_p8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_p16_p64Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpretq_p16_p128Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpretq_p16_s8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_p16_s16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_p16_s32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_p16_s64Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_p16_u8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_p16_u16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_p16_u32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_p16_u64Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_p64_p8Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpretq_p64_p16Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpretq_p64_p128Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpretq_p64_s8Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpretq_p64_s16Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpretq_p64_s32Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpretq_p64_u8Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpretq_p64_u16Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpretq_p64_u32Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpretq_p128_f32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_p128_p8Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpretq_p128_p16Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpretq_p128_p64Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpretq_p128_s8Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpretq_p128_s16Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpretq_p128_s32Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpretq_p128_s64Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpretq_p128_u8Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpretq_p128_u16Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpretq_p128_u32Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpretq_p128_u64Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpretq_s8_f32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_s8_p8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_s8_p16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_s8_p64Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpretq_s8_p128Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpretq_s8_s16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_s8_s32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_s8_s64Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_s8_u8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_s8_u16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_s8_u32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_s8_u64Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_s16_f32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_s16_p8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_s16_p16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_s16_p64Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpretq_s16_p128Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpretq_s16_s8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_s16_s32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_s16_s64Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_s16_u8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_s16_u16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_s16_u32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_s16_u64Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_s32_f32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_s32_p8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_s32_p16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_s32_p64Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpretq_s32_p128Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpretq_s32_s8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_s32_s16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_s32_s64Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_s32_u8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_s32_u16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_s32_u32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_s32_u64Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_s64_f32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_s64_p8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_s64_p16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_s64_p128Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpretq_s64_s8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_s64_s16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_s64_s32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_s64_u8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_s64_u16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_s64_u32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_s64_u64Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_u8_f32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_u8_p8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_u8_p16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_u8_p64Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpretq_u8_p128Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpretq_u8_s8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_u8_s16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_u8_s32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_u8_s64Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_u8_u16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_u8_u32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_u8_u64Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_u16_f32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_u16_p8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_u16_p16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_u16_p64Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpretq_u16_p128Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpretq_u16_s8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_u16_s16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_u16_s32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_u16_s64Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_u16_u8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_u16_u32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_u16_u64Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_u32_f32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_u32_p8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_u32_p16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_u32_p64Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpretq_u32_p128Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpretq_u32_s8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_u32_s16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_u32_s32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_u32_s64Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_u32_u8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_u32_u16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_u32_u64Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_u64_f32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_u64_p8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_u64_p16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_u64_p128Experimentalneon,aes and v8
Vector reinterpret cast operation
vreinterpretq_u64_s8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_u64_s16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_u64_s32Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_u64_s64Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_u64_u8Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_u64_u16Experimentalneon and v7
Vector reinterpret cast operation
vreinterpretq_u64_u32Experimentalneon and v7
Vector reinterpret cast operation
vrev16_p8Experimentalneon and v7
Reversing vector elements (swap endianness)
vrev16_s8Experimentalneon and v7
Reversing vector elements (swap endianness)
vrev16_u8Experimentalneon and v7
Reversing vector elements (swap endianness)
vrev16q_p8Experimentalneon and v7
Reversing vector elements (swap endianness)
vrev16q_s8Experimentalneon and v7
Reversing vector elements (swap endianness)
vrev16q_u8Experimentalneon and v7
Reversing vector elements (swap endianness)
vrev32_p8Experimentalneon and v7
Reversing vector elements (swap endianness)
vrev32_p16Experimentalneon and v7
Reversing vector elements (swap endianness)
vrev32_s8Experimentalneon and v7
Reversing vector elements (swap endianness)
vrev32_s16Experimentalneon and v7
Reversing vector elements (swap endianness)
vrev32_u8Experimentalneon and v7
Reversing vector elements (swap endianness)
vrev32_u16Experimentalneon and v7
Reversing vector elements (swap endianness)
vrev32q_p8Experimentalneon and v7
Reversing vector elements (swap endianness)
vrev32q_p16Experimentalneon and v7
Reversing vector elements (swap endianness)
vrev32q_s8Experimentalneon and v7
Reversing vector elements (swap endianness)
vrev32q_s16Experimentalneon and v7
Reversing vector elements (swap endianness)
vrev32q_u8Experimentalneon and v7
Reversing vector elements (swap endianness)
vrev32q_u16Experimentalneon and v7
Reversing vector elements (swap endianness)
vrev64_f32Experimentalneon and v7
Reversing vector elements (swap endianness)
vrev64_p8Experimentalneon and v7
Reversing vector elements (swap endianness)
vrev64_p16Experimentalneon and v7
Reversing vector elements (swap endianness)
vrev64_s8Experimentalneon and v7
Reversing vector elements (swap endianness)
vrev64_s16Experimentalneon and v7
Reversing vector elements (swap endianness)
vrev64_s32Experimentalneon and v7
Reversing vector elements (swap endianness)
vrev64_u8Experimentalneon and v7
Reversing vector elements (swap endianness)
vrev64_u16Experimentalneon and v7
Reversing vector elements (swap endianness)
vrev64_u32Experimentalneon and v7
Reversing vector elements (swap endianness)
vrev64q_f32Experimentalneon and v7
Reversing vector elements (swap endianness)
vrev64q_p8Experimentalneon and v7
Reversing vector elements (swap endianness)
vrev64q_p16Experimentalneon and v7
Reversing vector elements (swap endianness)
vrev64q_s8Experimentalneon and v7
Reversing vector elements (swap endianness)
vrev64q_s16Experimentalneon and v7
Reversing vector elements (swap endianness)
vrev64q_s32Experimentalneon and v7
Reversing vector elements (swap endianness)
vrev64q_u8Experimentalneon and v7
Reversing vector elements (swap endianness)
vrev64q_u16Experimentalneon and v7
Reversing vector elements (swap endianness)
vrev64q_u32Experimentalneon and v7
Reversing vector elements (swap endianness)
vrhadd_s8Experimentalneon and v7
Rounding halving add
vrhadd_s16Experimentalneon and v7
Rounding halving add
vrhadd_s32Experimentalneon and v7
Rounding halving add
vrhadd_u8Experimentalneon and v7
Rounding halving add
vrhadd_u16Experimentalneon and v7
Rounding halving add
vrhadd_u32Experimentalneon and v7
Rounding halving add
vrhaddq_s8Experimentalneon and v7
Rounding halving add
vrhaddq_s16Experimentalneon and v7
Rounding halving add
vrhaddq_s32Experimentalneon and v7
Rounding halving add
vrhaddq_u8Experimentalneon and v7
Rounding halving add
vrhaddq_u16Experimentalneon and v7
Rounding halving add
vrhaddq_u32Experimentalneon and v7
Rounding halving add
vrnd32x_f32Experimentalneon,frintts
Floating-point round to 32-bit integer, using current rounding mode
vrnd32x_f64Experimentalneon,frintts
Floating-point round to 32-bit integer, using current rounding mode
vrnd32xq_f32Experimentalneon,frintts
Floating-point round to 32-bit integer, using current rounding mode
vrnd32xq_f64Experimentalneon,frintts
Floating-point round to 32-bit integer, using current rounding mode
vrnd32z_f32Experimentalneon,frintts
Floating-point round to 32-bit integer toward zero
vrnd32z_f64Experimentalneon,frintts
Floating-point round to 32-bit integer toward zero
vrnd32zq_f32Experimentalneon,frintts
Floating-point round to 32-bit integer toward zero
vrnd32zq_f64Experimentalneon,frintts
Floating-point round to 32-bit integer toward zero
vrnd64x_f32Experimentalneon,frintts
Floating-point round to 64-bit integer, using current rounding mode
vrnd64x_f64Experimentalneon,frintts
Floating-point round to 64-bit integer, using current rounding mode
vrnd64xq_f32Experimentalneon,frintts
Floating-point round to 64-bit integer, using current rounding mode
vrnd64xq_f64Experimentalneon,frintts
Floating-point round to 64-bit integer, using current rounding mode
vrnd64z_f32Experimentalneon,frintts
Floating-point round to 64-bit integer toward zero
vrnd64z_f64Experimentalneon,frintts
Floating-point round to 64-bit integer toward zero
vrnd64zq_f32Experimentalneon,frintts
Floating-point round to 64-bit integer toward zero
vrnd64zq_f64Experimentalneon,frintts
Floating-point round to 64-bit integer toward zero
vrndn_f32Experimentalneon and fp-armv8,v8
Floating-point round to integral, to nearest with ties to even
vrndnq_f32Experimentalneon and fp-armv8,v8
Floating-point round to integral, to nearest with ties to even
vrshl_s8Experimentalneon and v7
Signed rounding shift left
vrshl_s16Experimentalneon and v7
Signed rounding shift left
vrshl_s32Experimentalneon and v7
Signed rounding shift left
vrshl_s64Experimentalneon and v7
Signed rounding shift left
vrshl_u8Experimentalneon and v7
Unsigned rounding shift left
vrshl_u16Experimentalneon and v7
Unsigned rounding shift left
vrshl_u32Experimentalneon and v7
Unsigned rounding shift left
vrshl_u64Experimentalneon and v7
Unsigned rounding shift left
vrshlq_s8Experimentalneon and v7
Signed rounding shift left
vrshlq_s16Experimentalneon and v7
Signed rounding shift left
vrshlq_s32Experimentalneon and v7
Signed rounding shift left
vrshlq_s64Experimentalneon and v7
Signed rounding shift left
vrshlq_u8Experimentalneon and v7
Unsigned rounding shift left
vrshlq_u16Experimentalneon and v7
Unsigned rounding shift left
vrshlq_u32Experimentalneon and v7
Unsigned rounding shift left
vrshlq_u64Experimentalneon and v7
Unsigned rounding shift left
vrshr_n_s8Experimentalneon and v7
Signed rounding shift right
vrshr_n_s16Experimentalneon and v7
Signed rounding shift right
vrshr_n_s32Experimentalneon and v7
Signed rounding shift right
vrshr_n_s64Experimentalneon and v7
Signed rounding shift right
vrshr_n_u8Experimentalneon and v7
Unsigned rounding shift right
vrshr_n_u16Experimentalneon and v7
Unsigned rounding shift right
vrshr_n_u32Experimentalneon and v7
Unsigned rounding shift right
vrshr_n_u64Experimentalneon and v7
Unsigned rounding shift right
vrshrn_n_s16Experimentalneon,v7
Rounding shift right narrow
vrshrn_n_s32Experimentalneon,v7
Rounding shift right narrow
vrshrn_n_s64Experimentalneon,v7
Rounding shift right narrow
vrshrn_n_u16Experimentalneon and v7
Rounding shift right narrow
vrshrn_n_u32Experimentalneon and v7
Rounding shift right narrow
vrshrn_n_u64Experimentalneon and v7
Rounding shift right narrow
vrshrq_n_s8Experimentalneon and v7
Signed rounding shift right
vrshrq_n_s16Experimentalneon and v7
Signed rounding shift right
vrshrq_n_s32Experimentalneon and v7
Signed rounding shift right
vrshrq_n_s64Experimentalneon and v7
Signed rounding shift right
vrshrq_n_u8Experimentalneon and v7
Unsigned rounding shift right
vrshrq_n_u16Experimentalneon and v7
Unsigned rounding shift right
vrshrq_n_u32Experimentalneon and v7
Unsigned rounding shift right
vrshrq_n_u64Experimentalneon and v7
Unsigned rounding shift right
vrsqrte_f32Experimentalneon and v7
Reciprocal square-root estimate.
vrsqrte_u32Experimentalneon and v7
Unsigned reciprocal square root estimate
vrsqrteq_f32Experimentalneon and v7
Reciprocal square-root estimate.
vrsqrteq_u32Experimentalneon and v7
Unsigned reciprocal square root estimate
vrsqrts_f32Experimentalneon and v7
Floating-point reciprocal square root step
vrsqrtsq_f32Experimentalneon and v7
Floating-point reciprocal square root step
vrsra_n_s8Experimentalneon and v7
Signed rounding shift right and accumulate
vrsra_n_s16Experimentalneon and v7
Signed rounding shift right and accumulate
vrsra_n_s32Experimentalneon and v7
Signed rounding shift right and accumulate
vrsra_n_s64Experimentalneon and v7
Signed rounding shift right and accumulate
vrsra_n_u8Experimentalneon and v7
Unsigned rounding shift right and accumulate
vrsra_n_u16Experimentalneon and v7
Unsigned rounding shift right and accumulate
vrsra_n_u32Experimentalneon and v7
Unsigned rounding shift right and accumulate
vrsra_n_u64Experimentalneon and v7
Unsigned rounding shift right and accumulate
vrsraq_n_s8Experimentalneon and v7
Signed rounding shift right and accumulate
vrsraq_n_s16Experimentalneon and v7
Signed rounding shift right and accumulate
vrsraq_n_s32Experimentalneon and v7
Signed rounding shift right and accumulate
vrsraq_n_s64Experimentalneon and v7
Signed rounding shift right and accumulate
vrsraq_n_u8Experimentalneon and v7
Unsigned rounding shift right and accumulate
vrsraq_n_u16Experimentalneon and v7
Unsigned rounding shift right and accumulate
vrsraq_n_u32Experimentalneon and v7
Unsigned rounding shift right and accumulate
vrsraq_n_u64Experimentalneon and v7
Unsigned rounding shift right and accumulate
vrsubhn_s16Experimentalneon and v7
Rounding subtract returning high narrow
vrsubhn_s32Experimentalneon and v7
Rounding subtract returning high narrow
vrsubhn_s64Experimentalneon and v7
Rounding subtract returning high narrow
vrsubhn_u16Experimentalneon and v7
Rounding subtract returning high narrow
vrsubhn_u32Experimentalneon and v7
Rounding subtract returning high narrow
vrsubhn_u64Experimentalneon and v7
Rounding subtract returning high narrow
vset_lane_f32Experimentalneon and v7
Insert vector element from another vector element
vset_lane_p8Experimentalneon and v7
Insert vector element from another vector element
vset_lane_p16Experimentalneon and v7
Insert vector element from another vector element
vset_lane_p64Experimentalneon,aes and v8
Insert vector element from another vector element
vset_lane_s8Experimentalneon and v7
Insert vector element from another vector element
vset_lane_s16Experimentalneon and v7
Insert vector element from another vector element
vset_lane_s32Experimentalneon and v7
Insert vector element from another vector element
vset_lane_s64Experimentalneon and v7
Insert vector element from another vector element
vset_lane_u8Experimentalneon and v7
Insert vector element from another vector element
vset_lane_u16Experimentalneon and v7
Insert vector element from another vector element
vset_lane_u32Experimentalneon and v7
Insert vector element from another vector element
vset_lane_u64Experimentalneon and v7
Insert vector element from another vector element
vsetq_lane_f32Experimentalneon and v7
Insert vector element from another vector element
vsetq_lane_p8Experimentalneon and v7
Insert vector element from another vector element
vsetq_lane_p16Experimentalneon and v7
Insert vector element from another vector element
vsetq_lane_p64Experimentalneon,aes and v8
Insert vector element from another vector element
vsetq_lane_s8Experimentalneon and v7
Insert vector element from another vector element
vsetq_lane_s16Experimentalneon and v7
Insert vector element from another vector element
vsetq_lane_s32Experimentalneon and v7
Insert vector element from another vector element
vsetq_lane_s64Experimentalneon and v7
Insert vector element from another vector element
vsetq_lane_u8Experimentalneon and v7
Insert vector element from another vector element
vsetq_lane_u16Experimentalneon and v7
Insert vector element from another vector element
vsetq_lane_u32Experimentalneon and v7
Insert vector element from another vector element
vsetq_lane_u64Experimentalneon and v7
Insert vector element from another vector element
vsha1cq_u32Experimentalsha2 and v8
SHA1 hash update accelerator, choose.
vsha1h_u32Experimentalsha2 and v8
SHA1 fixed rotate.
vsha1mq_u32Experimentalsha2 and v8
SHA1 hash update accelerator, majority.
vsha1pq_u32Experimentalsha2 and v8
SHA1 hash update accelerator, parity.
vsha1su0q_u32Experimentalsha2 and v8
SHA1 schedule update accelerator, first part.
vsha1su1q_u32Experimentalsha2 and v8
SHA1 schedule update accelerator, second part.
vsha256h2q_u32Experimentalsha2 and v8
SHA256 hash update accelerator, upper part.
vsha256hq_u32Experimentalsha2 and v8
SHA256 hash update accelerator.
vsha256su0q_u32Experimentalsha2 and v8
SHA256 schedule update accelerator, first part.
vsha256su1q_u32Experimentalsha2 and v8
SHA256 schedule update accelerator, second part.
vshl_n_s8Experimentalneon and v7
Shift left
vshl_n_s16Experimentalneon and v7
Shift left
vshl_n_s32Experimentalneon and v7
Shift left
vshl_n_s64Experimentalneon and v7
Shift left
vshl_n_u8Experimentalneon and v7
Shift left
vshl_n_u16Experimentalneon and v7
Shift left
vshl_n_u32Experimentalneon and v7
Shift left
vshl_n_u64Experimentalneon and v7
Shift left
vshl_s8Experimentalneon and v7
Signed Shift left
vshl_s16Experimentalneon and v7
Signed Shift left
vshl_s32Experimentalneon and v7
Signed Shift left
vshl_s64Experimentalneon and v7
Signed Shift left
vshl_u8Experimentalneon and v7
Unsigned Shift left
vshl_u16Experimentalneon and v7
Unsigned Shift left
vshl_u32Experimentalneon and v7
Unsigned Shift left
vshl_u64Experimentalneon and v7
Unsigned Shift left
vshll_n_s8Experimentalneon and v7
Signed shift left long
vshll_n_s16Experimentalneon and v7
Signed shift left long
vshll_n_s32Experimentalneon and v7
Signed shift left long
vshll_n_u8Experimentalneon and v7
Signed shift left long
vshll_n_u16Experimentalneon and v7
Signed shift left long
vshll_n_u32Experimentalneon and v7
Signed shift left long
vshlq_n_s8Experimentalneon and v7
Shift left
vshlq_n_s16Experimentalneon and v7
Shift left
vshlq_n_s32Experimentalneon and v7
Shift left
vshlq_n_s64Experimentalneon and v7
Shift left
vshlq_n_u8Experimentalneon and v7
Shift left
vshlq_n_u16Experimentalneon and v7
Shift left
vshlq_n_u32Experimentalneon and v7
Shift left
vshlq_n_u64Experimentalneon and v7
Shift left
vshlq_s8Experimentalneon and v7
Signed Shift left
vshlq_s16Experimentalneon and v7
Signed Shift left
vshlq_s32Experimentalneon and v7
Signed Shift left
vshlq_s64Experimentalneon and v7
Signed Shift left
vshlq_u8Experimentalneon and v7
Unsigned Shift left
vshlq_u16Experimentalneon and v7
Unsigned Shift left
vshlq_u32Experimentalneon and v7
Unsigned Shift left
vshlq_u64Experimentalneon and v7
Unsigned Shift left
vshr_n_s8Experimentalneon and v7
Shift right
vshr_n_s16Experimentalneon and v7
Shift right
vshr_n_s32Experimentalneon and v7
Shift right
vshr_n_s64Experimentalneon and v7
Shift right
vshr_n_u8Experimentalneon and v7
Shift right
vshr_n_u16Experimentalneon and v7
Shift right
vshr_n_u32Experimentalneon and v7
Shift right
vshr_n_u64Experimentalneon and v7
Shift right
vshrn_n_s16Experimentalneon and v7
Shift right narrow
vshrn_n_s32Experimentalneon and v7
Shift right narrow
vshrn_n_s64Experimentalneon and v7
Shift right narrow
vshrn_n_u16Experimentalneon and v7
Shift right narrow
vshrn_n_u32Experimentalneon and v7
Shift right narrow
vshrn_n_u64Experimentalneon and v7
Shift right narrow
vshrq_n_s8Experimentalneon and v7
Shift right
vshrq_n_s16Experimentalneon and v7
Shift right
vshrq_n_s32Experimentalneon and v7
Shift right
vshrq_n_s64Experimentalneon and v7
Shift right
vshrq_n_u8Experimentalneon and v7
Shift right
vshrq_n_u16Experimentalneon and v7
Shift right
vshrq_n_u32Experimentalneon and v7
Shift right
vshrq_n_u64Experimentalneon and v7
Shift right
vsm3partw1q_u32Experimentalneon,sm4
SM3PARTW1
vsm3partw2q_u32Experimentalneon,sm4
SM3PARTW2
vsm3ss1q_u32Experimentalneon,sm4
SM3SS1
vsm3tt1aq_u32Experimentalneon,sm4
SM3TT1A
vsm3tt1bq_u32Experimentalneon,sm4
SM3TT1B
vsm3tt2aq_u32Experimentalneon,sm4
SM3TT2A
vsm3tt2bq_u32Experimentalneon,sm4
SM3TT2B
vsm4ekeyq_u32Experimentalneon,sm4
SM4 key
vsm4eq_u32Experimentalneon,sm4
SM4 encode
vsra_n_s8Experimentalneon and v7
Signed shift right and accumulate
vsra_n_s16Experimentalneon and v7
Signed shift right and accumulate
vsra_n_s32Experimentalneon and v7
Signed shift right and accumulate
vsra_n_s64Experimentalneon and v7
Signed shift right and accumulate
vsra_n_u8Experimentalneon and v7
Unsigned shift right and accumulate
vsra_n_u16Experimentalneon and v7
Unsigned shift right and accumulate
vsra_n_u32Experimentalneon and v7
Unsigned shift right and accumulate
vsra_n_u64Experimentalneon and v7
Unsigned shift right and accumulate
vsraq_n_s8Experimentalneon and v7
Signed shift right and accumulate
vsraq_n_s16Experimentalneon and v7
Signed shift right and accumulate
vsraq_n_s32Experimentalneon and v7
Signed shift right and accumulate
vsraq_n_s64Experimentalneon and v7
Signed shift right and accumulate
vsraq_n_u8Experimentalneon and v7
Unsigned shift right and accumulate
vsraq_n_u16Experimentalneon and v7
Unsigned shift right and accumulate
vsraq_n_u32Experimentalneon and v7
Unsigned shift right and accumulate
vsraq_n_u64Experimentalneon and v7
Unsigned shift right and accumulate
vst1_f32_x2Experimentalneon,v7
Store multiple single-element structures to one, two, three, or four registers
vst1_f32_x3Experimentalneon,v7
Store multiple single-element structures to one, two, three, or four registers
vst1_f32_x4Experimentalneon,v7
Store multiple single-element structures to one, two, three, or four registers
vst1_lane_f32Experimentalneon and v7
Store multiple single-element structures from one, two, three, or four registers
vst1_lane_p8Experimentalneon and v7
Store multiple single-element structures from one, two, three, or four registers
vst1_lane_p16Experimentalneon and v7
Store multiple single-element structures from one, two, three, or four registers
vst1_lane_p64Experimentalneon,aes and v8
Store multiple single-element structures from one, two, three, or four registers
vst1_lane_s8Experimentalneon and v7
Store multiple single-element structures from one, two, three, or four registers
vst1_lane_s16Experimentalneon and v7
Store multiple single-element structures from one, two, three, or four registers
vst1_lane_s32Experimentalneon and v7
Store multiple single-element structures from one, two, three, or four registers
vst1_lane_s64Experimentalneon and v7
Store multiple single-element structures from one, two, three, or four registers
vst1_lane_u8Experimentalneon and v7
Store multiple single-element structures from one, two, three, or four registers
vst1_lane_u16Experimentalneon and v7
Store multiple single-element structures from one, two, three, or four registers
vst1_lane_u32Experimentalneon and v7
Store multiple single-element structures from one, two, three, or four registers
vst1_lane_u64Experimentalneon and v7
Store multiple single-element structures from one, two, three, or four registers
vst1_p8_x2Experimentalneon and v7
Store multiple single-element structures to one, two, three, or four registers
vst1_p8_x3Experimentalneon and v7
Store multiple single-element structures to one, two, three, or four registers
vst1_p8_x4Experimentalneon and v7
Store multiple single-element structures to one, two, three, or four registers
vst1_p16_x2Experimentalneon and v7
Store multiple single-element structures to one, two, three, or four registers
vst1_p16_x3Experimentalneon and v7
Store multiple single-element structures to one, two, three, or four registers
vst1_p16_x4Experimentalneon and v7
Store multiple single-element structures to one, two, three, or four registers
vst1_p64_x2Experimentalneon,aes and v8
Store multiple single-element structures to one, two, three, or four registers
vst1_p64_x3Experimentalneon,aes and v8
Store multiple single-element structures to one, two, three, or four registers
vst1_p64_x4Experimentalneon,aes and v8
Store multiple single-element structures to one, two, three, or four registers
vst1_s8_x2Experimentalneon,v7
Store multiple single-element structures from one, two, three, or four registers
vst1_s8_x3Experimentalneon,v7
Store multiple single-element structures from one, two, three, or four registers
vst1_s8_x4Experimentalneon,v7
Store multiple single-element structures from one, two, three, or four registers
vst1_s16_x2Experimentalneon,v7
Store multiple single-element structures from one, two, three, or four registers
vst1_s16_x3Experimentalneon,v7
Store multiple single-element structures from one, two, three, or four registers
vst1_s16_x4Experimentalneon,v7
Store multiple single-element structures from one, two, three, or four registers
vst1_s32_x2Experimentalneon,v7
Store multiple single-element structures from one, two, three, or four registers
vst1_s32_x3Experimentalneon,v7
Store multiple single-element structures from one, two, three, or four registers
vst1_s32_x4Experimentalneon,v7
Store multiple single-element structures from one, two, three, or four registers
vst1_s64_x2Experimentalneon,v7
Store multiple single-element structures from one, two, three, or four registers
vst1_s64_x3Experimentalneon,v7
Store multiple single-element structures from one, two, three, or four registers
vst1_s64_x4Experimentalneon,v7
Store multiple single-element structures from one, two, three, or four registers
vst1_u8_x2Experimentalneon and v7
Store multiple single-element structures to one, two, three, or four registers
vst1_u8_x3Experimentalneon and v7
Store multiple single-element structures to one, two, three, or four registers
vst1_u8_x4Experimentalneon and v7
Store multiple single-element structures to one, two, three, or four registers
vst1_u16_x2Experimentalneon and v7
Store multiple single-element structures to one, two, three, or four registers
vst1_u16_x3Experimentalneon and v7
Store multiple single-element structures to one, two, three, or four registers
vst1_u16_x4Experimentalneon and v7
Store multiple single-element structures to one, two, three, or four registers
vst1_u32_x2Experimentalneon and v7
Store multiple single-element structures to one, two, three, or four registers
vst1_u32_x3Experimentalneon and v7
Store multiple single-element structures to one, two, three, or four registers
vst1_u32_x4Experimentalneon and v7
Store multiple single-element structures to one, two, three, or four registers
vst1_u64_x2Experimentalneon and v7
Store multiple single-element structures to one, two, three, or four registers
vst1_u64_x3Experimentalneon and v7
Store multiple single-element structures to one, two, three, or four registers
vst1_u64_x4Experimentalneon and v7
Store multiple single-element structures to one, two, three, or four registers
vst1q_f32_x2Experimentalneon,v7
Store multiple single-element structures to one, two, three, or four registers
vst1q_f32_x3Experimentalneon,v7
Store multiple single-element structures to one, two, three, or four registers
vst1q_f32_x4Experimentalneon,v7
Store multiple single-element structures to one, two, three, or four registers
vst1q_lane_f32Experimentalneon and v7
Store multiple single-element structures from one, two, three, or four registers
vst1q_lane_p8Experimentalneon and v7
Store multiple single-element structures from one, two, three, or four registers
vst1q_lane_p16Experimentalneon and v7
Store multiple single-element structures from one, two, three, or four registers
vst1q_lane_p64Experimentalneon,aes and v8
Store multiple single-element structures from one, two, three, or four registers
vst1q_lane_s8Experimentalneon and v7
Store multiple single-element structures from one, two, three, or four registers
vst1q_lane_s16Experimentalneon and v7
Store multiple single-element structures from one, two, three, or four registers
vst1q_lane_s32Experimentalneon and v7
Store multiple single-element structures from one, two, three, or four registers
vst1q_lane_s64Experimentalneon and v7
Store multiple single-element structures from one, two, three, or four registers
vst1q_lane_u8Experimentalneon and v7
Store multiple single-element structures from one, two, three, or four registers
vst1q_lane_u16Experimentalneon and v7
Store multiple single-element structures from one, two, three, or four registers
vst1q_lane_u32Experimentalneon and v7
Store multiple single-element structures from one, two, three, or four registers
vst1q_lane_u64Experimentalneon and v7
Store multiple single-element structures from one, two, three, or four registers
vst1q_p8_x2Experimentalneon and v7
Store multiple single-element structures to one, two, three, or four registers
vst1q_p8_x3Experimentalneon and v7
Store multiple single-element structures to one, two, three, or four registers
vst1q_p8_x4Experimentalneon and v7
Store multiple single-element structures to one, two, three, or four registers
vst1q_p16_x2Experimentalneon and v7
Store multiple single-element structures to one, two, three, or four registers
vst1q_p16_x3Experimentalneon and v7
Store multiple single-element structures to one, two, three, or four registers
vst1q_p16_x4Experimentalneon and v7
Store multiple single-element structures to one, two, three, or four registers
vst1q_p64_x2Experimentalneon,aes and v8
Store multiple single-element structures to one, two, three, or four registers
vst1q_p64_x3Experimentalneon,aes and v8
Store multiple single-element structures to one, two, three, or four registers
vst1q_p64_x4Experimentalneon,aes and v8
Store multiple single-element structures to one, two, three, or four registers
vst1q_s8_x2Experimentalneon,v7
Store multiple single-element structures from one, two, three, or four registers
vst1q_s8_x3Experimentalneon,v7
Store multiple single-element structures from one, two, three, or four registers
vst1q_s8_x4Experimentalneon,v7
Store multiple single-element structures from one, two, three, or four registers
vst1q_s16_x2Experimentalneon,v7
Store multiple single-element structures from one, two, three, or four registers
vst1q_s16_x3Experimentalneon,v7
Store multiple single-element structures from one, two, three, or four registers
vst1q_s16_x4Experimentalneon,v7
Store multiple single-element structures from one, two, three, or four registers
vst1q_s32_x2Experimentalneon,v7
Store multiple single-element structures from one, two, three, or four registers
vst1q_s32_x3Experimentalneon,v7
Store multiple single-element structures from one, two, three, or four registers
vst1q_s32_x4Experimentalneon,v7
Store multiple single-element structures from one, two, three, or four registers
vst1q_s64_x2Experimentalneon,v7
Store multiple single-element structures from one, two, three, or four registers
vst1q_s64_x3Experimentalneon,v7
Store multiple single-element structures from one, two, three, or four registers
vst1q_s64_x4Experimentalneon,v7
Store multiple single-element structures from one, two, three, or four registers
vst1q_u8_x2Experimentalneon and v7
Store multiple single-element structures to one, two, three, or four registers
vst1q_u8_x3Experimentalneon and v7
Store multiple single-element structures to one, two, three, or four registers
vst1q_u8_x4Experimentalneon and v7
Store multiple single-element structures to one, two, three, or four registers
vst1q_u16_x2Experimentalneon and v7
Store multiple single-element structures to one, two, three, or four registers
vst1q_u16_x3Experimentalneon and v7
Store multiple single-element structures to one, two, three, or four registers
vst1q_u16_x4Experimentalneon and v7
Store multiple single-element structures to one, two, three, or four registers
vst1q_u32_x2Experimentalneon and v7
Store multiple single-element structures to one, two, three, or four registers
vst1q_u32_x3Experimentalneon and v7
Store multiple single-element structures to one, two, three, or four registers
vst1q_u32_x4Experimentalneon and v7
Store multiple single-element structures to one, two, three, or four registers
vst1q_u64_x2Experimentalneon and v7
Store multiple single-element structures to one, two, three, or four registers
vst1q_u64_x3Experimentalneon and v7
Store multiple single-element structures to one, two, three, or four registers
vst1q_u64_x4Experimentalneon and v7
Store multiple single-element structures to one, two, three, or four registers
vst2_f32Experimentalneon,v7
Store multiple 2-element structures from two registers
vst2_lane_f32Experimentalneon,v7
Store multiple 2-element structures from two registers
vst2_lane_p8Experimentalneon and v7
Store multiple 2-element structures from two registers
vst2_lane_p16Experimentalneon and v7
Store multiple 2-element structures from two registers
vst2_lane_s8Experimentalneon,v7
Store multiple 2-element structures from two registers
vst2_lane_s16Experimentalneon,v7
Store multiple 2-element structures from two registers
vst2_lane_s32Experimentalneon,v7
Store multiple 2-element structures from two registers
vst2_lane_u8Experimentalneon and v7
Store multiple 2-element structures from two registers
vst2_lane_u16Experimentalneon and v7
Store multiple 2-element structures from two registers
vst2_lane_u32Experimentalneon and v7
Store multiple 2-element structures from two registers
vst2_p8Experimentalneon and v7
Store multiple 2-element structures from two registers
vst2_p16Experimentalneon and v7
Store multiple 2-element structures from two registers
vst2_p64Experimentalneon,aes and v8
Store multiple 2-element structures from two registers
vst2_s8Experimentalneon,v7
Store multiple 2-element structures from two registers
vst2_s16Experimentalneon,v7
Store multiple 2-element structures from two registers
vst2_s32Experimentalneon,v7
Store multiple 2-element structures from two registers
vst2_s64Experimentalneon,v7
Store multiple 2-element structures from two registers
vst2_u8Experimentalneon and v7
Store multiple 2-element structures from two registers
vst2_u16Experimentalneon and v7
Store multiple 2-element structures from two registers
vst2_u32Experimentalneon and v7
Store multiple 2-element structures from two registers
vst2_u64Experimentalneon and v7
Store multiple 2-element structures from two registers
vst2q_f32Experimentalneon,v7
Store multiple 2-element structures from two registers
vst2q_lane_f32Experimentalneon,v7
Store multiple 2-element structures from two registers
vst2q_lane_p16Experimentalneon and v7
Store multiple 2-element structures from two registers
vst2q_lane_s16Experimentalneon,v7
Store multiple 2-element structures from two registers
vst2q_lane_s32Experimentalneon,v7
Store multiple 2-element structures from two registers
vst2q_lane_u16Experimentalneon and v7
Store multiple 2-element structures from two registers
vst2q_lane_u32Experimentalneon and v7
Store multiple 2-element structures from two registers
vst2q_p8Experimentalneon and v7
Store multiple 2-element structures from two registers
vst2q_p16Experimentalneon and v7
Store multiple 2-element structures from two registers
vst2q_s8Experimentalneon,v7
Store multiple 2-element structures from two registers
vst2q_s16Experimentalneon,v7
Store multiple 2-element structures from two registers
vst2q_s32Experimentalneon,v7
Store multiple 2-element structures from two registers
vst2q_u8Experimentalneon and v7
Store multiple 2-element structures from two registers
vst2q_u16Experimentalneon and v7
Store multiple 2-element structures from two registers
vst2q_u32Experimentalneon and v7
Store multiple 2-element structures from two registers
vst3_f32Experimentalneon,v7
Store multiple 3-element structures from three registers
vst3_lane_f32Experimentalneon,v7
Store multiple 3-element structures from three registers
vst3_lane_p8Experimentalneon and v7
Store multiple 3-element structures from three registers
vst3_lane_p16Experimentalneon and v7
Store multiple 3-element structures from three registers
vst3_lane_s8Experimentalneon,v7
Store multiple 3-element structures from three registers
vst3_lane_s16Experimentalneon,v7
Store multiple 3-element structures from three registers
vst3_lane_s32Experimentalneon,v7
Store multiple 3-element structures from three registers
vst3_lane_u8Experimentalneon and v7
Store multiple 3-element structures from three registers
vst3_lane_u16Experimentalneon and v7
Store multiple 3-element structures from three registers
vst3_lane_u32Experimentalneon and v7
Store multiple 3-element structures from three registers
vst3_p8Experimentalneon and v7
Store multiple 3-element structures from three registers
vst3_p16Experimentalneon and v7
Store multiple 3-element structures from three registers
vst3_p64Experimentalneon,aes and v8
Store multiple 3-element structures from three registers
vst3_s8Experimentalneon,v7
Store multiple 3-element structures from three registers
vst3_s16Experimentalneon,v7
Store multiple 3-element structures from three registers
vst3_s32Experimentalneon,v7
Store multiple 3-element structures from three registers
vst3_s64Experimentalneon,v7
Store multiple 3-element structures from three registers
vst3_u8Experimentalneon and v7
Store multiple 3-element structures from three registers
vst3_u16Experimentalneon and v7
Store multiple 3-element structures from three registers
vst3_u32Experimentalneon and v7
Store multiple 3-element structures from three registers
vst3_u64Experimentalneon and v7
Store multiple 3-element structures from three registers
vst3q_f32Experimentalneon,v7
Store multiple 3-element structures from three registers
vst3q_lane_f32Experimentalneon,v7
Store multiple 3-element structures from three registers
vst3q_lane_p16Experimentalneon and v7
Store multiple 3-element structures from three registers
vst3q_lane_s16Experimentalneon,v7
Store multiple 3-element structures from three registers
vst3q_lane_s32Experimentalneon,v7
Store multiple 3-element structures from three registers
vst3q_lane_u16Experimentalneon and v7
Store multiple 3-element structures from three registers
vst3q_lane_u32Experimentalneon and v7
Store multiple 3-element structures from three registers
vst3q_p8Experimentalneon and v7
Store multiple 3-element structures from three registers
vst3q_p16Experimentalneon and v7
Store multiple 3-element structures from three registers
vst3q_s8Experimentalneon,v7
Store multiple 3-element structures from three registers
vst3q_s16Experimentalneon,v7
Store multiple 3-element structures from three registers
vst3q_s32Experimentalneon,v7
Store multiple 3-element structures from three registers
vst3q_u8Experimentalneon and v7
Store multiple 3-element structures from three registers
vst3q_u16Experimentalneon and v7
Store multiple 3-element structures from three registers
vst3q_u32Experimentalneon and v7
Store multiple 3-element structures from three registers
vst4_f32Experimentalneon,v7
Store multiple 4-element structures from four registers
vst4_lane_f32Experimentalneon,v7
Store multiple 4-element structures from four registers
vst4_lane_p8Experimentalneon and v7
Store multiple 4-element structures from four registers
vst4_lane_p16Experimentalneon and v7
Store multiple 4-element structures from four registers
vst4_lane_s8Experimentalneon,v7
Store multiple 4-element structures from four registers
vst4_lane_s16Experimentalneon,v7
Store multiple 4-element structures from four registers
vst4_lane_s32Experimentalneon,v7
Store multiple 4-element structures from four registers
vst4_lane_u8Experimentalneon and v7
Store multiple 4-element structures from four registers
vst4_lane_u16Experimentalneon and v7
Store multiple 4-element structures from four registers
vst4_lane_u32Experimentalneon and v7
Store multiple 4-element structures from four registers
vst4_p8Experimentalneon and v7
Store multiple 4-element structures from four registers
vst4_p16Experimentalneon and v7
Store multiple 4-element structures from four registers
vst4_p64Experimentalneon,aes and v8
Store multiple 4-element structures from four registers
vst4_s8Experimentalneon,v7
Store multiple 4-element structures from four registers
vst4_s16Experimentalneon,v7
Store multiple 4-element structures from four registers
vst4_s32Experimentalneon,v7
Store multiple 4-element structures from four registers
vst4_s64Experimentalneon,v7
Store multiple 4-element structures from four registers
vst4_u8Experimentalneon and v7
Store multiple 4-element structures from four registers
vst4_u16Experimentalneon and v7
Store multiple 4-element structures from four registers
vst4_u32Experimentalneon and v7
Store multiple 4-element structures from four registers
vst4_u64Experimentalneon and v7
Store multiple 4-element structures from four registers
vst4q_f32Experimentalneon,v7
Store multiple 4-element structures from four registers
vst4q_lane_f32Experimentalneon,v7
Store multiple 4-element structures from four registers
vst4q_lane_p16Experimentalneon and v7
Store multiple 4-element structures from four registers
vst4q_lane_s16Experimentalneon,v7
Store multiple 4-element structures from four registers
vst4q_lane_s32Experimentalneon,v7
Store multiple 4-element structures from four registers
vst4q_lane_u16Experimentalneon and v7
Store multiple 4-element structures from four registers
vst4q_lane_u32Experimentalneon and v7
Store multiple 4-element structures from four registers
vst4q_p8Experimentalneon and v7
Store multiple 4-element structures from four registers
vst4q_p16Experimentalneon and v7
Store multiple 4-element structures from four registers
vst4q_s8Experimentalneon,v7
Store multiple 4-element structures from four registers
vst4q_s16Experimentalneon,v7
Store multiple 4-element structures from four registers
vst4q_s32Experimentalneon,v7
Store multiple 4-element structures from four registers
vst4q_u8Experimentalneon and v7
Store multiple 4-element structures from four registers
vst4q_u16Experimentalneon and v7
Store multiple 4-element structures from four registers
vst4q_u32Experimentalneon and v7
Store multiple 4-element structures from four registers
vstrq_p128Experimentalneon and v7
Store SIMD&FP register (immediate offset)
vsub_f32Experimentalneon and v7
Subtract
vsub_s8Experimentalneon and v7
Subtract
vsub_s16Experimentalneon and v7
Subtract
vsub_s32Experimentalneon and v7
Subtract
vsub_s64Experimentalneon and v7
Subtract
vsub_u8Experimentalneon and v7
Subtract
vsub_u16Experimentalneon and v7
Subtract
vsub_u32Experimentalneon and v7
Subtract
vsub_u64Experimentalneon and v7
Subtract
vsubhn_high_s16Experimentalneon and v7
Subtract returning high narrow
vsubhn_high_s32Experimentalneon and v7
Subtract returning high narrow
vsubhn_high_s64Experimentalneon and v7
Subtract returning high narrow
vsubhn_high_u16Experimentalneon and v7
Subtract returning high narrow
vsubhn_high_u32Experimentalneon and v7
Subtract returning high narrow
vsubhn_high_u64Experimentalneon and v7
Subtract returning high narrow
vsubhn_s16Experimentalneon and v7
Subtract returning high narrow
vsubhn_s32Experimentalneon and v7
Subtract returning high narrow
vsubhn_s64Experimentalneon and v7
Subtract returning high narrow
vsubhn_u16Experimentalneon and v7
Subtract returning high narrow
vsubhn_u32Experimentalneon and v7
Subtract returning high narrow
vsubhn_u64Experimentalneon and v7
Subtract returning high narrow
vsubl_s8Experimentalneon and v7
Signed Subtract Long
vsubl_s16Experimentalneon and v7
Signed Subtract Long
vsubl_s32Experimentalneon and v7
Signed Subtract Long
vsubl_u8Experimentalneon and v7
Unsigned Subtract Long
vsubl_u16Experimentalneon and v7
Unsigned Subtract Long
vsubl_u32Experimentalneon and v7
Unsigned Subtract Long
vsubq_f32Experimentalneon and v7
Subtract
vsubq_s8Experimentalneon and v7
Subtract
vsubq_s16Experimentalneon and v7
Subtract
vsubq_s32Experimentalneon and v7
Subtract
vsubq_s64Experimentalneon and v7
Subtract
vsubq_u8Experimentalneon and v7
Subtract
vsubq_u16Experimentalneon and v7
Subtract
vsubq_u32Experimentalneon and v7
Subtract
vsubq_u64Experimentalneon and v7
Subtract
vsubw_s8Experimentalneon and v7
Signed Subtract Wide
vsubw_s16Experimentalneon and v7
Signed Subtract Wide
vsubw_s32Experimentalneon and v7
Signed Subtract Wide
vsubw_u8Experimentalneon and v7
Unsigned Subtract Wide
vsubw_u16Experimentalneon and v7
Unsigned Subtract Wide
vsubw_u32Experimentalneon and v7
Unsigned Subtract Wide
vsudot_lane_s32Experimentalneon,i8mm and v8
Dot product index form with signed and unsigned integers
vsudot_laneq_s32Experimentalneon,i8mm
Dot product index form with signed and unsigned integers
vsudotq_lane_s32Experimentalneon,i8mm and v8
Dot product index form with signed and unsigned integers
vsudotq_laneq_s32Experimentalneon,i8mm
Dot product index form with signed and unsigned integers
vtrn_f32Experimentalneon and v7
Transpose elements
vtrn_p8Experimentalneon and v7
Transpose elements
vtrn_p16Experimentalneon and v7
Transpose elements
vtrn_s8Experimentalneon and v7
Transpose elements
vtrn_s16Experimentalneon and v7
Transpose elements
vtrn_s32Experimentalneon and v7
Transpose elements
vtrn_u8Experimentalneon and v7
Transpose elements
vtrn_u16Experimentalneon and v7
Transpose elements
vtrn_u32Experimentalneon and v7
Transpose elements
vtrnq_f32Experimentalneon and v7
Transpose elements
vtrnq_p8Experimentalneon and v7
Transpose elements
vtrnq_p16Experimentalneon and v7
Transpose elements
vtrnq_s8Experimentalneon and v7
Transpose elements
vtrnq_s16Experimentalneon and v7
Transpose elements
vtrnq_s32Experimentalneon and v7
Transpose elements
vtrnq_u8Experimentalneon and v7
Transpose elements
vtrnq_u16Experimentalneon and v7
Transpose elements
vtrnq_u32Experimentalneon and v7
Transpose elements
vtst_p8Experimentalneon and v7
Signed compare bitwise Test bits nonzero
vtst_p16Experimentalneon and v7
Signed compare bitwise Test bits nonzero
vtst_s8Experimentalneon and v7
Signed compare bitwise Test bits nonzero
vtst_s16Experimentalneon and v7
Signed compare bitwise Test bits nonzero
vtst_s32Experimentalneon and v7
Signed compare bitwise Test bits nonzero
vtst_u8Experimentalneon and v7
Unsigned compare bitwise Test bits nonzero
vtst_u16Experimentalneon and v7
Unsigned compare bitwise Test bits nonzero
vtst_u32Experimentalneon and v7
Unsigned compare bitwise Test bits nonzero
vtstq_p8Experimentalneon and v7
Signed compare bitwise Test bits nonzero
vtstq_p16Experimentalneon and v7
Signed compare bitwise Test bits nonzero
vtstq_s8Experimentalneon and v7
Signed compare bitwise Test bits nonzero
vtstq_s16Experimentalneon and v7
Signed compare bitwise Test bits nonzero
vtstq_s32Experimentalneon and v7
Signed compare bitwise Test bits nonzero
vtstq_u8Experimentalneon and v7
Unsigned compare bitwise Test bits nonzero
vtstq_u16Experimentalneon and v7
Unsigned compare bitwise Test bits nonzero
vtstq_u32Experimentalneon and v7
Unsigned compare bitwise Test bits nonzero
vusdot_lane_s32Experimentalneon,i8mm and v8
Dot product index form with unsigned and signed integers
vusdot_laneq_s32Experimentalneon,i8mm
Dot product index form with unsigned and signed integers
vusdot_s32Experimentalneon,i8mm and v8
Dot product vector form with unsigned and signed integers
vusdotq_lane_s32Experimentalneon,i8mm and v8
Dot product index form with unsigned and signed integers
vusdotq_laneq_s32Experimentalneon,i8mm
Dot product index form with unsigned and signed integers
vusdotq_s32Experimentalneon,i8mm and v8
Dot product vector form with unsigned and signed integers
vusmmlaq_s32Experimentalneon,i8mm and v8
Unsigned and signed 8-bit integer matrix multiply-accumulate
vuzp_f32Experimentalneon and v7
Unzip vectors
vuzp_p8Experimentalneon and v7
Unzip vectors
vuzp_p16Experimentalneon and v7
Unzip vectors
vuzp_s8Experimentalneon and v7
Unzip vectors
vuzp_s16Experimentalneon and v7
Unzip vectors
vuzp_s32Experimentalneon and v7
Unzip vectors
vuzp_u8Experimentalneon and v7
Unzip vectors
vuzp_u16Experimentalneon and v7
Unzip vectors
vuzp_u32Experimentalneon and v7
Unzip vectors
vuzpq_f32Experimentalneon and v7
Unzip vectors
vuzpq_p8Experimentalneon and v7
Unzip vectors
vuzpq_p16Experimentalneon and v7
Unzip vectors
vuzpq_s8Experimentalneon and v7
Unzip vectors
vuzpq_s16Experimentalneon and v7
Unzip vectors
vuzpq_s32Experimentalneon and v7
Unzip vectors
vuzpq_u8Experimentalneon and v7
Unzip vectors
vuzpq_u16Experimentalneon and v7
Unzip vectors
vuzpq_u32Experimentalneon and v7
Unzip vectors
vzip_f32Experimentalneon and v7
Zip vectors
vzip_p8Experimentalneon and v7
Zip vectors
vzip_p16Experimentalneon and v7
Zip vectors
vzip_s8Experimentalneon and v7
Zip vectors
vzip_s16Experimentalneon and v7
Zip vectors
vzip_s32Experimentalneon and v7
Zip vectors
vzip_u8Experimentalneon and v7
Zip vectors
vzip_u16Experimentalneon and v7
Zip vectors
vzip_u32Experimentalneon and v7
Zip vectors
vzipq_f32Experimentalneon and v7
Zip vectors
vzipq_p8Experimentalneon and v7
Zip vectors
vzipq_p16Experimentalneon and v7
Zip vectors
vzipq_s8Experimentalneon and v7
Zip vectors
vzipq_s16Experimentalneon and v7
Zip vectors
vzipq_s32Experimentalneon and v7
Zip vectors
vzipq_u8Experimentalneon and v7
Zip vectors
vzipq_u16Experimentalneon and v7
Zip vectors
vzipq_u32Experimentalneon and v7
Zip vectors