core/stdarch/crates/core_arch/src/x86_64/
avx512f.rs

1use crate::{
2    core_arch::{simd::*, x86::*, x86_64::*},
3    mem::transmute,
4};
5
6#[cfg(test)]
7use stdarch_test::assert_instr;
8
9/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer, and store the result in dst.
10///
11/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsd_i64&expand=1792)
12#[inline]
13#[target_feature(enable = "avx512f")]
14#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
15#[cfg_attr(test, assert_instr(vcvtsd2si))]
16pub unsafe fn _mm_cvtsd_i64(a: __m128d) -> i64 {
17    _mm_cvtsd_si64(a)
18}
19
20/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer, and store the result in dst.
21///
22/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtss_i64&expand=1894)
23#[inline]
24#[target_feature(enable = "avx512f")]
25#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
26#[cfg_attr(test, assert_instr(vcvtss2si))]
27pub unsafe fn _mm_cvtss_i64(a: __m128) -> i64 {
28    _mm_cvtss_si64(a)
29}
30
31/// Convert the lower single-precision (32-bit) floating-point element in a to an unsigned 64-bit integer, and store the result in dst.
32///
33/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtss_u64&expand=1902)
34#[inline]
35#[target_feature(enable = "avx512f")]
36#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
37#[cfg_attr(test, assert_instr(vcvtss2usi))]
38pub unsafe fn _mm_cvtss_u64(a: __m128) -> u64 {
39    vcvtss2usi64(a.as_f32x4(), _MM_FROUND_CUR_DIRECTION)
40}
41
42/// Convert the lower double-precision (64-bit) floating-point element in a to an unsigned 64-bit integer, and store the result in dst.
43///
44/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsd_u64&expand=1800)
45#[inline]
46#[target_feature(enable = "avx512f")]
47#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
48#[cfg_attr(test, assert_instr(vcvtsd2usi))]
49pub unsafe fn _mm_cvtsd_u64(a: __m128d) -> u64 {
50    vcvtsd2usi64(a.as_f64x2(), _MM_FROUND_CUR_DIRECTION)
51}
52
53/// Convert the signed 64-bit integer b to a single-precision (32-bit) floating-point element, store the result in the lower element of dst, and copy the upper 3 packed elements from a to the upper elements of dst.
54///
55/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_cvti64_ss&expand=1643)
56#[inline]
57#[target_feature(enable = "avx512f")]
58#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
59#[cfg_attr(test, assert_instr(vcvtsi2ss))]
60pub unsafe fn _mm_cvti64_ss(a: __m128, b: i64) -> __m128 {
61    let b = b as f32;
62    simd_insert!(a, 0, b)
63}
64
65/// Convert the signed 64-bit integer b to a double-precision (64-bit) floating-point element, store the result in the lower element of dst, and copy the upper element from a to the upper element of dst.
66///
67/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvti64_sd&expand=1644)
68#[inline]
69#[target_feature(enable = "avx512f")]
70#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
71#[cfg_attr(test, assert_instr(vcvtsi2sd))]
72pub unsafe fn _mm_cvti64_sd(a: __m128d, b: i64) -> __m128d {
73    let b = b as f64;
74    simd_insert!(a, 0, b)
75}
76
77/// Convert the unsigned 64-bit integer b to a single-precision (32-bit) floating-point element, store the result in the lower element of dst, and copy the upper 3 packed elements from a to the upper elements of dst.
78///
79/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtu64_ss&expand=2035)
80#[inline]
81#[target_feature(enable = "avx512f")]
82#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
83#[cfg_attr(test, assert_instr(vcvtusi2ss))]
84pub unsafe fn _mm_cvtu64_ss(a: __m128, b: u64) -> __m128 {
85    let b = b as f32;
86    simd_insert!(a, 0, b)
87}
88
89/// Convert the unsigned 64-bit integer b to a double-precision (64-bit) floating-point element, store the result in the lower element of dst, and copy the upper element from a to the upper element of dst.
90///
91/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtu64_sd&expand=2034)
92#[inline]
93#[target_feature(enable = "avx512f")]
94#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
95#[cfg_attr(test, assert_instr(vcvtusi2sd))]
96pub unsafe fn _mm_cvtu64_sd(a: __m128d, b: u64) -> __m128d {
97    let b = b as f64;
98    simd_insert!(a, 0, b)
99}
100
101/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.
102///
103/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvttsd_i64&expand=2016)
104#[inline]
105#[target_feature(enable = "avx512f")]
106#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
107#[cfg_attr(test, assert_instr(vcvttsd2si))]
108pub unsafe fn _mm_cvttsd_i64(a: __m128d) -> i64 {
109    vcvttsd2si64(a.as_f64x2(), _MM_FROUND_CUR_DIRECTION)
110}
111
112/// Convert the lower double-precision (64-bit) floating-point element in a to an unsigned 64-bit integer with truncation, and store the result in dst.
113///
114/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvttsd_u64&expand=2021)
115#[inline]
116#[target_feature(enable = "avx512f")]
117#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
118#[cfg_attr(test, assert_instr(vcvttsd2usi))]
119pub unsafe fn _mm_cvttsd_u64(a: __m128d) -> u64 {
120    vcvttsd2usi64(a.as_f64x2(), _MM_FROUND_CUR_DIRECTION)
121}
122
123/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.
124///
125/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=#text=_mm_cvttss_i64&expand=2023)
126#[inline]
127#[target_feature(enable = "avx512f")]
128#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
129#[cfg_attr(test, assert_instr(vcvttss2si))]
130pub unsafe fn _mm_cvttss_i64(a: __m128) -> i64 {
131    vcvttss2si64(a.as_f32x4(), _MM_FROUND_CUR_DIRECTION)
132}
133
134/// Convert the lower single-precision (32-bit) floating-point element in a to an unsigned 64-bit integer with truncation, and store the result in dst.
135///
136/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvttss_u64&expand=2027)
137#[inline]
138#[target_feature(enable = "avx512f")]
139#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
140#[cfg_attr(test, assert_instr(vcvttss2usi))]
141pub unsafe fn _mm_cvttss_u64(a: __m128) -> u64 {
142    vcvttss2usi64(a.as_f32x4(), _MM_FROUND_CUR_DIRECTION)
143}
144
145/// Convert the signed 64-bit integer b to a double-precision (64-bit) floating-point element, store the result in the lower element of dst, and copy the upper element from a to the upper element of dst.
146/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
147/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
148/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
149/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
150/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
151/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
152///
153/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundi64_sd&expand=1313)
154#[inline]
155#[target_feature(enable = "avx512f")]
156#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
157#[cfg_attr(test, assert_instr(vcvtsi2sd, ROUNDING = 8))]
158#[rustc_legacy_const_generics(2)]
159pub unsafe fn _mm_cvt_roundi64_sd<const ROUNDING: i32>(a: __m128d, b: i64) -> __m128d {
160    static_assert_rounding!(ROUNDING);
161    let a = a.as_f64x2();
162    let r = vcvtsi2sd64(a, b, ROUNDING);
163    transmute(r)
164}
165
166/// Convert the signed 64-bit integer b to a double-precision (64-bit) floating-point element, store the result in the lower element of dst, and copy the upper element from a to the upper element of dst.
167/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
168/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
169/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
170/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
171/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
172/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
173///
174/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundsi64_sd&expand=1367)
175#[inline]
176#[target_feature(enable = "avx512f")]
177#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
178#[cfg_attr(test, assert_instr(vcvtsi2sd, ROUNDING = 8))]
179#[rustc_legacy_const_generics(2)]
180pub unsafe fn _mm_cvt_roundsi64_sd<const ROUNDING: i32>(a: __m128d, b: i64) -> __m128d {
181    static_assert_rounding!(ROUNDING);
182    let a = a.as_f64x2();
183    let r = vcvtsi2sd64(a, b, ROUNDING);
184    transmute(r)
185}
186
187/// Convert the signed 64-bit integer b to a single-precision (32-bit) floating-point element, store the result in the lower element of dst, and copy the upper 3 packed elements from a to the upper elements of dst.
188/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
189/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
190/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
191/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
192/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
193/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
194///
195/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundi64_ss&expand=1314)
196#[inline]
197#[target_feature(enable = "avx512f")]
198#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
199#[cfg_attr(test, assert_instr(vcvtsi2ss, ROUNDING = 8))]
200#[rustc_legacy_const_generics(2)]
201pub unsafe fn _mm_cvt_roundi64_ss<const ROUNDING: i32>(a: __m128, b: i64) -> __m128 {
202    static_assert_rounding!(ROUNDING);
203    let a = a.as_f32x4();
204    let r = vcvtsi2ss64(a, b, ROUNDING);
205    transmute(r)
206}
207
208/// Convert the unsigned 64-bit integer b to a double-precision (64-bit) floating-point element, store the result in the lower element of dst, and copy the upper element from a to the upper element of dst.\
209/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
210/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
211/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
212/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
213/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
214/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
215///
216/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundu64_sd&expand=1379)
217#[inline]
218#[target_feature(enable = "avx512f")]
219#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
220#[cfg_attr(test, assert_instr(vcvtusi2sd, ROUNDING = 8))]
221#[rustc_legacy_const_generics(2)]
222pub unsafe fn _mm_cvt_roundu64_sd<const ROUNDING: i32>(a: __m128d, b: u64) -> __m128d {
223    static_assert_rounding!(ROUNDING);
224    let a = a.as_f64x2();
225    let r = vcvtusi2sd64(a, b, ROUNDING);
226    transmute(r)
227}
228
229/// Convert the signed 64-bit integer b to a single-precision (32-bit) floating-point element, store the result in the lower element of dst, and copy the upper 3 packed elements from a to the upper elements of dst.
230/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
231/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
232/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
233/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
234/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
235/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
236///
237/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundsi64_ss&expand=1368)
238#[inline]
239#[target_feature(enable = "avx512f")]
240#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
241#[cfg_attr(test, assert_instr(vcvtsi2ss, ROUNDING = 8))]
242#[rustc_legacy_const_generics(2)]
243pub unsafe fn _mm_cvt_roundsi64_ss<const ROUNDING: i32>(a: __m128, b: i64) -> __m128 {
244    static_assert_rounding!(ROUNDING);
245    let a = a.as_f32x4();
246    let r = vcvtsi2ss64(a, b, ROUNDING);
247    transmute(r)
248}
249
250/// Convert the unsigned 64-bit integer b to a single-precision (32-bit) floating-point element, store the result in the lower element of dst, and copy the upper 3 packed elements from a to the upper elements of dst.\
251/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
252/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
253/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
254/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
255/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
256/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
257///
258/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundu64_ss&expand=1380)
259#[inline]
260#[target_feature(enable = "avx512f")]
261#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
262#[cfg_attr(test, assert_instr(vcvtusi2ss, ROUNDING = 8))]
263#[rustc_legacy_const_generics(2)]
264pub unsafe fn _mm_cvt_roundu64_ss<const ROUNDING: i32>(a: __m128, b: u64) -> __m128 {
265    static_assert_rounding!(ROUNDING);
266    let a = a.as_f32x4();
267    let r = vcvtusi2ss64(a, b, ROUNDING);
268    transmute(r)
269}
270
271/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer, and store the result in dst.\
272/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
273/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
274/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
275/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
276/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
277/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
278///
279/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundsd_si64&expand=1360)
280#[inline]
281#[target_feature(enable = "avx512f")]
282#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
283#[cfg_attr(test, assert_instr(vcvtsd2si, ROUNDING = 8))]
284#[rustc_legacy_const_generics(1)]
285pub unsafe fn _mm_cvt_roundsd_si64<const ROUNDING: i32>(a: __m128d) -> i64 {
286    static_assert_rounding!(ROUNDING);
287    let a = a.as_f64x2();
288    vcvtsd2si64(a, ROUNDING)
289}
290
291/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer, and store the result in dst.\
292/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
293/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
294/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
295/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
296/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
297/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
298///
299/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundsd_i64&expand=1358)
300#[inline]
301#[target_feature(enable = "avx512f")]
302#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
303#[cfg_attr(test, assert_instr(vcvtsd2si, ROUNDING = 8))]
304#[rustc_legacy_const_generics(1)]
305pub unsafe fn _mm_cvt_roundsd_i64<const ROUNDING: i32>(a: __m128d) -> i64 {
306    static_assert_rounding!(ROUNDING);
307    let a = a.as_f64x2();
308    vcvtsd2si64(a, ROUNDING)
309}
310
311/// Convert the lower double-precision (64-bit) floating-point element in a to an unsigned 64-bit integer, and store the result in dst.\
312/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
313/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
314/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
315/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
316/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
317/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
318///
319/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundsd_u64&expand=1365)
320#[inline]
321#[target_feature(enable = "avx512f")]
322#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
323#[cfg_attr(test, assert_instr(vcvtsd2usi, ROUNDING = 8))]
324#[rustc_legacy_const_generics(1)]
325pub unsafe fn _mm_cvt_roundsd_u64<const ROUNDING: i32>(a: __m128d) -> u64 {
326    static_assert_rounding!(ROUNDING);
327    let a = a.as_f64x2();
328    vcvtsd2usi64(a, ROUNDING)
329}
330
331/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer, and store the result in dst.\
332/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
333/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
334/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
335/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
336/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
337/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
338///
339/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundss_si64&expand=1375)
340#[inline]
341#[target_feature(enable = "avx512f")]
342#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
343#[cfg_attr(test, assert_instr(vcvtss2si, ROUNDING = 8))]
344#[rustc_legacy_const_generics(1)]
345pub unsafe fn _mm_cvt_roundss_si64<const ROUNDING: i32>(a: __m128) -> i64 {
346    static_assert_rounding!(ROUNDING);
347    let a = a.as_f32x4();
348    vcvtss2si64(a, ROUNDING)
349}
350
351/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer, and store the result in dst.\
352/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
353/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
354/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
355/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
356/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
357/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
358///
359/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundss_i64&expand=1370)
360#[inline]
361#[target_feature(enable = "avx512f")]
362#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
363#[cfg_attr(test, assert_instr(vcvtss2si, ROUNDING = 8))]
364#[rustc_legacy_const_generics(1)]
365pub unsafe fn _mm_cvt_roundss_i64<const ROUNDING: i32>(a: __m128) -> i64 {
366    static_assert_rounding!(ROUNDING);
367    let a = a.as_f32x4();
368    vcvtss2si64(a, ROUNDING)
369}
370
371/// Convert the lower single-precision (32-bit) floating-point element in a to an unsigned 64-bit integer, and store the result in dst.\
372/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
373/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
374/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
375/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
376/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
377/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
378///
379/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundss_u64&expand=1377)
380#[inline]
381#[target_feature(enable = "avx512f")]
382#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
383#[cfg_attr(test, assert_instr(vcvtss2usi, ROUNDING = 8))]
384#[rustc_legacy_const_generics(1)]
385pub unsafe fn _mm_cvt_roundss_u64<const ROUNDING: i32>(a: __m128) -> u64 {
386    static_assert_rounding!(ROUNDING);
387    let a = a.as_f32x4();
388    vcvtss2usi64(a, ROUNDING)
389}
390
391/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.\
392/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
393///
394/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundsd_si64&expand=1931)
395#[inline]
396#[target_feature(enable = "avx512f")]
397#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
398#[cfg_attr(test, assert_instr(vcvttsd2si, SAE = 8))]
399#[rustc_legacy_const_generics(1)]
400pub unsafe fn _mm_cvtt_roundsd_si64<const SAE: i32>(a: __m128d) -> i64 {
401    static_assert_sae!(SAE);
402    let a = a.as_f64x2();
403    vcvttsd2si64(a, SAE)
404}
405
406/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.\
407/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
408///
409/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundsd_i64&expand=1929)
410#[inline]
411#[target_feature(enable = "avx512f")]
412#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
413#[cfg_attr(test, assert_instr(vcvttsd2si, SAE = 8))]
414#[rustc_legacy_const_generics(1)]
415pub unsafe fn _mm_cvtt_roundsd_i64<const SAE: i32>(a: __m128d) -> i64 {
416    static_assert_sae!(SAE);
417    let a = a.as_f64x2();
418    vcvttsd2si64(a, SAE)
419}
420
421/// Convert the lower double-precision (64-bit) floating-point element in a to an unsigned 64-bit integer with truncation, and store the result in dst.\
422/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
423///
424/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundsd_u64&expand=1933)
425#[inline]
426#[target_feature(enable = "avx512f")]
427#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
428#[cfg_attr(test, assert_instr(vcvttsd2usi, SAE = 8))]
429#[rustc_legacy_const_generics(1)]
430pub unsafe fn _mm_cvtt_roundsd_u64<const SAE: i32>(a: __m128d) -> u64 {
431    static_assert_sae!(SAE);
432    let a = a.as_f64x2();
433    vcvttsd2usi64(a, SAE)
434}
435
436/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.\
437/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
438///
439/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundss_i64&expand=1935)
440#[inline]
441#[target_feature(enable = "avx512f")]
442#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
443#[cfg_attr(test, assert_instr(vcvttss2si, SAE = 8))]
444#[rustc_legacy_const_generics(1)]
445pub unsafe fn _mm_cvtt_roundss_i64<const SAE: i32>(a: __m128) -> i64 {
446    static_assert_sae!(SAE);
447    let a = a.as_f32x4();
448    vcvttss2si64(a, SAE)
449}
450
451/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.\
452/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
453///
454/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundss_si64&expand=1937)
455#[inline]
456#[target_feature(enable = "avx512f")]
457#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
458#[cfg_attr(test, assert_instr(vcvttss2si, SAE = 8))]
459#[rustc_legacy_const_generics(1)]
460pub unsafe fn _mm_cvtt_roundss_si64<const SAE: i32>(a: __m128) -> i64 {
461    static_assert_sae!(SAE);
462    let a = a.as_f32x4();
463    vcvttss2si64(a, SAE)
464}
465
466/// Convert the lower single-precision (32-bit) floating-point element in a to an unsigned 64-bit integer with truncation, and store the result in dst.\
467/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
468///
469/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundss_u64&expand=1939)
470#[inline]
471#[target_feature(enable = "avx512f")]
472#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
473#[cfg_attr(test, assert_instr(vcvttss2usi, SAE = 8))]
474#[rustc_legacy_const_generics(1)]
475pub unsafe fn _mm_cvtt_roundss_u64<const SAE: i32>(a: __m128) -> u64 {
476    static_assert_sae!(SAE);
477    let a = a.as_f32x4();
478    vcvttss2usi64(a, SAE)
479}
480
481#[allow(improper_ctypes)]
482extern "C" {
483    #[link_name = "llvm.x86.avx512.vcvtss2si64"]
484    fn vcvtss2si64(a: f32x4, rounding: i32) -> i64;
485    #[link_name = "llvm.x86.avx512.vcvtss2usi64"]
486    fn vcvtss2usi64(a: f32x4, rounding: i32) -> u64;
487    #[link_name = "llvm.x86.avx512.vcvtsd2si64"]
488    fn vcvtsd2si64(a: f64x2, rounding: i32) -> i64;
489    #[link_name = "llvm.x86.avx512.vcvtsd2usi64"]
490    fn vcvtsd2usi64(a: f64x2, rounding: i32) -> u64;
491
492    #[link_name = "llvm.x86.avx512.cvtsi2ss64"]
493    fn vcvtsi2ss64(a: f32x4, b: i64, rounding: i32) -> f32x4;
494    #[link_name = "llvm.x86.avx512.cvtsi2sd64"]
495    fn vcvtsi2sd64(a: f64x2, b: i64, rounding: i32) -> f64x2;
496    #[link_name = "llvm.x86.avx512.cvtusi642ss"]
497    fn vcvtusi2ss64(a: f32x4, b: u64, rounding: i32) -> f32x4;
498    #[link_name = "llvm.x86.avx512.cvtusi642sd"]
499    fn vcvtusi2sd64(a: f64x2, b: u64, rounding: i32) -> f64x2;
500
501    #[link_name = "llvm.x86.avx512.cvttss2si64"]
502    fn vcvttss2si64(a: f32x4, rounding: i32) -> i64;
503    #[link_name = "llvm.x86.avx512.cvttss2usi64"]
504    fn vcvttss2usi64(a: f32x4, rounding: i32) -> u64;
505    #[link_name = "llvm.x86.avx512.cvttsd2si64"]
506    fn vcvttsd2si64(a: f64x2, rounding: i32) -> i64;
507    #[link_name = "llvm.x86.avx512.cvttsd2usi64"]
508    fn vcvttsd2usi64(a: f64x2, rounding: i32) -> u64;
509}
510
511#[cfg(test)]
512mod tests {
513
514    use stdarch_test::simd_test;
515
516    use crate::core_arch::x86::*;
517    use crate::core_arch::x86_64::*;
518    use crate::hint::black_box;
519
520    #[simd_test(enable = "avx512f")]
521    unsafe fn test_mm512_abs_epi64() {
522        let a = _mm512_set_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
523        let r = _mm512_abs_epi64(a);
524        let e = _mm512_set_epi64(0, 1, 1, i64::MAX, i64::MAX.wrapping_add(1), 100, 100, 32);
525        assert_eq_m512i(r, e);
526    }
527
528    #[simd_test(enable = "avx512f")]
529    unsafe fn test_mm512_mask_abs_epi64() {
530        let a = _mm512_set_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
531        let r = _mm512_mask_abs_epi64(a, 0, a);
532        assert_eq_m512i(r, a);
533        let r = _mm512_mask_abs_epi64(a, 0b11111111, a);
534        let e = _mm512_set_epi64(0, 1, 1, i64::MAX, i64::MIN, 100, 100, 32);
535        assert_eq_m512i(r, e);
536    }
537
538    #[simd_test(enable = "avx512f")]
539    unsafe fn test_mm512_maskz_abs_epi64() {
540        let a = _mm512_set_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
541        let r = _mm512_maskz_abs_epi64(0, a);
542        assert_eq_m512i(r, _mm512_setzero_si512());
543        let r = _mm512_maskz_abs_epi64(0b11111111, a);
544        let e = _mm512_set_epi64(0, 1, 1, i64::MAX, i64::MIN, 100, 100, 32);
545        assert_eq_m512i(r, e);
546    }
547
548    #[simd_test(enable = "avx512f,avx512vl")]
549    unsafe fn test_mm256_abs_epi64() {
550        let a = _mm256_set_epi64x(i64::MAX, i64::MIN, 100, -100);
551        let r = _mm256_abs_epi64(a);
552        let e = _mm256_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1), 100, 100);
553        assert_eq_m256i(r, e);
554    }
555
556    #[simd_test(enable = "avx512f,avx512vl")]
557    unsafe fn test_mm256_mask_abs_epi64() {
558        let a = _mm256_set_epi64x(i64::MAX, i64::MIN, 100, -100);
559        let r = _mm256_mask_abs_epi64(a, 0, a);
560        assert_eq_m256i(r, a);
561        let r = _mm256_mask_abs_epi64(a, 0b00001111, a);
562        let e = _mm256_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1), 100, 100);
563        assert_eq_m256i(r, e);
564    }
565
566    #[simd_test(enable = "avx512f,avx512vl")]
567    unsafe fn test_mm256_maskz_abs_epi64() {
568        let a = _mm256_set_epi64x(i64::MAX, i64::MIN, 100, -100);
569        let r = _mm256_maskz_abs_epi64(0, a);
570        assert_eq_m256i(r, _mm256_setzero_si256());
571        let r = _mm256_maskz_abs_epi64(0b00001111, a);
572        let e = _mm256_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1), 100, 100);
573        assert_eq_m256i(r, e);
574    }
575
576    #[simd_test(enable = "avx512f,avx512vl")]
577    unsafe fn test_mm_abs_epi64() {
578        let a = _mm_set_epi64x(i64::MAX, i64::MIN);
579        let r = _mm_abs_epi64(a);
580        let e = _mm_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1));
581        assert_eq_m128i(r, e);
582        let a = _mm_set_epi64x(100, -100);
583        let r = _mm_abs_epi64(a);
584        let e = _mm_set_epi64x(100, 100);
585        assert_eq_m128i(r, e);
586    }
587
588    #[simd_test(enable = "avx512f,avx512vl")]
589    unsafe fn test_mm_mask_abs_epi64() {
590        let a = _mm_set_epi64x(i64::MAX, i64::MIN);
591        let r = _mm_mask_abs_epi64(a, 0, a);
592        assert_eq_m128i(r, a);
593        let r = _mm_mask_abs_epi64(a, 0b00000011, a);
594        let e = _mm_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1));
595        assert_eq_m128i(r, e);
596        let a = _mm_set_epi64x(100, -100);
597        let r = _mm_mask_abs_epi64(a, 0b00000011, a);
598        let e = _mm_set_epi64x(100, 100);
599        assert_eq_m128i(r, e);
600    }
601
602    #[simd_test(enable = "avx512f,avx512vl")]
603    unsafe fn test_mm_maskz_abs_epi64() {
604        let a = _mm_set_epi64x(i64::MAX, i64::MIN);
605        let r = _mm_maskz_abs_epi64(0, a);
606        assert_eq_m128i(r, _mm_setzero_si128());
607        let r = _mm_maskz_abs_epi64(0b00000011, a);
608        let e = _mm_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1));
609        assert_eq_m128i(r, e);
610        let a = _mm_set_epi64x(100, -100);
611        let r = _mm_maskz_abs_epi64(0b00000011, a);
612        let e = _mm_set_epi64x(100, 100);
613        assert_eq_m128i(r, e);
614    }
615
616    #[simd_test(enable = "avx512f")]
617    unsafe fn test_mm512_abs_pd() {
618        let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
619        let r = _mm512_abs_pd(a);
620        let e = _mm512_setr_pd(0., 1., 1., f64::MAX, f64::MAX, 100., 100., 32.);
621        assert_eq_m512d(r, e);
622    }
623
624    #[simd_test(enable = "avx512f")]
625    unsafe fn test_mm512_mask_abs_pd() {
626        let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
627        let r = _mm512_mask_abs_pd(a, 0, a);
628        assert_eq_m512d(r, a);
629        let r = _mm512_mask_abs_pd(a, 0b00001111, a);
630        let e = _mm512_setr_pd(0., 1., 1., f64::MAX, f64::MIN, 100., -100., -32.);
631        assert_eq_m512d(r, e);
632    }
633
634    #[simd_test(enable = "avx512f")]
635    unsafe fn test_mm512_mask_mov_epi64() {
636        let src = _mm512_set1_epi64(1);
637        let a = _mm512_set1_epi64(2);
638        let r = _mm512_mask_mov_epi64(src, 0, a);
639        assert_eq_m512i(r, src);
640        let r = _mm512_mask_mov_epi64(src, 0b11111111, a);
641        assert_eq_m512i(r, a);
642    }
643
644    #[simd_test(enable = "avx512f")]
645    unsafe fn test_mm512_maskz_mov_epi64() {
646        let a = _mm512_set1_epi64(2);
647        let r = _mm512_maskz_mov_epi64(0, a);
648        assert_eq_m512i(r, _mm512_setzero_si512());
649        let r = _mm512_maskz_mov_epi64(0b11111111, a);
650        assert_eq_m512i(r, a);
651    }
652
653    #[simd_test(enable = "avx512f,avx512vl")]
654    unsafe fn test_mm256_mask_mov_epi64() {
655        let src = _mm256_set1_epi64x(1);
656        let a = _mm256_set1_epi64x(2);
657        let r = _mm256_mask_mov_epi64(src, 0, a);
658        assert_eq_m256i(r, src);
659        let r = _mm256_mask_mov_epi64(src, 0b00001111, a);
660        assert_eq_m256i(r, a);
661    }
662
663    #[simd_test(enable = "avx512f,avx512vl")]
664    unsafe fn test_mm256_maskz_mov_epi64() {
665        let a = _mm256_set1_epi64x(2);
666        let r = _mm256_maskz_mov_epi64(0, a);
667        assert_eq_m256i(r, _mm256_setzero_si256());
668        let r = _mm256_maskz_mov_epi64(0b00001111, a);
669        assert_eq_m256i(r, a);
670    }
671
672    #[simd_test(enable = "avx512f,avx512vl")]
673    unsafe fn test_mm_mask_mov_epi64() {
674        let src = _mm_set1_epi64x(1);
675        let a = _mm_set1_epi64x(2);
676        let r = _mm_mask_mov_epi64(src, 0, a);
677        assert_eq_m128i(r, src);
678        let r = _mm_mask_mov_epi64(src, 0b00000011, a);
679        assert_eq_m128i(r, a);
680    }
681
682    #[simd_test(enable = "avx512f,avx512vl")]
683    unsafe fn test_mm_maskz_mov_epi64() {
684        let a = _mm_set1_epi64x(2);
685        let r = _mm_maskz_mov_epi64(0, a);
686        assert_eq_m128i(r, _mm_setzero_si128());
687        let r = _mm_maskz_mov_epi64(0b00000011, a);
688        assert_eq_m128i(r, a);
689    }
690
691    #[simd_test(enable = "avx512f")]
692    unsafe fn test_mm512_mask_mov_pd() {
693        let src = _mm512_set1_pd(1.);
694        let a = _mm512_set1_pd(2.);
695        let r = _mm512_mask_mov_pd(src, 0, a);
696        assert_eq_m512d(r, src);
697        let r = _mm512_mask_mov_pd(src, 0b11111111, a);
698        assert_eq_m512d(r, a);
699    }
700
701    #[simd_test(enable = "avx512f")]
702    unsafe fn test_mm512_maskz_mov_pd() {
703        let a = _mm512_set1_pd(2.);
704        let r = _mm512_maskz_mov_pd(0, a);
705        assert_eq_m512d(r, _mm512_setzero_pd());
706        let r = _mm512_maskz_mov_pd(0b11111111, a);
707        assert_eq_m512d(r, a);
708    }
709
710    #[simd_test(enable = "avx512f,avx512vl")]
711    unsafe fn test_mm256_mask_mov_pd() {
712        let src = _mm256_set1_pd(1.);
713        let a = _mm256_set1_pd(2.);
714        let r = _mm256_mask_mov_pd(src, 0, a);
715        assert_eq_m256d(r, src);
716        let r = _mm256_mask_mov_pd(src, 0b00001111, a);
717        assert_eq_m256d(r, a);
718    }
719
720    #[simd_test(enable = "avx512f,avx512vl")]
721    unsafe fn test_mm256_maskz_mov_pd() {
722        let a = _mm256_set1_pd(2.);
723        let r = _mm256_maskz_mov_pd(0, a);
724        assert_eq_m256d(r, _mm256_setzero_pd());
725        let r = _mm256_maskz_mov_pd(0b00001111, a);
726        assert_eq_m256d(r, a);
727    }
728
729    #[simd_test(enable = "avx512f,avx512vl")]
730    unsafe fn test_mm_mask_mov_pd() {
731        let src = _mm_set1_pd(1.);
732        let a = _mm_set1_pd(2.);
733        let r = _mm_mask_mov_pd(src, 0, a);
734        assert_eq_m128d(r, src);
735        let r = _mm_mask_mov_pd(src, 0b00000011, a);
736        assert_eq_m128d(r, a);
737    }
738
739    #[simd_test(enable = "avx512f,avx512vl")]
740    unsafe fn test_mm_maskz_mov_pd() {
741        let a = _mm_set1_pd(2.);
742        let r = _mm_maskz_mov_pd(0, a);
743        assert_eq_m128d(r, _mm_setzero_pd());
744        let r = _mm_maskz_mov_pd(0b00000011, a);
745        assert_eq_m128d(r, a);
746    }
747
748    #[simd_test(enable = "avx512f")]
749    unsafe fn test_mm512_add_epi64() {
750        let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
751        let b = _mm512_set1_epi64(1);
752        let r = _mm512_add_epi64(a, b);
753        let e = _mm512_setr_epi64(1, 2, 0, i64::MIN, i64::MIN + 1, 101, -99, -31);
754        assert_eq_m512i(r, e);
755    }
756
757    #[simd_test(enable = "avx512f")]
758    unsafe fn test_mm512_mask_add_epi64() {
759        let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
760        let b = _mm512_set1_epi64(1);
761        let r = _mm512_mask_add_epi64(a, 0, a, b);
762        assert_eq_m512i(r, a);
763        let r = _mm512_mask_add_epi64(a, 0b00001111, a, b);
764        let e = _mm512_setr_epi64(1, 2, 0, i64::MIN, i64::MIN, 100, -100, -32);
765        assert_eq_m512i(r, e);
766    }
767
768    #[simd_test(enable = "avx512f")]
769    unsafe fn test_mm512_maskz_add_epi64() {
770        let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
771        let b = _mm512_set1_epi64(1);
772        let r = _mm512_maskz_add_epi64(0, a, b);
773        assert_eq_m512i(r, _mm512_setzero_si512());
774        let r = _mm512_maskz_add_epi64(0b00001111, a, b);
775        let e = _mm512_setr_epi64(1, 2, 0, i64::MIN, 0, 0, 0, 0);
776        assert_eq_m512i(r, e);
777    }
778
779    #[simd_test(enable = "avx512f,avx512vl")]
780    unsafe fn test_mm256_mask_add_epi64() {
781        let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
782        let b = _mm256_set1_epi64x(1);
783        let r = _mm256_mask_add_epi64(a, 0, a, b);
784        assert_eq_m256i(r, a);
785        let r = _mm256_mask_add_epi64(a, 0b00001111, a, b);
786        let e = _mm256_set_epi64x(2, 0, i64::MIN, i64::MIN + 1);
787        assert_eq_m256i(r, e);
788    }
789
790    #[simd_test(enable = "avx512f,avx512vl")]
791    unsafe fn test_mm256_maskz_add_epi64() {
792        let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
793        let b = _mm256_set1_epi64x(1);
794        let r = _mm256_maskz_add_epi64(0, a, b);
795        assert_eq_m256i(r, _mm256_setzero_si256());
796        let r = _mm256_maskz_add_epi64(0b00001111, a, b);
797        let e = _mm256_set_epi64x(2, 0, i64::MIN, i64::MIN + 1);
798        assert_eq_m256i(r, e);
799    }
800
801    #[simd_test(enable = "avx512f,avx512vl")]
802    unsafe fn test_mm_mask_add_epi64() {
803        let a = _mm_set_epi64x(i64::MAX, i64::MIN);
804        let b = _mm_set1_epi64x(1);
805        let r = _mm_mask_add_epi64(a, 0, a, b);
806        assert_eq_m128i(r, a);
807        let r = _mm_mask_add_epi64(a, 0b00000011, a, b);
808        let e = _mm_set_epi64x(i64::MIN, i64::MIN + 1);
809        assert_eq_m128i(r, e);
810    }
811
812    #[simd_test(enable = "avx512f,avx512vl")]
813    unsafe fn test_mm_maskz_add_epi64() {
814        let a = _mm_set_epi64x(i64::MAX, i64::MIN);
815        let b = _mm_set1_epi64x(1);
816        let r = _mm_maskz_add_epi64(0, a, b);
817        assert_eq_m128i(r, _mm_setzero_si128());
818        let r = _mm_maskz_add_epi64(0b00000011, a, b);
819        let e = _mm_set_epi64x(i64::MIN, i64::MIN + 1);
820        assert_eq_m128i(r, e);
821    }
822
823    #[simd_test(enable = "avx512f")]
824    unsafe fn test_mm512_add_pd() {
825        let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
826        let b = _mm512_set1_pd(1.);
827        let r = _mm512_add_pd(a, b);
828        let e = _mm512_setr_pd(1., 2., 0., f64::MAX, f64::MIN + 1., 101., -99., -31.);
829        assert_eq_m512d(r, e);
830    }
831
832    #[simd_test(enable = "avx512f")]
833    unsafe fn test_mm512_mask_add_pd() {
834        let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
835        let b = _mm512_set1_pd(1.);
836        let r = _mm512_mask_add_pd(a, 0, a, b);
837        assert_eq_m512d(r, a);
838        let r = _mm512_mask_add_pd(a, 0b00001111, a, b);
839        let e = _mm512_setr_pd(1., 2., 0., f64::MAX, f64::MIN, 100., -100., -32.);
840        assert_eq_m512d(r, e);
841    }
842
843    #[simd_test(enable = "avx512f")]
844    unsafe fn test_mm512_maskz_add_pd() {
845        let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
846        let b = _mm512_set1_pd(1.);
847        let r = _mm512_maskz_add_pd(0, a, b);
848        assert_eq_m512d(r, _mm512_setzero_pd());
849        let r = _mm512_maskz_add_pd(0b00001111, a, b);
850        let e = _mm512_setr_pd(1., 2., 0., f64::MAX, 0., 0., 0., 0.);
851        assert_eq_m512d(r, e);
852    }
853
854    #[simd_test(enable = "avx512f,avx512vl")]
855    unsafe fn test_mm256_mask_add_pd() {
856        let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
857        let b = _mm256_set1_pd(1.);
858        let r = _mm256_mask_add_pd(a, 0, a, b);
859        assert_eq_m256d(r, a);
860        let r = _mm256_mask_add_pd(a, 0b00001111, a, b);
861        let e = _mm256_set_pd(2., 0., f64::MAX, f64::MIN + 1.);
862        assert_eq_m256d(r, e);
863    }
864
865    #[simd_test(enable = "avx512f,avx512vl")]
866    unsafe fn test_mm256_maskz_add_pd() {
867        let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
868        let b = _mm256_set1_pd(1.);
869        let r = _mm256_maskz_add_pd(0, a, b);
870        assert_eq_m256d(r, _mm256_setzero_pd());
871        let r = _mm256_maskz_add_pd(0b00001111, a, b);
872        let e = _mm256_set_pd(2., 0., f64::MAX, f64::MIN + 1.);
873        assert_eq_m256d(r, e);
874    }
875
876    #[simd_test(enable = "avx512f,avx512vl")]
877    unsafe fn test_mm_mask_add_pd() {
878        let a = _mm_set_pd(f64::MAX, f64::MIN);
879        let b = _mm_set1_pd(1.);
880        let r = _mm_mask_add_pd(a, 0, a, b);
881        assert_eq_m128d(r, a);
882        let r = _mm_mask_add_pd(a, 0b00000011, a, b);
883        let e = _mm_set_pd(f64::MAX, f64::MIN + 1.);
884        assert_eq_m128d(r, e);
885    }
886
887    #[simd_test(enable = "avx512f,avx512vl")]
888    unsafe fn test_mm_maskz_add_pd() {
889        let a = _mm_set_pd(f64::MAX, f64::MIN);
890        let b = _mm_set1_pd(1.);
891        let r = _mm_maskz_add_pd(0, a, b);
892        assert_eq_m128d(r, _mm_setzero_pd());
893        let r = _mm_maskz_add_pd(0b00000011, a, b);
894        let e = _mm_set_pd(f64::MAX, f64::MIN + 1.);
895        assert_eq_m128d(r, e);
896    }
897
898    #[simd_test(enable = "avx512f")]
899    unsafe fn test_mm512_sub_epi64() {
900        let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
901        let b = _mm512_set1_epi64(1);
902        let r = _mm512_sub_epi64(a, b);
903        let e = _mm512_setr_epi64(-1, 0, -2, i64::MAX - 1, i64::MAX, 99, -101, -33);
904        assert_eq_m512i(r, e);
905    }
906
907    #[simd_test(enable = "avx512f")]
908    unsafe fn test_mm512_mask_sub_epi64() {
909        let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
910        let b = _mm512_set1_epi64(1);
911        let r = _mm512_mask_sub_epi64(a, 0, a, b);
912        assert_eq_m512i(r, a);
913        let r = _mm512_mask_sub_epi64(a, 0b00001111, a, b);
914        let e = _mm512_setr_epi64(-1, 0, -2, i64::MAX - 1, i64::MIN, 100, -100, -32);
915        assert_eq_m512i(r, e);
916    }
917
918    #[simd_test(enable = "avx512f")]
919    unsafe fn test_mm512_maskz_sub_epi64() {
920        let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
921        let b = _mm512_set1_epi64(1);
922        let r = _mm512_maskz_sub_epi64(0, a, b);
923        assert_eq_m512i(r, _mm512_setzero_si512());
924        let r = _mm512_maskz_sub_epi64(0b00001111, a, b);
925        let e = _mm512_setr_epi64(-1, 0, -2, i64::MAX - 1, 0, 0, 0, 0);
926        assert_eq_m512i(r, e);
927    }
928
929    #[simd_test(enable = "avx512f,avx512vl")]
930    unsafe fn test_mm256_mask_sub_epi64() {
931        let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
932        let b = _mm256_set1_epi64x(1);
933        let r = _mm256_mask_sub_epi64(a, 0, a, b);
934        assert_eq_m256i(r, a);
935        let r = _mm256_mask_sub_epi64(a, 0b00001111, a, b);
936        let e = _mm256_set_epi64x(0, -2, i64::MAX - 1, i64::MAX);
937        assert_eq_m256i(r, e);
938    }
939
940    #[simd_test(enable = "avx512f,avx512vl")]
941    unsafe fn test_mm256_maskz_sub_epi64() {
942        let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
943        let b = _mm256_set1_epi64x(1);
944        let r = _mm256_maskz_sub_epi64(0, a, b);
945        assert_eq_m256i(r, _mm256_setzero_si256());
946        let r = _mm256_maskz_sub_epi64(0b00001111, a, b);
947        let e = _mm256_set_epi64x(0, -2, i64::MAX - 1, i64::MAX);
948        assert_eq_m256i(r, e);
949    }
950
951    #[simd_test(enable = "avx512f,avx512vl")]
952    unsafe fn test_mm_mask_sub_epi64() {
953        let a = _mm_set_epi64x(i64::MAX, i64::MIN);
954        let b = _mm_set1_epi64x(1);
955        let r = _mm_mask_sub_epi64(a, 0, a, b);
956        assert_eq_m128i(r, a);
957        let r = _mm_mask_sub_epi64(a, 0b00000011, a, b);
958        let e = _mm_set_epi64x(i64::MAX - 1, i64::MAX);
959        assert_eq_m128i(r, e);
960    }
961
962    #[simd_test(enable = "avx512f,avx512vl")]
963    unsafe fn test_mm_maskz_sub_epi64() {
964        let a = _mm_set_epi64x(i64::MAX, i64::MIN);
965        let b = _mm_set1_epi64x(1);
966        let r = _mm_maskz_sub_epi64(0, a, b);
967        assert_eq_m128i(r, _mm_setzero_si128());
968        let r = _mm_maskz_sub_epi64(0b00000011, a, b);
969        let e = _mm_set_epi64x(i64::MAX - 1, i64::MAX);
970        assert_eq_m128i(r, e);
971    }
972
973    #[simd_test(enable = "avx512f")]
974    unsafe fn test_mm512_sub_pd() {
975        let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
976        let b = _mm512_set1_pd(1.);
977        let r = _mm512_sub_pd(a, b);
978        let e = _mm512_setr_pd(-1., 0., -2., f64::MAX - 1., f64::MIN, 99., -101., -33.);
979        assert_eq_m512d(r, e);
980    }
981
982    #[simd_test(enable = "avx512f")]
983    unsafe fn test_mm512_mask_sub_pd() {
984        let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
985        let b = _mm512_set1_pd(1.);
986        let r = _mm512_mask_sub_pd(a, 0, a, b);
987        assert_eq_m512d(r, a);
988        let r = _mm512_mask_sub_pd(a, 0b00001111, a, b);
989        let e = _mm512_setr_pd(-1., 0., -2., f64::MAX - 1., f64::MIN, 100., -100., -32.);
990        assert_eq_m512d(r, e);
991    }
992
993    #[simd_test(enable = "avx512f")]
994    unsafe fn test_mm512_maskz_sub_pd() {
995        let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
996        let b = _mm512_set1_pd(1.);
997        let r = _mm512_maskz_sub_pd(0, a, b);
998        assert_eq_m512d(r, _mm512_setzero_pd());
999        let r = _mm512_maskz_sub_pd(0b00001111, a, b);
1000        let e = _mm512_setr_pd(-1., 0., -2., f64::MAX - 1., 0., 0., 0., 0.);
1001        assert_eq_m512d(r, e);
1002    }
1003
1004    #[simd_test(enable = "avx512f,avx512vl")]
1005    unsafe fn test_mm256_mask_sub_pd() {
1006        let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
1007        let b = _mm256_set1_pd(1.);
1008        let r = _mm256_mask_sub_pd(a, 0, a, b);
1009        assert_eq_m256d(r, a);
1010        let r = _mm256_mask_sub_pd(a, 0b00001111, a, b);
1011        let e = _mm256_set_pd(0., -2., f64::MAX - 1., f64::MIN);
1012        assert_eq_m256d(r, e);
1013    }
1014
1015    #[simd_test(enable = "avx512f,avx512vl")]
1016    unsafe fn test_mm256_maskz_sub_pd() {
1017        let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
1018        let b = _mm256_set1_pd(1.);
1019        let r = _mm256_maskz_sub_pd(0, a, b);
1020        assert_eq_m256d(r, _mm256_setzero_pd());
1021        let r = _mm256_maskz_sub_pd(0b00001111, a, b);
1022        let e = _mm256_set_pd(0., -2., f64::MAX - 1., f64::MIN);
1023        assert_eq_m256d(r, e);
1024    }
1025
1026    #[simd_test(enable = "avx512f,avx512vl")]
1027    unsafe fn test_mm_mask_sub_pd() {
1028        let a = _mm_set_pd(f64::MAX, f64::MIN);
1029        let b = _mm_set1_pd(1.);
1030        let r = _mm_mask_sub_pd(a, 0, a, b);
1031        assert_eq_m128d(r, a);
1032        let r = _mm_mask_sub_pd(a, 0b00000011, a, b);
1033        let e = _mm_set_pd(f64::MAX - 1., f64::MIN);
1034        assert_eq_m128d(r, e);
1035    }
1036
1037    #[simd_test(enable = "avx512f,avx512vl")]
1038    unsafe fn test_mm_maskz_sub_pd() {
1039        let a = _mm_set_pd(f64::MAX, f64::MIN);
1040        let b = _mm_set1_pd(1.);
1041        let r = _mm_maskz_sub_pd(0, a, b);
1042        assert_eq_m128d(r, _mm_setzero_pd());
1043        let r = _mm_maskz_sub_pd(0b00000011, a, b);
1044        let e = _mm_set_pd(f64::MAX - 1., f64::MIN);
1045        assert_eq_m128d(r, e);
1046    }
1047
1048    #[simd_test(enable = "avx512f")]
1049    unsafe fn test_mm512_mul_epi32() {
1050        let a = _mm512_set1_epi32(1);
1051        let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1052        let r = _mm512_mul_epi32(a, b);
1053        let e = _mm512_set_epi64(15, 13, 11, 9, 7, 5, 3, 1);
1054        assert_eq_m512i(r, e);
1055    }
1056
1057    #[simd_test(enable = "avx512f")]
1058    unsafe fn test_mm512_mask_mul_epi32() {
1059        let a = _mm512_set1_epi32(1);
1060        let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1061        let r = _mm512_mask_mul_epi32(a, 0, a, b);
1062        assert_eq_m512i(r, a);
1063        let r = _mm512_mask_mul_epi32(a, 0b00001111, a, b);
1064        #[rustfmt::skip]
1065        let e = _mm512_set_epi64(
1066            1 | 1 << 32, 1 | 1 << 32, 1 | 1 << 32, 1 | 1 << 32,
1067            7, 5, 3, 1,
1068        );
1069        assert_eq_m512i(r, e);
1070    }
1071
1072    #[simd_test(enable = "avx512f")]
1073    unsafe fn test_mm512_maskz_mul_epi32() {
1074        let a = _mm512_set1_epi32(1);
1075        let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1076        let r = _mm512_maskz_mul_epi32(0, a, b);
1077        assert_eq_m512i(r, _mm512_setzero_si512());
1078        let r = _mm512_maskz_mul_epi32(0b00001111, a, b);
1079        let e = _mm512_set_epi64(0, 0, 0, 0, 7, 5, 3, 1);
1080        assert_eq_m512i(r, e);
1081    }
1082
1083    #[simd_test(enable = "avx512f,avx512vl")]
1084    unsafe fn test_mm256_mask_mul_epi32() {
1085        let a = _mm256_set1_epi32(1);
1086        let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
1087        let r = _mm256_mask_mul_epi32(a, 0, a, b);
1088        assert_eq_m256i(r, a);
1089        let r = _mm256_mask_mul_epi32(a, 0b00001111, a, b);
1090        let e = _mm256_set_epi64x(2, 4, 6, 8);
1091        assert_eq_m256i(r, e);
1092    }
1093
1094    #[simd_test(enable = "avx512f,avx512vl")]
1095    unsafe fn test_mm256_maskz_mul_epi32() {
1096        let a = _mm256_set1_epi32(1);
1097        let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
1098        let r = _mm256_maskz_mul_epi32(0, a, b);
1099        assert_eq_m256i(r, _mm256_setzero_si256());
1100        let r = _mm256_maskz_mul_epi32(0b00001111, a, b);
1101        let e = _mm256_set_epi64x(2, 4, 6, 8);
1102        assert_eq_m256i(r, e);
1103    }
1104
1105    #[simd_test(enable = "avx512f,avx512vl")]
1106    unsafe fn test_mm_mask_mul_epi32() {
1107        let a = _mm_set1_epi32(1);
1108        let b = _mm_set_epi32(1, 2, 3, 4);
1109        let r = _mm_mask_mul_epi32(a, 0, a, b);
1110        assert_eq_m128i(r, a);
1111        let r = _mm_mask_mul_epi32(a, 0b00000011, a, b);
1112        let e = _mm_set_epi64x(2, 4);
1113        assert_eq_m128i(r, e);
1114    }
1115
1116    #[simd_test(enable = "avx512f,avx512vl")]
1117    unsafe fn test_mm_maskz_mul_epi32() {
1118        let a = _mm_set1_epi32(1);
1119        let b = _mm_set_epi32(1, 2, 3, 4);
1120        let r = _mm_maskz_mul_epi32(0, a, b);
1121        assert_eq_m128i(r, _mm_setzero_si128());
1122        let r = _mm_maskz_mul_epi32(0b00000011, a, b);
1123        let e = _mm_set_epi64x(2, 4);
1124        assert_eq_m128i(r, e);
1125    }
1126
1127    #[simd_test(enable = "avx512f")]
1128    unsafe fn test_mm512_mul_epu32() {
1129        let a = _mm512_set1_epi32(1);
1130        let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1131        let r = _mm512_mul_epu32(a, b);
1132        let e = _mm512_set_epi64(15, 13, 11, 9, 7, 5, 3, 1);
1133        assert_eq_m512i(r, e);
1134    }
1135
1136    #[simd_test(enable = "avx512f")]
1137    unsafe fn test_mm512_mask_mul_epu32() {
1138        let a = _mm512_set1_epi32(1);
1139        let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1140        let r = _mm512_mask_mul_epu32(a, 0, a, b);
1141        assert_eq_m512i(r, a);
1142        let r = _mm512_mask_mul_epu32(a, 0b00001111, a, b);
1143        #[rustfmt::skip]
1144        let e = _mm512_set_epi64(
1145            1 | 1 << 32, 1 | 1 << 32, 1 | 1 << 32, 1 | 1 << 32,
1146            7, 5, 3, 1,
1147        );
1148        assert_eq_m512i(r, e);
1149    }
1150
1151    #[simd_test(enable = "avx512f")]
1152    unsafe fn test_mm512_maskz_mul_epu32() {
1153        let a = _mm512_set1_epi32(1);
1154        let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1155        let r = _mm512_maskz_mul_epu32(0, a, b);
1156        assert_eq_m512i(r, _mm512_setzero_si512());
1157        let r = _mm512_maskz_mul_epu32(0b00001111, a, b);
1158        let e = _mm512_set_epi64(0, 0, 0, 0, 7, 5, 3, 1);
1159        assert_eq_m512i(r, e);
1160    }
1161
1162    #[simd_test(enable = "avx512f,avx512vl")]
1163    unsafe fn test_mm256_mask_mul_epu32() {
1164        let a = _mm256_set1_epi32(1);
1165        let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
1166        let r = _mm256_mask_mul_epu32(a, 0, a, b);
1167        assert_eq_m256i(r, a);
1168        let r = _mm256_mask_mul_epu32(a, 0b00001111, a, b);
1169        let e = _mm256_set_epi64x(2, 4, 6, 8);
1170        assert_eq_m256i(r, e);
1171    }
1172
1173    #[simd_test(enable = "avx512f,avx512vl")]
1174    unsafe fn test_mm256_maskz_mul_epu32() {
1175        let a = _mm256_set1_epi32(1);
1176        let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
1177        let r = _mm256_maskz_mul_epu32(0, a, b);
1178        assert_eq_m256i(r, _mm256_setzero_si256());
1179        let r = _mm256_maskz_mul_epu32(0b00001111, a, b);
1180        let e = _mm256_set_epi64x(2, 4, 6, 8);
1181        assert_eq_m256i(r, e);
1182    }
1183
1184    #[simd_test(enable = "avx512f,avx512vl")]
1185    unsafe fn test_mm_mask_mul_epu32() {
1186        let a = _mm_set1_epi32(1);
1187        let b = _mm_set_epi32(1, 2, 3, 4);
1188        let r = _mm_mask_mul_epu32(a, 0, a, b);
1189        assert_eq_m128i(r, a);
1190        let r = _mm_mask_mul_epu32(a, 0b00000011, a, b);
1191        let e = _mm_set_epi64x(2, 4);
1192        assert_eq_m128i(r, e);
1193    }
1194
1195    #[simd_test(enable = "avx512f,avx512vl")]
1196    unsafe fn test_mm_maskz_mul_epu32() {
1197        let a = _mm_set1_epi32(1);
1198        let b = _mm_set_epi32(1, 2, 3, 4);
1199        let r = _mm_maskz_mul_epu32(0, a, b);
1200        assert_eq_m128i(r, _mm_setzero_si128());
1201        let r = _mm_maskz_mul_epu32(0b00000011, a, b);
1202        let e = _mm_set_epi64x(2, 4);
1203        assert_eq_m128i(r, e);
1204    }
1205
1206    #[simd_test(enable = "avx512f")]
1207    unsafe fn test_mm512_mullox_epi64() {
1208        let a = _mm512_setr_epi64(0, 1, i64::MAX, i64::MIN, i64::MAX, 100, -100, -32);
1209        let b = _mm512_set1_epi64(2);
1210        let r = _mm512_mullox_epi64(a, b);
1211        let e = _mm512_setr_epi64(0, 2, -2, 0, -2, 200, -200, -64);
1212        assert_eq_m512i(r, e);
1213    }
1214
1215    #[simd_test(enable = "avx512f")]
1216    unsafe fn test_mm512_mask_mullox_epi64() {
1217        let a = _mm512_setr_epi64(0, 1, i64::MAX, i64::MIN, i64::MAX, 100, -100, -32);
1218        let b = _mm512_set1_epi64(2);
1219        let r = _mm512_mask_mullox_epi64(a, 0, a, b);
1220        assert_eq_m512i(r, a);
1221        let r = _mm512_mask_mullox_epi64(a, 0b00001111, a, b);
1222        let e = _mm512_setr_epi64(0, 2, -2, 0, i64::MAX, 100, -100, -32);
1223        assert_eq_m512i(r, e);
1224    }
1225
1226    #[simd_test(enable = "avx512f")]
1227    unsafe fn test_mm512_mul_pd() {
1228        let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1229        let b = _mm512_set1_pd(2.);
1230        let r = _mm512_mul_pd(a, b);
1231        #[rustfmt::skip]
1232        let e = _mm512_setr_pd(
1233            0., 2., f64::INFINITY, f64::NEG_INFINITY,
1234            f64::INFINITY, f64::NEG_INFINITY, -200., -64.,
1235        );
1236        assert_eq_m512d(r, e);
1237    }
1238
1239    #[simd_test(enable = "avx512f")]
1240    unsafe fn test_mm512_mask_mul_pd() {
1241        let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1242        let b = _mm512_set1_pd(2.);
1243        let r = _mm512_mask_mul_pd(a, 0, a, b);
1244        assert_eq_m512d(r, a);
1245        let r = _mm512_mask_mul_pd(a, 0b00001111, a, b);
1246        #[rustfmt::skip]
1247        let e = _mm512_setr_pd(
1248            0., 2., f64::INFINITY, f64::NEG_INFINITY,
1249            f64::MAX, f64::MIN, -100., -32.,
1250        );
1251        assert_eq_m512d(r, e);
1252    }
1253
1254    #[simd_test(enable = "avx512f")]
1255    unsafe fn test_mm512_maskz_mul_pd() {
1256        let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1257        let b = _mm512_set1_pd(2.);
1258        let r = _mm512_maskz_mul_pd(0, a, b);
1259        assert_eq_m512d(r, _mm512_setzero_pd());
1260        let r = _mm512_maskz_mul_pd(0b00001111, a, b);
1261        let e = _mm512_setr_pd(0., 2., f64::INFINITY, f64::NEG_INFINITY, 0., 0., 0., 0.);
1262        assert_eq_m512d(r, e);
1263    }
1264
1265    #[simd_test(enable = "avx512f,avx512vl")]
1266    unsafe fn test_mm256_mask_mul_pd() {
1267        let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
1268        let b = _mm256_set1_pd(2.);
1269        let r = _mm256_mask_mul_pd(a, 0, a, b);
1270        assert_eq_m256d(r, a);
1271        let r = _mm256_mask_mul_pd(a, 0b00001111, a, b);
1272        let e = _mm256_set_pd(0., 2., f64::INFINITY, f64::NEG_INFINITY);
1273        assert_eq_m256d(r, e);
1274    }
1275
1276    #[simd_test(enable = "avx512f,avx512vl")]
1277    unsafe fn test_mm256_maskz_mul_pd() {
1278        let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
1279        let b = _mm256_set1_pd(2.);
1280        let r = _mm256_maskz_mul_pd(0, a, b);
1281        assert_eq_m256d(r, _mm256_setzero_pd());
1282        let r = _mm256_maskz_mul_pd(0b00001111, a, b);
1283        let e = _mm256_set_pd(0., 2., f64::INFINITY, f64::NEG_INFINITY);
1284        assert_eq_m256d(r, e);
1285    }
1286
1287    #[simd_test(enable = "avx512f,avx512vl")]
1288    unsafe fn test_mm_mask_mul_pd() {
1289        let a = _mm_set_pd(f64::MAX, f64::MIN);
1290        let b = _mm_set1_pd(2.);
1291        let r = _mm_mask_mul_pd(a, 0, a, b);
1292        assert_eq_m128d(r, a);
1293        let r = _mm_mask_mul_pd(a, 0b00000011, a, b);
1294        let e = _mm_set_pd(f64::INFINITY, f64::NEG_INFINITY);
1295        assert_eq_m128d(r, e);
1296    }
1297
1298    #[simd_test(enable = "avx512f,avx512vl")]
1299    unsafe fn test_mm_maskz_mul_pd() {
1300        let a = _mm_set_pd(f64::MAX, f64::MIN);
1301        let b = _mm_set1_pd(2.);
1302        let r = _mm_maskz_mul_pd(0, a, b);
1303        assert_eq_m128d(r, _mm_setzero_pd());
1304        let r = _mm_maskz_mul_pd(0b00000011, a, b);
1305        let e = _mm_set_pd(f64::INFINITY, f64::NEG_INFINITY);
1306        assert_eq_m128d(r, e);
1307    }
1308
1309    #[simd_test(enable = "avx512f")]
1310    unsafe fn test_mm512_div_pd() {
1311        let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1312        let b = _mm512_setr_pd(2., 2., 0., 0., 0., 0., 2., 2.);
1313        let r = _mm512_div_pd(a, b);
1314        #[rustfmt::skip]
1315        let e = _mm512_setr_pd(
1316            0., 0.5, f64::INFINITY, f64::NEG_INFINITY,
1317            f64::INFINITY, f64::NEG_INFINITY, -50., -16.,
1318        );
1319        assert_eq_m512d(r, e);
1320    }
1321
1322    #[simd_test(enable = "avx512f")]
1323    unsafe fn test_mm512_mask_div_pd() {
1324        let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1325        let b = _mm512_setr_pd(2., 2., 0., 0., 0., 0., 2., 2.);
1326        let r = _mm512_mask_div_pd(a, 0, a, b);
1327        assert_eq_m512d(r, a);
1328        let r = _mm512_mask_div_pd(a, 0b00001111, a, b);
1329        #[rustfmt::skip]
1330        let e = _mm512_setr_pd(
1331            0., 0.5, f64::INFINITY, f64::NEG_INFINITY,
1332            f64::MAX, f64::MIN, -100., -32.,
1333        );
1334        assert_eq_m512d(r, e);
1335    }
1336
1337    #[simd_test(enable = "avx512f")]
1338    unsafe fn test_mm512_maskz_div_pd() {
1339        let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1340        let b = _mm512_setr_pd(2., 2., 0., 0., 0., 0., 2., 2.);
1341        let r = _mm512_maskz_div_pd(0, a, b);
1342        assert_eq_m512d(r, _mm512_setzero_pd());
1343        let r = _mm512_maskz_div_pd(0b00001111, a, b);
1344        let e = _mm512_setr_pd(0., 0.5, f64::INFINITY, f64::NEG_INFINITY, 0., 0., 0., 0.);
1345        assert_eq_m512d(r, e);
1346    }
1347
1348    #[simd_test(enable = "avx512f,avx512vl")]
1349    unsafe fn test_mm256_mask_div_pd() {
1350        let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
1351        let b = _mm256_set_pd(2., 2., 0., 0.);
1352        let r = _mm256_mask_div_pd(a, 0, a, b);
1353        assert_eq_m256d(r, a);
1354        let r = _mm256_mask_div_pd(a, 0b00001111, a, b);
1355        let e = _mm256_set_pd(0., 0.5, f64::INFINITY, f64::NEG_INFINITY);
1356        assert_eq_m256d(r, e);
1357    }
1358
1359    #[simd_test(enable = "avx512f,avx512vl")]
1360    unsafe fn test_mm256_maskz_div_pd() {
1361        let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
1362        let b = _mm256_set_pd(2., 2., 0., 0.);
1363        let r = _mm256_maskz_div_pd(0, a, b);
1364        assert_eq_m256d(r, _mm256_setzero_pd());
1365        let r = _mm256_maskz_div_pd(0b00001111, a, b);
1366        let e = _mm256_set_pd(0., 0.5, f64::INFINITY, f64::NEG_INFINITY);
1367        assert_eq_m256d(r, e);
1368    }
1369
1370    #[simd_test(enable = "avx512f,avx512vl")]
1371    unsafe fn test_mm_mask_div_pd() {
1372        let a = _mm_set_pd(f64::MAX, f64::MIN);
1373        let b = _mm_set_pd(0., 0.);
1374        let r = _mm_mask_div_pd(a, 0, a, b);
1375        assert_eq_m128d(r, a);
1376        let r = _mm_mask_div_pd(a, 0b00000011, a, b);
1377        let e = _mm_set_pd(f64::INFINITY, f64::NEG_INFINITY);
1378        assert_eq_m128d(r, e);
1379    }
1380
1381    #[simd_test(enable = "avx512f,avx512vl")]
1382    unsafe fn test_mm_maskz_div_pd() {
1383        let a = _mm_set_pd(f64::MAX, f64::MIN);
1384        let b = _mm_set_pd(0., 0.);
1385        let r = _mm_maskz_div_pd(0, a, b);
1386        assert_eq_m128d(r, _mm_setzero_pd());
1387        let r = _mm_maskz_div_pd(0b00000011, a, b);
1388        let e = _mm_set_pd(f64::INFINITY, f64::NEG_INFINITY);
1389        assert_eq_m128d(r, e);
1390    }
1391
1392    #[simd_test(enable = "avx512f")]
1393    unsafe fn test_mm512_max_epi64() {
1394        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1395        let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1396        let r = _mm512_max_epi64(a, b);
1397        let e = _mm512_setr_epi64(7, 6, 5, 4, 4, 5, 6, 7);
1398        assert_eq_m512i(r, e);
1399    }
1400
1401    #[simd_test(enable = "avx512f")]
1402    unsafe fn test_mm512_mask_max_epi64() {
1403        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1404        let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1405        let r = _mm512_mask_max_epi64(a, 0, a, b);
1406        assert_eq_m512i(r, a);
1407        let r = _mm512_mask_max_epi64(a, 0b00001111, a, b);
1408        let e = _mm512_setr_epi64(7, 6, 5, 4, 4, 5, 6, 7);
1409        assert_eq_m512i(r, e);
1410    }
1411
1412    #[simd_test(enable = "avx512f")]
1413    unsafe fn test_mm512_maskz_max_epi64() {
1414        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1415        let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1416        let r = _mm512_maskz_max_epi64(0, a, b);
1417        assert_eq_m512i(r, _mm512_setzero_si512());
1418        let r = _mm512_maskz_max_epi64(0b00001111, a, b);
1419        let e = _mm512_setr_epi64(7, 6, 5, 4, 0, 0, 0, 0);
1420        assert_eq_m512i(r, e);
1421    }
1422
1423    #[simd_test(enable = "avx512f,avx512vl")]
1424    unsafe fn test_mm256_max_epi64() {
1425        let a = _mm256_set_epi64x(0, 1, 2, 3);
1426        let b = _mm256_set_epi64x(3, 2, 1, 0);
1427        let r = _mm256_max_epi64(a, b);
1428        let e = _mm256_set_epi64x(3, 2, 2, 3);
1429        assert_eq_m256i(r, e);
1430    }
1431
1432    #[simd_test(enable = "avx512f,avx512vl")]
1433    unsafe fn test_mm256_mask_max_epi64() {
1434        let a = _mm256_set_epi64x(0, 1, 2, 3);
1435        let b = _mm256_set_epi64x(3, 2, 1, 0);
1436        let r = _mm256_mask_max_epi64(a, 0, a, b);
1437        assert_eq_m256i(r, a);
1438        let r = _mm256_mask_max_epi64(a, 0b00001111, a, b);
1439        let e = _mm256_set_epi64x(3, 2, 2, 3);
1440        assert_eq_m256i(r, e);
1441    }
1442
1443    #[simd_test(enable = "avx512f,avx512vl")]
1444    unsafe fn test_mm256_maskz_max_epi64() {
1445        let a = _mm256_set_epi64x(0, 1, 2, 3);
1446        let b = _mm256_set_epi64x(3, 2, 1, 0);
1447        let r = _mm256_maskz_max_epi64(0, a, b);
1448        assert_eq_m256i(r, _mm256_setzero_si256());
1449        let r = _mm256_maskz_max_epi64(0b00001111, a, b);
1450        let e = _mm256_set_epi64x(3, 2, 2, 3);
1451        assert_eq_m256i(r, e);
1452    }
1453
1454    #[simd_test(enable = "avx512f,avx512vl")]
1455    unsafe fn test_mm_max_epi64() {
1456        let a = _mm_set_epi64x(2, 3);
1457        let b = _mm_set_epi64x(3, 2);
1458        let r = _mm_max_epi64(a, b);
1459        let e = _mm_set_epi64x(3, 3);
1460        assert_eq_m128i(r, e);
1461    }
1462
1463    #[simd_test(enable = "avx512f,avx512vl")]
1464    unsafe fn test_mm_mask_max_epi64() {
1465        let a = _mm_set_epi64x(2, 3);
1466        let b = _mm_set_epi64x(3, 2);
1467        let r = _mm_mask_max_epi64(a, 0, a, b);
1468        assert_eq_m128i(r, a);
1469        let r = _mm_mask_max_epi64(a, 0b00000011, a, b);
1470        let e = _mm_set_epi64x(3, 3);
1471        assert_eq_m128i(r, e);
1472    }
1473
1474    #[simd_test(enable = "avx512f,avx512vl")]
1475    unsafe fn test_mm_maskz_max_epi64() {
1476        let a = _mm_set_epi64x(2, 3);
1477        let b = _mm_set_epi64x(3, 2);
1478        let r = _mm_maskz_max_epi64(0, a, b);
1479        assert_eq_m128i(r, _mm_setzero_si128());
1480        let r = _mm_maskz_max_epi64(0b00000011, a, b);
1481        let e = _mm_set_epi64x(3, 3);
1482        assert_eq_m128i(r, e);
1483    }
1484
1485    #[simd_test(enable = "avx512f")]
1486    unsafe fn test_mm512_max_pd() {
1487        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1488        let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1489        let r = _mm512_max_pd(a, b);
1490        let e = _mm512_setr_pd(7., 6., 5., 4., 4., 5., 6., 7.);
1491        assert_eq_m512d(r, e);
1492    }
1493
1494    #[simd_test(enable = "avx512f")]
1495    unsafe fn test_mm512_mask_max_pd() {
1496        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1497        let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1498        let r = _mm512_mask_max_pd(a, 0, a, b);
1499        assert_eq_m512d(r, a);
1500        let r = _mm512_mask_max_pd(a, 0b00001111, a, b);
1501        let e = _mm512_setr_pd(7., 6., 5., 4., 4., 5., 6., 7.);
1502        assert_eq_m512d(r, e);
1503    }
1504
1505    #[simd_test(enable = "avx512f")]
1506    unsafe fn test_mm512_maskz_max_pd() {
1507        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1508        let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1509        let r = _mm512_maskz_max_pd(0, a, b);
1510        assert_eq_m512d(r, _mm512_setzero_pd());
1511        let r = _mm512_maskz_max_pd(0b00001111, a, b);
1512        let e = _mm512_setr_pd(7., 6., 5., 4., 0., 0., 0., 0.);
1513        assert_eq_m512d(r, e);
1514    }
1515
1516    #[simd_test(enable = "avx512f,avx512vl")]
1517    unsafe fn test_mm256_mask_max_pd() {
1518        let a = _mm256_set_pd(0., 1., 2., 3.);
1519        let b = _mm256_set_pd(3., 2., 1., 0.);
1520        let r = _mm256_mask_max_pd(a, 0, a, b);
1521        assert_eq_m256d(r, a);
1522        let r = _mm256_mask_max_pd(a, 0b00001111, a, b);
1523        let e = _mm256_set_pd(3., 2., 2., 3.);
1524        assert_eq_m256d(r, e);
1525    }
1526
1527    #[simd_test(enable = "avx512f,avx512vl")]
1528    unsafe fn test_mm256_maskz_max_pd() {
1529        let a = _mm256_set_pd(0., 1., 2., 3.);
1530        let b = _mm256_set_pd(3., 2., 1., 0.);
1531        let r = _mm256_maskz_max_pd(0, a, b);
1532        assert_eq_m256d(r, _mm256_setzero_pd());
1533        let r = _mm256_maskz_max_pd(0b00001111, a, b);
1534        let e = _mm256_set_pd(3., 2., 2., 3.);
1535        assert_eq_m256d(r, e);
1536    }
1537
1538    #[simd_test(enable = "avx512f,avx512vl")]
1539    unsafe fn test_mm_mask_max_pd() {
1540        let a = _mm_set_pd(2., 3.);
1541        let b = _mm_set_pd(3., 2.);
1542        let r = _mm_mask_max_pd(a, 0, a, b);
1543        assert_eq_m128d(r, a);
1544        let r = _mm_mask_max_pd(a, 0b00000011, a, b);
1545        let e = _mm_set_pd(3., 3.);
1546        assert_eq_m128d(r, e);
1547    }
1548
1549    #[simd_test(enable = "avx512f,avx512vl")]
1550    unsafe fn test_mm_maskz_max_pd() {
1551        let a = _mm_set_pd(2., 3.);
1552        let b = _mm_set_pd(3., 2.);
1553        let r = _mm_maskz_max_pd(0, a, b);
1554        assert_eq_m128d(r, _mm_setzero_pd());
1555        let r = _mm_maskz_max_pd(0b00000011, a, b);
1556        let e = _mm_set_pd(3., 3.);
1557        assert_eq_m128d(r, e);
1558    }
1559
1560    #[simd_test(enable = "avx512f")]
1561    unsafe fn test_mm512_max_epu64() {
1562        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1563        let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1564        let r = _mm512_max_epu64(a, b);
1565        let e = _mm512_setr_epi64(7, 6, 5, 4, 4, 5, 6, 7);
1566        assert_eq_m512i(r, e);
1567    }
1568
1569    #[simd_test(enable = "avx512f")]
1570    unsafe fn test_mm512_mask_max_epu64() {
1571        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1572        let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1573        let r = _mm512_mask_max_epu64(a, 0, a, b);
1574        assert_eq_m512i(r, a);
1575        let r = _mm512_mask_max_epu64(a, 0b00001111, a, b);
1576        let e = _mm512_setr_epi64(7, 6, 5, 4, 4, 5, 6, 7);
1577        assert_eq_m512i(r, e);
1578    }
1579
1580    #[simd_test(enable = "avx512f")]
1581    unsafe fn test_mm512_maskz_max_epu64() {
1582        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1583        let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1584        let r = _mm512_maskz_max_epu64(0, a, b);
1585        assert_eq_m512i(r, _mm512_setzero_si512());
1586        let r = _mm512_maskz_max_epu64(0b00001111, a, b);
1587        let e = _mm512_setr_epi64(7, 6, 5, 4, 0, 0, 0, 0);
1588        assert_eq_m512i(r, e);
1589    }
1590
1591    #[simd_test(enable = "avx512f,avx512vl")]
1592    unsafe fn test_mm256_max_epu64() {
1593        let a = _mm256_set_epi64x(0, 1, 2, 3);
1594        let b = _mm256_set_epi64x(3, 2, 1, 0);
1595        let r = _mm256_max_epu64(a, b);
1596        let e = _mm256_set_epi64x(3, 2, 2, 3);
1597        assert_eq_m256i(r, e);
1598    }
1599
1600    #[simd_test(enable = "avx512f,avx512vl")]
1601    unsafe fn test_mm256_mask_max_epu64() {
1602        let a = _mm256_set_epi64x(0, 1, 2, 3);
1603        let b = _mm256_set_epi64x(3, 2, 1, 0);
1604        let r = _mm256_mask_max_epu64(a, 0, a, b);
1605        assert_eq_m256i(r, a);
1606        let r = _mm256_mask_max_epu64(a, 0b00001111, a, b);
1607        let e = _mm256_set_epi64x(3, 2, 2, 3);
1608        assert_eq_m256i(r, e);
1609    }
1610
1611    #[simd_test(enable = "avx512f,avx512vl")]
1612    unsafe fn test_mm256_maskz_max_epu64() {
1613        let a = _mm256_set_epi64x(0, 1, 2, 3);
1614        let b = _mm256_set_epi64x(3, 2, 1, 0);
1615        let r = _mm256_maskz_max_epu64(0, a, b);
1616        assert_eq_m256i(r, _mm256_setzero_si256());
1617        let r = _mm256_maskz_max_epu64(0b00001111, a, b);
1618        let e = _mm256_set_epi64x(3, 2, 2, 3);
1619        assert_eq_m256i(r, e);
1620    }
1621
1622    #[simd_test(enable = "avx512f,avx512vl")]
1623    unsafe fn test_mm_max_epu64() {
1624        let a = _mm_set_epi64x(2, 3);
1625        let b = _mm_set_epi64x(3, 2);
1626        let r = _mm_max_epu64(a, b);
1627        let e = _mm_set_epi64x(3, 3);
1628        assert_eq_m128i(r, e);
1629    }
1630
1631    #[simd_test(enable = "avx512f,avx512vl")]
1632    unsafe fn test_mm_mask_max_epu64() {
1633        let a = _mm_set_epi64x(2, 3);
1634        let b = _mm_set_epi64x(3, 2);
1635        let r = _mm_mask_max_epu64(a, 0, a, b);
1636        assert_eq_m128i(r, a);
1637        let r = _mm_mask_max_epu64(a, 0b00000011, a, b);
1638        let e = _mm_set_epi64x(3, 3);
1639        assert_eq_m128i(r, e);
1640    }
1641
1642    #[simd_test(enable = "avx512f,avx512vl")]
1643    unsafe fn test_mm_maskz_max_epu64() {
1644        let a = _mm_set_epi64x(2, 3);
1645        let b = _mm_set_epi64x(3, 2);
1646        let r = _mm_maskz_max_epu64(0, a, b);
1647        assert_eq_m128i(r, _mm_setzero_si128());
1648        let r = _mm_maskz_max_epu64(0b00000011, a, b);
1649        let e = _mm_set_epi64x(3, 3);
1650        assert_eq_m128i(r, e);
1651    }
1652
1653    #[simd_test(enable = "avx512f")]
1654    unsafe fn test_mm512_min_epi64() {
1655        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1656        let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1657        let r = _mm512_min_epi64(a, b);
1658        let e = _mm512_setr_epi64(0, 1, 2, 3, 3, 2, 1, 0);
1659        assert_eq_m512i(r, e);
1660    }
1661
1662    #[simd_test(enable = "avx512f")]
1663    unsafe fn test_mm512_mask_min_epi64() {
1664        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1665        let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1666        let r = _mm512_mask_min_epi64(a, 0, a, b);
1667        assert_eq_m512i(r, a);
1668        let r = _mm512_mask_min_epi64(a, 0b00001111, a, b);
1669        let e = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1670        assert_eq_m512i(r, e);
1671    }
1672
1673    #[simd_test(enable = "avx512f")]
1674    unsafe fn test_mm512_maskz_min_epi64() {
1675        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1676        let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1677        let r = _mm512_maskz_min_epi64(0, a, b);
1678        assert_eq_m512i(r, _mm512_setzero_si512());
1679        let r = _mm512_maskz_min_epi64(0b00001111, a, b);
1680        let e = _mm512_setr_epi64(0, 1, 2, 3, 0, 0, 0, 0);
1681        assert_eq_m512i(r, e);
1682    }
1683
1684    #[simd_test(enable = "avx512f,avx512vl")]
1685    unsafe fn test_mm256_min_epi64() {
1686        let a = _mm256_set_epi64x(0, 1, 2, 3);
1687        let b = _mm256_set_epi64x(3, 2, 1, 0);
1688        let r = _mm256_min_epi64(a, b);
1689        let e = _mm256_set_epi64x(0, 1, 1, 0);
1690        assert_eq_m256i(r, e);
1691    }
1692
1693    #[simd_test(enable = "avx512f,avx512vl")]
1694    unsafe fn test_mm256_mask_min_epi64() {
1695        let a = _mm256_set_epi64x(0, 1, 2, 3);
1696        let b = _mm256_set_epi64x(3, 2, 1, 0);
1697        let r = _mm256_mask_min_epi64(a, 0, a, b);
1698        assert_eq_m256i(r, a);
1699        let r = _mm256_mask_min_epi64(a, 0b00001111, a, b);
1700        let e = _mm256_set_epi64x(0, 1, 1, 0);
1701        assert_eq_m256i(r, e);
1702    }
1703
1704    #[simd_test(enable = "avx512f,avx512vl")]
1705    unsafe fn test_mm256_maskz_min_epi64() {
1706        let a = _mm256_set_epi64x(0, 1, 2, 3);
1707        let b = _mm256_set_epi64x(3, 2, 1, 0);
1708        let r = _mm256_maskz_min_epi64(0, a, b);
1709        assert_eq_m256i(r, _mm256_setzero_si256());
1710        let r = _mm256_maskz_min_epi64(0b00001111, a, b);
1711        let e = _mm256_set_epi64x(0, 1, 1, 0);
1712        assert_eq_m256i(r, e);
1713    }
1714
1715    #[simd_test(enable = "avx512f,avx512vl")]
1716    unsafe fn test_mm_min_epi64() {
1717        let a = _mm_set_epi64x(0, 1);
1718        let b = _mm_set_epi64x(3, 2);
1719        let r = _mm_min_epi64(a, b);
1720        let e = _mm_set_epi64x(0, 1);
1721        assert_eq_m128i(r, e);
1722        let a = _mm_set_epi64x(2, 3);
1723        let b = _mm_set_epi64x(1, 0);
1724        let r = _mm_min_epi64(a, b);
1725        let e = _mm_set_epi64x(1, 0);
1726        assert_eq_m128i(r, e);
1727    }
1728
1729    #[simd_test(enable = "avx512f,avx512vl")]
1730    unsafe fn test_mm_mask_min_epi64() {
1731        let a = _mm_set_epi64x(0, 1);
1732        let b = _mm_set_epi64x(3, 2);
1733        let r = _mm_mask_min_epi64(a, 0, a, b);
1734        assert_eq_m128i(r, a);
1735        let r = _mm_mask_min_epi64(a, 0b00000011, a, b);
1736        let e = _mm_set_epi64x(0, 1);
1737        assert_eq_m128i(r, e);
1738    }
1739
1740    #[simd_test(enable = "avx512f,avx512vl")]
1741    unsafe fn test_mm_maskz_min_epi64() {
1742        let a = _mm_set_epi64x(0, 1);
1743        let b = _mm_set_epi64x(3, 2);
1744        let r = _mm_maskz_min_epi64(0, a, b);
1745        assert_eq_m128i(r, _mm_setzero_si128());
1746        let r = _mm_maskz_min_epi64(0b00000011, a, b);
1747        let e = _mm_set_epi64x(0, 1);
1748        assert_eq_m128i(r, e);
1749    }
1750
1751    #[simd_test(enable = "avx512f")]
1752    unsafe fn test_mm512_min_pd() {
1753        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1754        let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1755        let r = _mm512_min_pd(a, b);
1756        let e = _mm512_setr_pd(0., 1., 2., 3., 3., 2., 1., 0.);
1757        assert_eq_m512d(r, e);
1758    }
1759
1760    #[simd_test(enable = "avx512f")]
1761    unsafe fn test_mm512_mask_min_pd() {
1762        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1763        let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1764        let r = _mm512_mask_min_pd(a, 0, a, b);
1765        assert_eq_m512d(r, a);
1766        let r = _mm512_mask_min_pd(a, 0b00001111, a, b);
1767        let e = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1768        assert_eq_m512d(r, e);
1769    }
1770
1771    #[simd_test(enable = "avx512f")]
1772    unsafe fn test_mm512_maskz_min_pd() {
1773        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1774        let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1775        let r = _mm512_maskz_min_pd(0, a, b);
1776        assert_eq_m512d(r, _mm512_setzero_pd());
1777        let r = _mm512_maskz_min_pd(0b00001111, a, b);
1778        let e = _mm512_setr_pd(0., 1., 2., 3., 0., 0., 0., 0.);
1779        assert_eq_m512d(r, e);
1780    }
1781
1782    #[simd_test(enable = "avx512f,avx512vl")]
1783    unsafe fn test_mm256_mask_min_pd() {
1784        let a = _mm256_set_pd(0., 1., 2., 3.);
1785        let b = _mm256_set_pd(3., 2., 1., 0.);
1786        let r = _mm256_mask_min_pd(a, 0, a, b);
1787        assert_eq_m256d(r, a);
1788        let r = _mm256_mask_min_pd(a, 0b00001111, a, b);
1789        let e = _mm256_set_pd(0., 1., 1., 0.);
1790        assert_eq_m256d(r, e);
1791    }
1792
1793    #[simd_test(enable = "avx512f,avx512vl")]
1794    unsafe fn test_mm256_maskz_min_pd() {
1795        let a = _mm256_set_pd(0., 1., 2., 3.);
1796        let b = _mm256_set_pd(3., 2., 1., 0.);
1797        let r = _mm256_maskz_min_pd(0, a, b);
1798        assert_eq_m256d(r, _mm256_setzero_pd());
1799        let r = _mm256_maskz_min_pd(0b00001111, a, b);
1800        let e = _mm256_set_pd(0., 1., 1., 0.);
1801        assert_eq_m256d(r, e);
1802    }
1803
1804    #[simd_test(enable = "avx512f,avx512vl")]
1805    unsafe fn test_mm_mask_min_pd() {
1806        let a = _mm_set_pd(0., 1.);
1807        let b = _mm_set_pd(1., 0.);
1808        let r = _mm_mask_min_pd(a, 0, a, b);
1809        assert_eq_m128d(r, a);
1810        let r = _mm_mask_min_pd(a, 0b00000011, a, b);
1811        let e = _mm_set_pd(0., 0.);
1812        assert_eq_m128d(r, e);
1813    }
1814
1815    #[simd_test(enable = "avx512f,avx512vl")]
1816    unsafe fn test_mm_maskz_min_pd() {
1817        let a = _mm_set_pd(0., 1.);
1818        let b = _mm_set_pd(1., 0.);
1819        let r = _mm_maskz_min_pd(0, a, b);
1820        assert_eq_m128d(r, _mm_setzero_pd());
1821        let r = _mm_maskz_min_pd(0b00000011, a, b);
1822        let e = _mm_set_pd(0., 0.);
1823        assert_eq_m128d(r, e);
1824    }
1825
1826    #[simd_test(enable = "avx512f")]
1827    unsafe fn test_mm512_min_epu64() {
1828        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1829        let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1830        let r = _mm512_min_epu64(a, b);
1831        let e = _mm512_setr_epi64(0, 1, 2, 3, 3, 2, 1, 0);
1832        assert_eq_m512i(r, e);
1833    }
1834
1835    #[simd_test(enable = "avx512f")]
1836    unsafe fn test_mm512_mask_min_epu64() {
1837        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1838        let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1839        let r = _mm512_mask_min_epu64(a, 0, a, b);
1840        assert_eq_m512i(r, a);
1841        let r = _mm512_mask_min_epu64(a, 0b00001111, a, b);
1842        let e = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1843        assert_eq_m512i(r, e);
1844    }
1845
1846    #[simd_test(enable = "avx512f")]
1847    unsafe fn test_mm512_maskz_min_epu64() {
1848        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1849        let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1850        let r = _mm512_maskz_min_epu64(0, a, b);
1851        assert_eq_m512i(r, _mm512_setzero_si512());
1852        let r = _mm512_maskz_min_epu64(0b00001111, a, b);
1853        let e = _mm512_setr_epi64(0, 1, 2, 3, 0, 0, 0, 0);
1854        assert_eq_m512i(r, e);
1855    }
1856
1857    #[simd_test(enable = "avx512f,avx512vl")]
1858    unsafe fn test_mm256_min_epu64() {
1859        let a = _mm256_set_epi64x(0, 1, 2, 3);
1860        let b = _mm256_set_epi64x(3, 2, 1, 0);
1861        let r = _mm256_min_epu64(a, b);
1862        let e = _mm256_set_epi64x(0, 1, 1, 0);
1863        assert_eq_m256i(r, e);
1864    }
1865
1866    #[simd_test(enable = "avx512f,avx512vl")]
1867    unsafe fn test_mm256_mask_min_epu64() {
1868        let a = _mm256_set_epi64x(0, 1, 2, 3);
1869        let b = _mm256_set_epi64x(3, 2, 1, 0);
1870        let r = _mm256_mask_min_epu64(a, 0, a, b);
1871        assert_eq_m256i(r, a);
1872        let r = _mm256_mask_min_epu64(a, 0b00001111, a, b);
1873        let e = _mm256_set_epi64x(0, 1, 1, 0);
1874        assert_eq_m256i(r, e);
1875    }
1876
1877    #[simd_test(enable = "avx512f,avx512vl")]
1878    unsafe fn test_mm256_maskz_min_epu64() {
1879        let a = _mm256_set_epi64x(0, 1, 2, 3);
1880        let b = _mm256_set_epi64x(3, 2, 1, 0);
1881        let r = _mm256_maskz_min_epu64(0, a, b);
1882        assert_eq_m256i(r, _mm256_setzero_si256());
1883        let r = _mm256_maskz_min_epu64(0b00001111, a, b);
1884        let e = _mm256_set_epi64x(0, 1, 1, 0);
1885        assert_eq_m256i(r, e);
1886    }
1887
1888    #[simd_test(enable = "avx512f,avx512vl")]
1889    unsafe fn test_mm_min_epu64() {
1890        let a = _mm_set_epi64x(0, 1);
1891        let b = _mm_set_epi64x(1, 0);
1892        let r = _mm_min_epu64(a, b);
1893        let e = _mm_set_epi64x(0, 0);
1894        assert_eq_m128i(r, e);
1895    }
1896
1897    #[simd_test(enable = "avx512f,avx512vl")]
1898    unsafe fn test_mm_mask_min_epu64() {
1899        let a = _mm_set_epi64x(0, 1);
1900        let b = _mm_set_epi64x(1, 0);
1901        let r = _mm_mask_min_epu64(a, 0, a, b);
1902        assert_eq_m128i(r, a);
1903        let r = _mm_mask_min_epu64(a, 0b00000011, a, b);
1904        let e = _mm_set_epi64x(0, 0);
1905        assert_eq_m128i(r, e);
1906    }
1907
1908    #[simd_test(enable = "avx512f,avx512vl")]
1909    unsafe fn test_mm_maskz_min_epu64() {
1910        let a = _mm_set_epi64x(0, 1);
1911        let b = _mm_set_epi64x(1, 0);
1912        let r = _mm_maskz_min_epu64(0, a, b);
1913        assert_eq_m128i(r, _mm_setzero_si128());
1914        let r = _mm_maskz_min_epu64(0b00000011, a, b);
1915        let e = _mm_set_epi64x(0, 0);
1916        assert_eq_m128i(r, e);
1917    }
1918
1919    #[simd_test(enable = "avx512f")]
1920    unsafe fn test_mm512_sqrt_pd() {
1921        let a = _mm512_setr_pd(0., 1., 4., 9., 16., 25., 36., 49.);
1922        let r = _mm512_sqrt_pd(a);
1923        let e = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1924        assert_eq_m512d(r, e);
1925    }
1926
1927    #[simd_test(enable = "avx512f")]
1928    unsafe fn test_mm512_mask_sqrt_pd() {
1929        let a = _mm512_setr_pd(0., 1., 4., 9., 16., 25., 36., 49.);
1930        let r = _mm512_mask_sqrt_pd(a, 0, a);
1931        assert_eq_m512d(r, a);
1932        let r = _mm512_mask_sqrt_pd(a, 0b00001111, a);
1933        let e = _mm512_setr_pd(0., 1., 2., 3., 16., 25., 36., 49.);
1934        assert_eq_m512d(r, e);
1935    }
1936
1937    #[simd_test(enable = "avx512f")]
1938    unsafe fn test_mm512_maskz_sqrt_pd() {
1939        let a = _mm512_setr_pd(0., 1., 4., 9., 16., 25., 36., 49.);
1940        let r = _mm512_maskz_sqrt_pd(0, a);
1941        assert_eq_m512d(r, _mm512_setzero_pd());
1942        let r = _mm512_maskz_sqrt_pd(0b00001111, a);
1943        let e = _mm512_setr_pd(0., 1., 2., 3., 0., 0., 0., 0.);
1944        assert_eq_m512d(r, e);
1945    }
1946
1947    #[simd_test(enable = "avx512f,avx512vl")]
1948    unsafe fn test_mm256_mask_sqrt_pd() {
1949        let a = _mm256_set_pd(0., 1., 4., 9.);
1950        let r = _mm256_mask_sqrt_pd(a, 0, a);
1951        assert_eq_m256d(r, a);
1952        let r = _mm256_mask_sqrt_pd(a, 0b00001111, a);
1953        let e = _mm256_set_pd(0., 1., 2., 3.);
1954        assert_eq_m256d(r, e);
1955    }
1956
1957    #[simd_test(enable = "avx512f,avx512vl")]
1958    unsafe fn test_mm256_maskz_sqrt_pd() {
1959        let a = _mm256_set_pd(0., 1., 4., 9.);
1960        let r = _mm256_maskz_sqrt_pd(0, a);
1961        assert_eq_m256d(r, _mm256_setzero_pd());
1962        let r = _mm256_maskz_sqrt_pd(0b00001111, a);
1963        let e = _mm256_set_pd(0., 1., 2., 3.);
1964        assert_eq_m256d(r, e);
1965    }
1966
1967    #[simd_test(enable = "avx512f,avx512vl")]
1968    unsafe fn test_mm_mask_sqrt_pd() {
1969        let a = _mm_set_pd(0., 1.);
1970        let r = _mm_mask_sqrt_pd(a, 0, a);
1971        assert_eq_m128d(r, a);
1972        let r = _mm_mask_sqrt_pd(a, 0b00000011, a);
1973        let e = _mm_set_pd(0., 1.);
1974        assert_eq_m128d(r, e);
1975    }
1976
1977    #[simd_test(enable = "avx512f,avx512vl")]
1978    unsafe fn test_mm_maskz_sqrt_pd() {
1979        let a = _mm_set_pd(0., 1.);
1980        let r = _mm_maskz_sqrt_pd(0, a);
1981        assert_eq_m128d(r, _mm_setzero_pd());
1982        let r = _mm_maskz_sqrt_pd(0b00000011, a);
1983        let e = _mm_set_pd(0., 1.);
1984        assert_eq_m128d(r, e);
1985    }
1986
1987    #[simd_test(enable = "avx512f")]
1988    unsafe fn test_mm512_fmadd_pd() {
1989        let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
1990        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1991        let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
1992        let r = _mm512_fmadd_pd(a, b, c);
1993        let e = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
1994        assert_eq_m512d(r, e);
1995    }
1996
1997    #[simd_test(enable = "avx512f")]
1998    unsafe fn test_mm512_mask_fmadd_pd() {
1999        let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
2000        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2001        let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
2002        let r = _mm512_mask_fmadd_pd(a, 0, b, c);
2003        assert_eq_m512d(r, a);
2004        let r = _mm512_mask_fmadd_pd(a, 0b00001111, b, c);
2005        let e = _mm512_setr_pd(1., 2., 3., 4., 1., 1., 1., 1.);
2006        assert_eq_m512d(r, e);
2007    }
2008
2009    #[simd_test(enable = "avx512f")]
2010    unsafe fn test_mm512_maskz_fmadd_pd() {
2011        let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
2012        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2013        let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
2014        let r = _mm512_maskz_fmadd_pd(0, a, b, c);
2015        assert_eq_m512d(r, _mm512_setzero_pd());
2016        let r = _mm512_maskz_fmadd_pd(0b00001111, a, b, c);
2017        let e = _mm512_setr_pd(1., 2., 3., 4., 0., 0., 0., 0.);
2018        assert_eq_m512d(r, e);
2019    }
2020
2021    #[simd_test(enable = "avx512f")]
2022    unsafe fn test_mm512_mask3_fmadd_pd() {
2023        let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
2024        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2025        let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2026        let r = _mm512_mask3_fmadd_pd(a, b, c, 0);
2027        assert_eq_m512d(r, c);
2028        let r = _mm512_mask3_fmadd_pd(a, b, c, 0b00001111);
2029        let e = _mm512_setr_pd(1., 2., 3., 4., 2., 2., 2., 2.);
2030        assert_eq_m512d(r, e);
2031    }
2032
2033    #[simd_test(enable = "avx512f,avx512vl")]
2034    unsafe fn test_mm256_mask_fmadd_pd() {
2035        let a = _mm256_set1_pd(1.);
2036        let b = _mm256_set_pd(0., 1., 2., 3.);
2037        let c = _mm256_set1_pd(1.);
2038        let r = _mm256_mask_fmadd_pd(a, 0, b, c);
2039        assert_eq_m256d(r, a);
2040        let r = _mm256_mask_fmadd_pd(a, 0b00001111, b, c);
2041        let e = _mm256_set_pd(1., 2., 3., 4.);
2042        assert_eq_m256d(r, e);
2043    }
2044
2045    #[simd_test(enable = "avx512f,avx512vl")]
2046    unsafe fn test_mm256_maskz_fmadd_pd() {
2047        let a = _mm256_set1_pd(1.);
2048        let b = _mm256_set_pd(0., 1., 2., 3.);
2049        let c = _mm256_set1_pd(1.);
2050        let r = _mm256_maskz_fmadd_pd(0, a, b, c);
2051        assert_eq_m256d(r, _mm256_setzero_pd());
2052        let r = _mm256_maskz_fmadd_pd(0b00001111, a, b, c);
2053        let e = _mm256_set_pd(1., 2., 3., 4.);
2054        assert_eq_m256d(r, e);
2055    }
2056
2057    #[simd_test(enable = "avx512f,avx512vl")]
2058    unsafe fn test_mm256_mask3_fmadd_pd() {
2059        let a = _mm256_set1_pd(1.);
2060        let b = _mm256_set_pd(0., 1., 2., 3.);
2061        let c = _mm256_set1_pd(1.);
2062        let r = _mm256_mask3_fmadd_pd(a, b, c, 0);
2063        assert_eq_m256d(r, c);
2064        let r = _mm256_mask3_fmadd_pd(a, b, c, 0b00001111);
2065        let e = _mm256_set_pd(1., 2., 3., 4.);
2066        assert_eq_m256d(r, e);
2067    }
2068
2069    #[simd_test(enable = "avx512f,avx512vl")]
2070    unsafe fn test_mm_mask_fmadd_pd() {
2071        let a = _mm_set1_pd(1.);
2072        let b = _mm_set_pd(0., 1.);
2073        let c = _mm_set1_pd(1.);
2074        let r = _mm_mask_fmadd_pd(a, 0, b, c);
2075        assert_eq_m128d(r, a);
2076        let r = _mm_mask_fmadd_pd(a, 0b00000011, b, c);
2077        let e = _mm_set_pd(1., 2.);
2078        assert_eq_m128d(r, e);
2079    }
2080
2081    #[simd_test(enable = "avx512f,avx512vl")]
2082    unsafe fn test_mm_maskz_fmadd_pd() {
2083        let a = _mm_set1_pd(1.);
2084        let b = _mm_set_pd(0., 1.);
2085        let c = _mm_set1_pd(1.);
2086        let r = _mm_maskz_fmadd_pd(0, a, b, c);
2087        assert_eq_m128d(r, _mm_setzero_pd());
2088        let r = _mm_maskz_fmadd_pd(0b00000011, a, b, c);
2089        let e = _mm_set_pd(1., 2.);
2090        assert_eq_m128d(r, e);
2091    }
2092
2093    #[simd_test(enable = "avx512f,avx512vl")]
2094    unsafe fn test_mm_mask3_fmadd_pd() {
2095        let a = _mm_set1_pd(1.);
2096        let b = _mm_set_pd(0., 1.);
2097        let c = _mm_set1_pd(1.);
2098        let r = _mm_mask3_fmadd_pd(a, b, c, 0);
2099        assert_eq_m128d(r, c);
2100        let r = _mm_mask3_fmadd_pd(a, b, c, 0b00000011);
2101        let e = _mm_set_pd(1., 2.);
2102        assert_eq_m128d(r, e);
2103    }
2104
2105    #[simd_test(enable = "avx512f")]
2106    unsafe fn test_mm512_fmsub_pd() {
2107        let a = _mm512_set1_pd(1.);
2108        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2109        let c = _mm512_set1_pd(1.);
2110        let r = _mm512_fmsub_pd(a, b, c);
2111        let e = _mm512_setr_pd(-1., 0., 1., 2., 3., 4., 5., 6.);
2112        assert_eq_m512d(r, e);
2113    }
2114
2115    #[simd_test(enable = "avx512f")]
2116    unsafe fn test_mm512_mask_fmsub_pd() {
2117        let a = _mm512_set1_pd(1.);
2118        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2119        let c = _mm512_set1_pd(1.);
2120        let r = _mm512_mask_fmsub_pd(a, 0, b, c);
2121        assert_eq_m512d(r, a);
2122        let r = _mm512_mask_fmsub_pd(a, 0b00001111, b, c);
2123        let e = _mm512_setr_pd(-1., 0., 1., 2., 1., 1., 1., 1.);
2124        assert_eq_m512d(r, e);
2125    }
2126
2127    #[simd_test(enable = "avx512f")]
2128    unsafe fn test_mm512_maskz_fmsub_pd() {
2129        let a = _mm512_set1_pd(1.);
2130        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2131        let c = _mm512_set1_pd(1.);
2132        let r = _mm512_maskz_fmsub_pd(0, a, b, c);
2133        assert_eq_m512d(r, _mm512_setzero_pd());
2134        let r = _mm512_maskz_fmsub_pd(0b00001111, a, b, c);
2135        let e = _mm512_setr_pd(-1., 0., 1., 2., 0., 0., 0., 0.);
2136        assert_eq_m512d(r, e);
2137    }
2138
2139    #[simd_test(enable = "avx512f")]
2140    unsafe fn test_mm512_mask3_fmsub_pd() {
2141        let a = _mm512_set1_pd(1.);
2142        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2143        let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2144        let r = _mm512_mask3_fmsub_pd(a, b, c, 0);
2145        assert_eq_m512d(r, c);
2146        let r = _mm512_mask3_fmsub_pd(a, b, c, 0b00001111);
2147        let e = _mm512_setr_pd(-1., 0., 1., 2., 2., 2., 2., 2.);
2148        assert_eq_m512d(r, e);
2149    }
2150
2151    #[simd_test(enable = "avx512f,avx512vl")]
2152    unsafe fn test_mm256_mask_fmsub_pd() {
2153        let a = _mm256_set1_pd(1.);
2154        let b = _mm256_set_pd(0., 1., 2., 3.);
2155        let c = _mm256_set1_pd(1.);
2156        let r = _mm256_mask_fmsub_pd(a, 0, b, c);
2157        assert_eq_m256d(r, a);
2158        let r = _mm256_mask_fmsub_pd(a, 0b00001111, b, c);
2159        let e = _mm256_set_pd(-1., 0., 1., 2.);
2160        assert_eq_m256d(r, e);
2161    }
2162
2163    #[simd_test(enable = "avx512f,avx512vl")]
2164    unsafe fn test_mm256_maskz_fmsub_pd() {
2165        let a = _mm256_set1_pd(1.);
2166        let b = _mm256_set_pd(0., 1., 2., 3.);
2167        let c = _mm256_set1_pd(1.);
2168        let r = _mm256_maskz_fmsub_pd(0, a, b, c);
2169        assert_eq_m256d(r, _mm256_setzero_pd());
2170        let r = _mm256_maskz_fmsub_pd(0b00001111, a, b, c);
2171        let e = _mm256_set_pd(-1., 0., 1., 2.);
2172        assert_eq_m256d(r, e);
2173    }
2174
2175    #[simd_test(enable = "avx512f,avx512vl")]
2176    unsafe fn test_mm256_mask3_fmsub_pd() {
2177        let a = _mm256_set1_pd(1.);
2178        let b = _mm256_set_pd(0., 1., 2., 3.);
2179        let c = _mm256_set1_pd(1.);
2180        let r = _mm256_mask3_fmsub_pd(a, b, c, 0);
2181        assert_eq_m256d(r, c);
2182        let r = _mm256_mask3_fmsub_pd(a, b, c, 0b00001111);
2183        let e = _mm256_set_pd(-1., 0., 1., 2.);
2184        assert_eq_m256d(r, e);
2185    }
2186
2187    #[simd_test(enable = "avx512f,avx512vl")]
2188    unsafe fn test_mm_mask_fmsub_pd() {
2189        let a = _mm_set1_pd(1.);
2190        let b = _mm_set_pd(0., 1.);
2191        let c = _mm_set1_pd(1.);
2192        let r = _mm_mask_fmsub_pd(a, 0, b, c);
2193        assert_eq_m128d(r, a);
2194        let r = _mm_mask_fmsub_pd(a, 0b00000011, b, c);
2195        let e = _mm_set_pd(-1., 0.);
2196        assert_eq_m128d(r, e);
2197    }
2198
2199    #[simd_test(enable = "avx512f,avx512vl")]
2200    unsafe fn test_mm_maskz_fmsub_pd() {
2201        let a = _mm_set1_pd(1.);
2202        let b = _mm_set_pd(0., 1.);
2203        let c = _mm_set1_pd(1.);
2204        let r = _mm_maskz_fmsub_pd(0, a, b, c);
2205        assert_eq_m128d(r, _mm_setzero_pd());
2206        let r = _mm_maskz_fmsub_pd(0b00000011, a, b, c);
2207        let e = _mm_set_pd(-1., 0.);
2208        assert_eq_m128d(r, e);
2209    }
2210
2211    #[simd_test(enable = "avx512f,avx512vl")]
2212    unsafe fn test_mm_mask3_fmsub_pd() {
2213        let a = _mm_set1_pd(1.);
2214        let b = _mm_set_pd(0., 1.);
2215        let c = _mm_set1_pd(1.);
2216        let r = _mm_mask3_fmsub_pd(a, b, c, 0);
2217        assert_eq_m128d(r, c);
2218        let r = _mm_mask3_fmsub_pd(a, b, c, 0b00000011);
2219        let e = _mm_set_pd(-1., 0.);
2220        assert_eq_m128d(r, e);
2221    }
2222
2223    #[simd_test(enable = "avx512f")]
2224    unsafe fn test_mm512_fmaddsub_pd() {
2225        let a = _mm512_set1_pd(1.);
2226        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2227        let c = _mm512_set1_pd(1.);
2228        let r = _mm512_fmaddsub_pd(a, b, c);
2229        let e = _mm512_setr_pd(-1., 2., 1., 4., 3., 6., 5., 8.);
2230        assert_eq_m512d(r, e);
2231    }
2232
2233    #[simd_test(enable = "avx512f")]
2234    unsafe fn test_mm512_mask_fmaddsub_pd() {
2235        let a = _mm512_set1_pd(1.);
2236        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2237        let c = _mm512_set1_pd(1.);
2238        let r = _mm512_mask_fmaddsub_pd(a, 0, b, c);
2239        assert_eq_m512d(r, a);
2240        let r = _mm512_mask_fmaddsub_pd(a, 0b00001111, b, c);
2241        let e = _mm512_setr_pd(-1., 2., 1., 4., 1., 1., 1., 1.);
2242        assert_eq_m512d(r, e);
2243    }
2244
2245    #[simd_test(enable = "avx512f")]
2246    unsafe fn test_mm512_maskz_fmaddsub_pd() {
2247        let a = _mm512_set1_pd(1.);
2248        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2249        let c = _mm512_set1_pd(1.);
2250        let r = _mm512_maskz_fmaddsub_pd(0, a, b, c);
2251        assert_eq_m512d(r, _mm512_setzero_pd());
2252        let r = _mm512_maskz_fmaddsub_pd(0b00001111, a, b, c);
2253        let e = _mm512_setr_pd(-1., 2., 1., 4., 0., 0., 0., 0.);
2254        assert_eq_m512d(r, e);
2255    }
2256
2257    #[simd_test(enable = "avx512f")]
2258    unsafe fn test_mm512_mask3_fmaddsub_pd() {
2259        let a = _mm512_set1_pd(1.);
2260        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2261        let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2262        let r = _mm512_mask3_fmaddsub_pd(a, b, c, 0);
2263        assert_eq_m512d(r, c);
2264        let r = _mm512_mask3_fmaddsub_pd(a, b, c, 0b00001111);
2265        let e = _mm512_setr_pd(-1., 2., 1., 4., 2., 2., 2., 2.);
2266        assert_eq_m512d(r, e);
2267    }
2268
2269    #[simd_test(enable = "avx512f,avx512vl")]
2270    unsafe fn test_mm256_mask_fmaddsub_pd() {
2271        let a = _mm256_set1_pd(1.);
2272        let b = _mm256_set_pd(0., 1., 2., 3.);
2273        let c = _mm256_set1_pd(1.);
2274        let r = _mm256_mask_fmaddsub_pd(a, 0, b, c);
2275        assert_eq_m256d(r, a);
2276        let r = _mm256_mask_fmaddsub_pd(a, 0b00001111, b, c);
2277        let e = _mm256_set_pd(1., 0., 3., 2.);
2278        assert_eq_m256d(r, e);
2279    }
2280
2281    #[simd_test(enable = "avx512f,avx512vl")]
2282    unsafe fn test_mm256_maskz_fmaddsub_pd() {
2283        let a = _mm256_set1_pd(1.);
2284        let b = _mm256_set_pd(0., 1., 2., 3.);
2285        let c = _mm256_set1_pd(1.);
2286        let r = _mm256_maskz_fmaddsub_pd(0, a, b, c);
2287        assert_eq_m256d(r, _mm256_setzero_pd());
2288        let r = _mm256_maskz_fmaddsub_pd(0b00001111, a, b, c);
2289        let e = _mm256_set_pd(1., 0., 3., 2.);
2290        assert_eq_m256d(r, e);
2291    }
2292
2293    #[simd_test(enable = "avx512f,avx512vl")]
2294    unsafe fn test_mm256_mask3_fmaddsub_pd() {
2295        let a = _mm256_set1_pd(1.);
2296        let b = _mm256_set_pd(0., 1., 2., 3.);
2297        let c = _mm256_set1_pd(1.);
2298        let r = _mm256_mask3_fmaddsub_pd(a, b, c, 0);
2299        assert_eq_m256d(r, c);
2300        let r = _mm256_mask3_fmaddsub_pd(a, b, c, 0b00001111);
2301        let e = _mm256_set_pd(1., 0., 3., 2.);
2302        assert_eq_m256d(r, e);
2303    }
2304
2305    #[simd_test(enable = "avx512f,avx512vl")]
2306    unsafe fn test_mm_mask_fmaddsub_pd() {
2307        let a = _mm_set1_pd(1.);
2308        let b = _mm_set_pd(0., 1.);
2309        let c = _mm_set1_pd(1.);
2310        let r = _mm_mask_fmaddsub_pd(a, 0, b, c);
2311        assert_eq_m128d(r, a);
2312        let r = _mm_mask_fmaddsub_pd(a, 0b00000011, b, c);
2313        let e = _mm_set_pd(1., 0.);
2314        assert_eq_m128d(r, e);
2315    }
2316
2317    #[simd_test(enable = "avx512f,avx512vl")]
2318    unsafe fn test_mm_maskz_fmaddsub_pd() {
2319        let a = _mm_set1_pd(1.);
2320        let b = _mm_set_pd(0., 1.);
2321        let c = _mm_set1_pd(1.);
2322        let r = _mm_maskz_fmaddsub_pd(0, a, b, c);
2323        assert_eq_m128d(r, _mm_setzero_pd());
2324        let r = _mm_maskz_fmaddsub_pd(0b00000011, a, b, c);
2325        let e = _mm_set_pd(1., 0.);
2326        assert_eq_m128d(r, e);
2327    }
2328
2329    #[simd_test(enable = "avx512f,avx512vl")]
2330    unsafe fn test_mm_mask3_fmaddsub_pd() {
2331        let a = _mm_set1_pd(1.);
2332        let b = _mm_set_pd(0., 1.);
2333        let c = _mm_set1_pd(1.);
2334        let r = _mm_mask3_fmaddsub_pd(a, b, c, 0);
2335        assert_eq_m128d(r, c);
2336        let r = _mm_mask3_fmaddsub_pd(a, b, c, 0b00000011);
2337        let e = _mm_set_pd(1., 0.);
2338        assert_eq_m128d(r, e);
2339    }
2340
2341    #[simd_test(enable = "avx512f")]
2342    unsafe fn test_mm512_fmsubadd_pd() {
2343        let a = _mm512_set1_pd(1.);
2344        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2345        let c = _mm512_set1_pd(1.);
2346        let r = _mm512_fmsubadd_pd(a, b, c);
2347        let e = _mm512_setr_pd(1., 0., 3., 2., 5., 4., 7., 6.);
2348        assert_eq_m512d(r, e);
2349    }
2350
2351    #[simd_test(enable = "avx512f")]
2352    unsafe fn test_mm512_mask_fmsubadd_pd() {
2353        let a = _mm512_set1_pd(1.);
2354        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2355        let c = _mm512_set1_pd(1.);
2356        let r = _mm512_mask_fmsubadd_pd(a, 0, b, c);
2357        assert_eq_m512d(r, a);
2358        let r = _mm512_mask_fmsubadd_pd(a, 0b00001111, b, c);
2359        let e = _mm512_setr_pd(1., 0., 3., 2., 1., 1., 1., 1.);
2360        assert_eq_m512d(r, e);
2361    }
2362
2363    #[simd_test(enable = "avx512f")]
2364    unsafe fn test_mm512_maskz_fmsubadd_pd() {
2365        let a = _mm512_set1_pd(1.);
2366        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2367        let c = _mm512_set1_pd(1.);
2368        let r = _mm512_maskz_fmsubadd_pd(0, a, b, c);
2369        assert_eq_m512d(r, _mm512_setzero_pd());
2370        let r = _mm512_maskz_fmsubadd_pd(0b00001111, a, b, c);
2371        let e = _mm512_setr_pd(1., 0., 3., 2., 0., 0., 0., 0.);
2372        assert_eq_m512d(r, e);
2373    }
2374
2375    #[simd_test(enable = "avx512f")]
2376    unsafe fn test_mm512_mask3_fmsubadd_pd() {
2377        let a = _mm512_set1_pd(1.);
2378        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2379        let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2380        let r = _mm512_mask3_fmsubadd_pd(a, b, c, 0);
2381        assert_eq_m512d(r, c);
2382        let r = _mm512_mask3_fmsubadd_pd(a, b, c, 0b00001111);
2383        let e = _mm512_setr_pd(1., 0., 3., 2., 2., 2., 2., 2.);
2384        assert_eq_m512d(r, e);
2385    }
2386
2387    #[simd_test(enable = "avx512f,avx512vl")]
2388    unsafe fn test_mm256_mask_fmsubadd_pd() {
2389        let a = _mm256_set1_pd(1.);
2390        let b = _mm256_set_pd(0., 1., 2., 3.);
2391        let c = _mm256_set1_pd(1.);
2392        let r = _mm256_mask_fmsubadd_pd(a, 0, b, c);
2393        assert_eq_m256d(r, a);
2394        let r = _mm256_mask_fmsubadd_pd(a, 0b00001111, b, c);
2395        let e = _mm256_set_pd(-1., 2., 1., 4.);
2396        assert_eq_m256d(r, e);
2397    }
2398
2399    #[simd_test(enable = "avx512f,avx512vl")]
2400    unsafe fn test_mm256_maskz_fmsubadd_pd() {
2401        let a = _mm256_set1_pd(1.);
2402        let b = _mm256_set_pd(0., 1., 2., 3.);
2403        let c = _mm256_set1_pd(1.);
2404        let r = _mm256_maskz_fmsubadd_pd(0, a, b, c);
2405        assert_eq_m256d(r, _mm256_setzero_pd());
2406        let r = _mm256_maskz_fmsubadd_pd(0b00001111, a, b, c);
2407        let e = _mm256_set_pd(-1., 2., 1., 4.);
2408        assert_eq_m256d(r, e);
2409    }
2410
2411    #[simd_test(enable = "avx512f,avx512vl")]
2412    unsafe fn test_mm256_mask3_fmsubadd_pd() {
2413        let a = _mm256_set1_pd(1.);
2414        let b = _mm256_set_pd(0., 1., 2., 3.);
2415        let c = _mm256_set1_pd(1.);
2416        let r = _mm256_mask3_fmsubadd_pd(a, b, c, 0);
2417        assert_eq_m256d(r, c);
2418        let r = _mm256_mask3_fmsubadd_pd(a, b, c, 0b00001111);
2419        let e = _mm256_set_pd(-1., 2., 1., 4.);
2420        assert_eq_m256d(r, e);
2421    }
2422
2423    #[simd_test(enable = "avx512f,avx512vl")]
2424    unsafe fn test_mm_mask_fmsubadd_pd() {
2425        let a = _mm_set1_pd(1.);
2426        let b = _mm_set_pd(0., 1.);
2427        let c = _mm_set1_pd(1.);
2428        let r = _mm_mask_fmsubadd_pd(a, 0, b, c);
2429        assert_eq_m128d(r, a);
2430        let r = _mm_mask_fmsubadd_pd(a, 0b00000011, b, c);
2431        let e = _mm_set_pd(-1., 2.);
2432        assert_eq_m128d(r, e);
2433    }
2434
2435    #[simd_test(enable = "avx512f,avx512vl")]
2436    unsafe fn test_mm_maskz_fmsubadd_pd() {
2437        let a = _mm_set1_pd(1.);
2438        let b = _mm_set_pd(0., 1.);
2439        let c = _mm_set1_pd(1.);
2440        let r = _mm_maskz_fmsubadd_pd(0, a, b, c);
2441        assert_eq_m128d(r, _mm_setzero_pd());
2442        let r = _mm_maskz_fmsubadd_pd(0b00000011, a, b, c);
2443        let e = _mm_set_pd(-1., 2.);
2444        assert_eq_m128d(r, e);
2445    }
2446
2447    #[simd_test(enable = "avx512f,avx512vl")]
2448    unsafe fn test_mm_mask3_fmsubadd_pd() {
2449        let a = _mm_set1_pd(1.);
2450        let b = _mm_set_pd(0., 1.);
2451        let c = _mm_set1_pd(1.);
2452        let r = _mm_mask3_fmsubadd_pd(a, b, c, 0);
2453        assert_eq_m128d(r, c);
2454        let r = _mm_mask3_fmsubadd_pd(a, b, c, 0b00000011);
2455        let e = _mm_set_pd(-1., 2.);
2456        assert_eq_m128d(r, e);
2457    }
2458
2459    #[simd_test(enable = "avx512f")]
2460    unsafe fn test_mm512_fnmadd_pd() {
2461        let a = _mm512_set1_pd(1.);
2462        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2463        let c = _mm512_set1_pd(1.);
2464        let r = _mm512_fnmadd_pd(a, b, c);
2465        let e = _mm512_setr_pd(1., 0., -1., -2., -3., -4., -5., -6.);
2466        assert_eq_m512d(r, e);
2467    }
2468
2469    #[simd_test(enable = "avx512f")]
2470    unsafe fn test_mm512_mask_fnmadd_pd() {
2471        let a = _mm512_set1_pd(1.);
2472        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2473        let c = _mm512_set1_pd(1.);
2474        let r = _mm512_mask_fnmadd_pd(a, 0, b, c);
2475        assert_eq_m512d(r, a);
2476        let r = _mm512_mask_fnmadd_pd(a, 0b00001111, b, c);
2477        let e = _mm512_setr_pd(1., 0., -1., -2., 1., 1., 1., 1.);
2478        assert_eq_m512d(r, e);
2479    }
2480
2481    #[simd_test(enable = "avx512f")]
2482    unsafe fn test_mm512_maskz_fnmadd_pd() {
2483        let a = _mm512_set1_pd(1.);
2484        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2485        let c = _mm512_set1_pd(1.);
2486        let r = _mm512_maskz_fnmadd_pd(0, a, b, c);
2487        assert_eq_m512d(r, _mm512_setzero_pd());
2488        let r = _mm512_maskz_fnmadd_pd(0b00001111, a, b, c);
2489        let e = _mm512_setr_pd(1., 0., -1., -2., 0., 0., 0., 0.);
2490        assert_eq_m512d(r, e);
2491    }
2492
2493    #[simd_test(enable = "avx512f")]
2494    unsafe fn test_mm512_mask3_fnmadd_pd() {
2495        let a = _mm512_set1_pd(1.);
2496        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2497        let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2498        let r = _mm512_mask3_fnmadd_pd(a, b, c, 0);
2499        assert_eq_m512d(r, c);
2500        let r = _mm512_mask3_fnmadd_pd(a, b, c, 0b00001111);
2501        let e = _mm512_setr_pd(1., 0., -1., -2., 2., 2., 2., 2.);
2502        assert_eq_m512d(r, e);
2503    }
2504
2505    #[simd_test(enable = "avx512f,avx512vl")]
2506    unsafe fn test_mm256_mask_fnmadd_pd() {
2507        let a = _mm256_set1_pd(1.);
2508        let b = _mm256_set_pd(0., 1., 2., 3.);
2509        let c = _mm256_set1_pd(1.);
2510        let r = _mm256_mask_fnmadd_pd(a, 0, b, c);
2511        assert_eq_m256d(r, a);
2512        let r = _mm256_mask_fnmadd_pd(a, 0b00001111, b, c);
2513        let e = _mm256_set_pd(1., 0., -1., -2.);
2514        assert_eq_m256d(r, e);
2515    }
2516
2517    #[simd_test(enable = "avx512f,avx512vl")]
2518    unsafe fn test_mm256_maskz_fnmadd_pd() {
2519        let a = _mm256_set1_pd(1.);
2520        let b = _mm256_set_pd(0., 1., 2., 3.);
2521        let c = _mm256_set1_pd(1.);
2522        let r = _mm256_maskz_fnmadd_pd(0, a, b, c);
2523        assert_eq_m256d(r, _mm256_setzero_pd());
2524        let r = _mm256_maskz_fnmadd_pd(0b00001111, a, b, c);
2525        let e = _mm256_set_pd(1., 0., -1., -2.);
2526        assert_eq_m256d(r, e);
2527    }
2528
2529    #[simd_test(enable = "avx512f,avx512vl")]
2530    unsafe fn test_mm256_mask3_fnmadd_pd() {
2531        let a = _mm256_set1_pd(1.);
2532        let b = _mm256_set_pd(0., 1., 2., 3.);
2533        let c = _mm256_set1_pd(1.);
2534        let r = _mm256_mask3_fnmadd_pd(a, b, c, 0);
2535        assert_eq_m256d(r, c);
2536        let r = _mm256_mask3_fnmadd_pd(a, b, c, 0b00001111);
2537        let e = _mm256_set_pd(1., 0., -1., -2.);
2538        assert_eq_m256d(r, e);
2539    }
2540
2541    #[simd_test(enable = "avx512f,avx512vl")]
2542    unsafe fn test_mm_mask_fnmadd_pd() {
2543        let a = _mm_set1_pd(1.);
2544        let b = _mm_set_pd(0., 1.);
2545        let c = _mm_set1_pd(1.);
2546        let r = _mm_mask_fnmadd_pd(a, 0, b, c);
2547        assert_eq_m128d(r, a);
2548        let r = _mm_mask_fnmadd_pd(a, 0b00000011, b, c);
2549        let e = _mm_set_pd(1., 0.);
2550        assert_eq_m128d(r, e);
2551    }
2552
2553    #[simd_test(enable = "avx512f,avx512vl")]
2554    unsafe fn test_mm_maskz_fnmadd_pd() {
2555        let a = _mm_set1_pd(1.);
2556        let b = _mm_set_pd(0., 1.);
2557        let c = _mm_set1_pd(1.);
2558        let r = _mm_maskz_fnmadd_pd(0, a, b, c);
2559        assert_eq_m128d(r, _mm_setzero_pd());
2560        let r = _mm_maskz_fnmadd_pd(0b00000011, a, b, c);
2561        let e = _mm_set_pd(1., 0.);
2562        assert_eq_m128d(r, e);
2563    }
2564
2565    #[simd_test(enable = "avx512f,avx512vl")]
2566    unsafe fn test_mm_mask3_fnmadd_pd() {
2567        let a = _mm_set1_pd(1.);
2568        let b = _mm_set_pd(0., 1.);
2569        let c = _mm_set1_pd(1.);
2570        let r = _mm_mask3_fnmadd_pd(a, b, c, 0);
2571        assert_eq_m128d(r, c);
2572        let r = _mm_mask3_fnmadd_pd(a, b, c, 0b00000011);
2573        let e = _mm_set_pd(1., 0.);
2574        assert_eq_m128d(r, e);
2575    }
2576
2577    #[simd_test(enable = "avx512f")]
2578    unsafe fn test_mm512_fnmsub_pd() {
2579        let a = _mm512_set1_pd(1.);
2580        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2581        let c = _mm512_set1_pd(1.);
2582        let r = _mm512_fnmsub_pd(a, b, c);
2583        let e = _mm512_setr_pd(-1., -2., -3., -4., -5., -6., -7., -8.);
2584        assert_eq_m512d(r, e);
2585    }
2586
2587    #[simd_test(enable = "avx512f")]
2588    unsafe fn test_mm512_mask_fnmsub_pd() {
2589        let a = _mm512_set1_pd(1.);
2590        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2591        let c = _mm512_set1_pd(1.);
2592        let r = _mm512_mask_fnmsub_pd(a, 0, b, c);
2593        assert_eq_m512d(r, a);
2594        let r = _mm512_mask_fnmsub_pd(a, 0b00001111, b, c);
2595        let e = _mm512_setr_pd(-1., -2., -3., -4., 1., 1., 1., 1.);
2596        assert_eq_m512d(r, e);
2597    }
2598
2599    #[simd_test(enable = "avx512f")]
2600    unsafe fn test_mm512_maskz_fnmsub_pd() {
2601        let a = _mm512_set1_pd(1.);
2602        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2603        let c = _mm512_set1_pd(1.);
2604        let r = _mm512_maskz_fnmsub_pd(0, a, b, c);
2605        assert_eq_m512d(r, _mm512_setzero_pd());
2606        let r = _mm512_maskz_fnmsub_pd(0b00001111, a, b, c);
2607        let e = _mm512_setr_pd(-1., -2., -3., -4., 0., 0., 0., 0.);
2608        assert_eq_m512d(r, e);
2609    }
2610
2611    #[simd_test(enable = "avx512f")]
2612    unsafe fn test_mm512_mask3_fnmsub_pd() {
2613        let a = _mm512_set1_pd(1.);
2614        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2615        let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2616        let r = _mm512_mask3_fnmsub_pd(a, b, c, 0);
2617        assert_eq_m512d(r, c);
2618        let r = _mm512_mask3_fnmsub_pd(a, b, c, 0b00001111);
2619        let e = _mm512_setr_pd(-1., -2., -3., -4., 2., 2., 2., 2.);
2620        assert_eq_m512d(r, e);
2621    }
2622
2623    #[simd_test(enable = "avx512f,avx512vl")]
2624    unsafe fn test_mm256_mask_fnmsub_pd() {
2625        let a = _mm256_set1_pd(1.);
2626        let b = _mm256_set_pd(0., 1., 2., 3.);
2627        let c = _mm256_set1_pd(1.);
2628        let r = _mm256_mask_fnmsub_pd(a, 0, b, c);
2629        assert_eq_m256d(r, a);
2630        let r = _mm256_mask_fnmsub_pd(a, 0b00001111, b, c);
2631        let e = _mm256_set_pd(-1., -2., -3., -4.);
2632        assert_eq_m256d(r, e);
2633    }
2634
2635    #[simd_test(enable = "avx512f,avx512vl")]
2636    unsafe fn test_mm256_maskz_fnmsub_pd() {
2637        let a = _mm256_set1_pd(1.);
2638        let b = _mm256_set_pd(0., 1., 2., 3.);
2639        let c = _mm256_set1_pd(1.);
2640        let r = _mm256_maskz_fnmsub_pd(0, a, b, c);
2641        assert_eq_m256d(r, _mm256_setzero_pd());
2642        let r = _mm256_maskz_fnmsub_pd(0b00001111, a, b, c);
2643        let e = _mm256_set_pd(-1., -2., -3., -4.);
2644        assert_eq_m256d(r, e);
2645    }
2646
2647    #[simd_test(enable = "avx512f,avx512vl")]
2648    unsafe fn test_mm256_mask3_fnmsub_pd() {
2649        let a = _mm256_set1_pd(1.);
2650        let b = _mm256_set_pd(0., 1., 2., 3.);
2651        let c = _mm256_set1_pd(1.);
2652        let r = _mm256_mask3_fnmsub_pd(a, b, c, 0);
2653        assert_eq_m256d(r, c);
2654        let r = _mm256_mask3_fnmsub_pd(a, b, c, 0b00001111);
2655        let e = _mm256_set_pd(-1., -2., -3., -4.);
2656        assert_eq_m256d(r, e);
2657    }
2658
2659    #[simd_test(enable = "avx512f,avx512vl")]
2660    unsafe fn test_mm_mask_fnmsub_pd() {
2661        let a = _mm_set1_pd(1.);
2662        let b = _mm_set_pd(0., 1.);
2663        let c = _mm_set1_pd(1.);
2664        let r = _mm_mask_fnmsub_pd(a, 0, b, c);
2665        assert_eq_m128d(r, a);
2666        let r = _mm_mask_fnmsub_pd(a, 0b00000011, b, c);
2667        let e = _mm_set_pd(-1., -2.);
2668        assert_eq_m128d(r, e);
2669    }
2670
2671    #[simd_test(enable = "avx512f,avx512vl")]
2672    unsafe fn test_mm_maskz_fnmsub_pd() {
2673        let a = _mm_set1_pd(1.);
2674        let b = _mm_set_pd(0., 1.);
2675        let c = _mm_set1_pd(1.);
2676        let r = _mm_maskz_fnmsub_pd(0, a, b, c);
2677        assert_eq_m128d(r, _mm_setzero_pd());
2678        let r = _mm_maskz_fnmsub_pd(0b00000011, a, b, c);
2679        let e = _mm_set_pd(-1., -2.);
2680        assert_eq_m128d(r, e);
2681    }
2682
2683    #[simd_test(enable = "avx512f,avx512vl")]
2684    unsafe fn test_mm_mask3_fnmsub_pd() {
2685        let a = _mm_set1_pd(1.);
2686        let b = _mm_set_pd(0., 1.);
2687        let c = _mm_set1_pd(1.);
2688        let r = _mm_mask3_fnmsub_pd(a, b, c, 0);
2689        assert_eq_m128d(r, c);
2690        let r = _mm_mask3_fnmsub_pd(a, b, c, 0b00000011);
2691        let e = _mm_set_pd(-1., -2.);
2692        assert_eq_m128d(r, e);
2693    }
2694
2695    #[simd_test(enable = "avx512f")]
2696    unsafe fn test_mm512_rcp14_pd() {
2697        let a = _mm512_set1_pd(3.);
2698        let r = _mm512_rcp14_pd(a);
2699        let e = _mm512_set1_pd(0.3333320617675781);
2700        assert_eq_m512d(r, e);
2701    }
2702
2703    #[simd_test(enable = "avx512f")]
2704    unsafe fn test_mm512_mask_rcp14_pd() {
2705        let a = _mm512_set1_pd(3.);
2706        let r = _mm512_mask_rcp14_pd(a, 0, a);
2707        assert_eq_m512d(r, a);
2708        let r = _mm512_mask_rcp14_pd(a, 0b11110000, a);
2709        #[rustfmt::skip]
2710        let e = _mm512_setr_pd(
2711            3., 3., 3., 3.,
2712            0.3333320617675781, 0.3333320617675781, 0.3333320617675781, 0.3333320617675781,
2713        );
2714        assert_eq_m512d(r, e);
2715    }
2716
2717    #[simd_test(enable = "avx512f")]
2718    unsafe fn test_mm512_maskz_rcp14_pd() {
2719        let a = _mm512_set1_pd(3.);
2720        let r = _mm512_maskz_rcp14_pd(0, a);
2721        assert_eq_m512d(r, _mm512_setzero_pd());
2722        let r = _mm512_maskz_rcp14_pd(0b11110000, a);
2723        #[rustfmt::skip]
2724        let e = _mm512_setr_pd(
2725            0., 0., 0., 0.,
2726            0.3333320617675781, 0.3333320617675781, 0.3333320617675781, 0.3333320617675781,
2727        );
2728        assert_eq_m512d(r, e);
2729    }
2730
2731    #[simd_test(enable = "avx512f,avx512vl")]
2732    unsafe fn test_mm256_rcp14_pd() {
2733        let a = _mm256_set1_pd(3.);
2734        let r = _mm256_rcp14_pd(a);
2735        let e = _mm256_set1_pd(0.3333320617675781);
2736        assert_eq_m256d(r, e);
2737    }
2738
2739    #[simd_test(enable = "avx512f,avx512vl")]
2740    unsafe fn test_mm256_mask_rcp14_pd() {
2741        let a = _mm256_set1_pd(3.);
2742        let r = _mm256_mask_rcp14_pd(a, 0, a);
2743        assert_eq_m256d(r, a);
2744        let r = _mm256_mask_rcp14_pd(a, 0b00001111, a);
2745        let e = _mm256_set1_pd(0.3333320617675781);
2746        assert_eq_m256d(r, e);
2747    }
2748
2749    #[simd_test(enable = "avx512f,avx512vl")]
2750    unsafe fn test_mm256_maskz_rcp14_pd() {
2751        let a = _mm256_set1_pd(3.);
2752        let r = _mm256_maskz_rcp14_pd(0, a);
2753        assert_eq_m256d(r, _mm256_setzero_pd());
2754        let r = _mm256_maskz_rcp14_pd(0b00001111, a);
2755        let e = _mm256_set1_pd(0.3333320617675781);
2756        assert_eq_m256d(r, e);
2757    }
2758
2759    #[simd_test(enable = "avx512f,avx512vl")]
2760    unsafe fn test_mm_rcp14_pd() {
2761        let a = _mm_set1_pd(3.);
2762        let r = _mm_rcp14_pd(a);
2763        let e = _mm_set1_pd(0.3333320617675781);
2764        assert_eq_m128d(r, e);
2765    }
2766
2767    #[simd_test(enable = "avx512f,avx512vl")]
2768    unsafe fn test_mm_mask_rcp14_pd() {
2769        let a = _mm_set1_pd(3.);
2770        let r = _mm_mask_rcp14_pd(a, 0, a);
2771        assert_eq_m128d(r, a);
2772        let r = _mm_mask_rcp14_pd(a, 0b00000011, a);
2773        let e = _mm_set1_pd(0.3333320617675781);
2774        assert_eq_m128d(r, e);
2775    }
2776
2777    #[simd_test(enable = "avx512f,avx512vl")]
2778    unsafe fn test_mm_maskz_rcp14_pd() {
2779        let a = _mm_set1_pd(3.);
2780        let r = _mm_maskz_rcp14_pd(0, a);
2781        assert_eq_m128d(r, _mm_setzero_pd());
2782        let r = _mm_maskz_rcp14_pd(0b00000011, a);
2783        let e = _mm_set1_pd(0.3333320617675781);
2784        assert_eq_m128d(r, e);
2785    }
2786
2787    #[simd_test(enable = "avx512f")]
2788    unsafe fn test_mm512_rsqrt14_pd() {
2789        let a = _mm512_set1_pd(3.);
2790        let r = _mm512_rsqrt14_pd(a);
2791        let e = _mm512_set1_pd(0.5773391723632813);
2792        assert_eq_m512d(r, e);
2793    }
2794
2795    #[simd_test(enable = "avx512f")]
2796    unsafe fn test_mm512_mask_rsqrt14_pd() {
2797        let a = _mm512_set1_pd(3.);
2798        let r = _mm512_mask_rsqrt14_pd(a, 0, a);
2799        assert_eq_m512d(r, a);
2800        let r = _mm512_mask_rsqrt14_pd(a, 0b11110000, a);
2801        #[rustfmt::skip]
2802        let e = _mm512_setr_pd(
2803            3., 3., 3., 3.,
2804            0.5773391723632813, 0.5773391723632813, 0.5773391723632813, 0.5773391723632813,
2805        );
2806        assert_eq_m512d(r, e);
2807    }
2808
2809    #[simd_test(enable = "avx512f")]
2810    unsafe fn test_mm512_maskz_rsqrt14_pd() {
2811        let a = _mm512_set1_pd(3.);
2812        let r = _mm512_maskz_rsqrt14_pd(0, a);
2813        assert_eq_m512d(r, _mm512_setzero_pd());
2814        let r = _mm512_maskz_rsqrt14_pd(0b11110000, a);
2815        #[rustfmt::skip]
2816        let e = _mm512_setr_pd(
2817            0., 0., 0., 0.,
2818            0.5773391723632813, 0.5773391723632813, 0.5773391723632813, 0.5773391723632813,
2819        );
2820        assert_eq_m512d(r, e);
2821    }
2822
2823    #[simd_test(enable = "avx512f,avx512vl")]
2824    unsafe fn test_mm256_rsqrt14_pd() {
2825        let a = _mm256_set1_pd(3.);
2826        let r = _mm256_rsqrt14_pd(a);
2827        let e = _mm256_set1_pd(0.5773391723632813);
2828        assert_eq_m256d(r, e);
2829    }
2830
2831    #[simd_test(enable = "avx512f,avx512vl")]
2832    unsafe fn test_mm256_mask_rsqrt14_pd() {
2833        let a = _mm256_set1_pd(3.);
2834        let r = _mm256_mask_rsqrt14_pd(a, 0, a);
2835        assert_eq_m256d(r, a);
2836        let r = _mm256_mask_rsqrt14_pd(a, 0b00001111, a);
2837        let e = _mm256_set1_pd(0.5773391723632813);
2838        assert_eq_m256d(r, e);
2839    }
2840
2841    #[simd_test(enable = "avx512f,avx512vl")]
2842    unsafe fn test_mm256_maskz_rsqrt14_pd() {
2843        let a = _mm256_set1_pd(3.);
2844        let r = _mm256_maskz_rsqrt14_pd(0, a);
2845        assert_eq_m256d(r, _mm256_setzero_pd());
2846        let r = _mm256_maskz_rsqrt14_pd(0b00001111, a);
2847        let e = _mm256_set1_pd(0.5773391723632813);
2848        assert_eq_m256d(r, e);
2849    }
2850
2851    #[simd_test(enable = "avx512f,avx512vl")]
2852    unsafe fn test_mm_rsqrt14_pd() {
2853        let a = _mm_set1_pd(3.);
2854        let r = _mm_rsqrt14_pd(a);
2855        let e = _mm_set1_pd(0.5773391723632813);
2856        assert_eq_m128d(r, e);
2857    }
2858
2859    #[simd_test(enable = "avx512f,avx512vl")]
2860    unsafe fn test_mm_mask_rsqrt14_pd() {
2861        let a = _mm_set1_pd(3.);
2862        let r = _mm_mask_rsqrt14_pd(a, 0, a);
2863        assert_eq_m128d(r, a);
2864        let r = _mm_mask_rsqrt14_pd(a, 0b00000011, a);
2865        let e = _mm_set1_pd(0.5773391723632813);
2866        assert_eq_m128d(r, e);
2867    }
2868
2869    #[simd_test(enable = "avx512f,avx512vl")]
2870    unsafe fn test_mm_maskz_rsqrt14_pd() {
2871        let a = _mm_set1_pd(3.);
2872        let r = _mm_maskz_rsqrt14_pd(0, a);
2873        assert_eq_m128d(r, _mm_setzero_pd());
2874        let r = _mm_maskz_rsqrt14_pd(0b00000011, a);
2875        let e = _mm_set1_pd(0.5773391723632813);
2876        assert_eq_m128d(r, e);
2877    }
2878
2879    #[simd_test(enable = "avx512f")]
2880    unsafe fn test_mm512_getexp_pd() {
2881        let a = _mm512_set1_pd(3.);
2882        let r = _mm512_getexp_pd(a);
2883        let e = _mm512_set1_pd(1.);
2884        assert_eq_m512d(r, e);
2885    }
2886
2887    #[simd_test(enable = "avx512f")]
2888    unsafe fn test_mm512_mask_getexp_pd() {
2889        let a = _mm512_set1_pd(3.);
2890        let r = _mm512_mask_getexp_pd(a, 0, a);
2891        assert_eq_m512d(r, a);
2892        let r = _mm512_mask_getexp_pd(a, 0b11110000, a);
2893        let e = _mm512_setr_pd(3., 3., 3., 3., 1., 1., 1., 1.);
2894        assert_eq_m512d(r, e);
2895    }
2896
2897    #[simd_test(enable = "avx512f")]
2898    unsafe fn test_mm512_maskz_getexp_pd() {
2899        let a = _mm512_set1_pd(3.);
2900        let r = _mm512_maskz_getexp_pd(0, a);
2901        assert_eq_m512d(r, _mm512_setzero_pd());
2902        let r = _mm512_maskz_getexp_pd(0b11110000, a);
2903        let e = _mm512_setr_pd(0., 0., 0., 0., 1., 1., 1., 1.);
2904        assert_eq_m512d(r, e);
2905    }
2906
2907    #[simd_test(enable = "avx512f,avx512vl")]
2908    unsafe fn test_mm256_getexp_pd() {
2909        let a = _mm256_set1_pd(3.);
2910        let r = _mm256_getexp_pd(a);
2911        let e = _mm256_set1_pd(1.);
2912        assert_eq_m256d(r, e);
2913    }
2914
2915    #[simd_test(enable = "avx512f,avx512vl")]
2916    unsafe fn test_mm256_mask_getexp_pd() {
2917        let a = _mm256_set1_pd(3.);
2918        let r = _mm256_mask_getexp_pd(a, 0, a);
2919        assert_eq_m256d(r, a);
2920        let r = _mm256_mask_getexp_pd(a, 0b00001111, a);
2921        let e = _mm256_set1_pd(1.);
2922        assert_eq_m256d(r, e);
2923    }
2924
2925    #[simd_test(enable = "avx512f,avx512vl")]
2926    unsafe fn test_mm256_maskz_getexp_pd() {
2927        let a = _mm256_set1_pd(3.);
2928        let r = _mm256_maskz_getexp_pd(0, a);
2929        assert_eq_m256d(r, _mm256_setzero_pd());
2930        let r = _mm256_maskz_getexp_pd(0b00001111, a);
2931        let e = _mm256_set1_pd(1.);
2932        assert_eq_m256d(r, e);
2933    }
2934
2935    #[simd_test(enable = "avx512f,avx512vl")]
2936    unsafe fn test_mm_getexp_pd() {
2937        let a = _mm_set1_pd(3.);
2938        let r = _mm_getexp_pd(a);
2939        let e = _mm_set1_pd(1.);
2940        assert_eq_m128d(r, e);
2941    }
2942
2943    #[simd_test(enable = "avx512f,avx512vl")]
2944    unsafe fn test_mm_mask_getexp_pd() {
2945        let a = _mm_set1_pd(3.);
2946        let r = _mm_mask_getexp_pd(a, 0, a);
2947        assert_eq_m128d(r, a);
2948        let r = _mm_mask_getexp_pd(a, 0b00000011, a);
2949        let e = _mm_set1_pd(1.);
2950        assert_eq_m128d(r, e);
2951    }
2952
2953    #[simd_test(enable = "avx512f,avx512vl")]
2954    unsafe fn test_mm_maskz_getexp_pd() {
2955        let a = _mm_set1_pd(3.);
2956        let r = _mm_maskz_getexp_pd(0, a);
2957        assert_eq_m128d(r, _mm_setzero_pd());
2958        let r = _mm_maskz_getexp_pd(0b00000011, a);
2959        let e = _mm_set1_pd(1.);
2960        assert_eq_m128d(r, e);
2961    }
2962
2963    #[simd_test(enable = "avx512f")]
2964    unsafe fn test_mm512_roundscale_pd() {
2965        let a = _mm512_set1_pd(1.1);
2966        let r = _mm512_roundscale_pd::<0b00_00_00_00>(a);
2967        let e = _mm512_set1_pd(1.0);
2968        assert_eq_m512d(r, e);
2969    }
2970
2971    #[simd_test(enable = "avx512f")]
2972    unsafe fn test_mm512_mask_roundscale_pd() {
2973        let a = _mm512_set1_pd(1.1);
2974        let r = _mm512_mask_roundscale_pd::<0b00_00_00_00>(a, 0, a);
2975        let e = _mm512_set1_pd(1.1);
2976        assert_eq_m512d(r, e);
2977        let r = _mm512_mask_roundscale_pd::<0b00_00_00_00>(a, 0b11111111, a);
2978        let e = _mm512_set1_pd(1.0);
2979        assert_eq_m512d(r, e);
2980    }
2981
2982    #[simd_test(enable = "avx512f")]
2983    unsafe fn test_mm512_maskz_roundscale_pd() {
2984        let a = _mm512_set1_pd(1.1);
2985        let r = _mm512_maskz_roundscale_pd::<0b00_00_00_00>(0, a);
2986        assert_eq_m512d(r, _mm512_setzero_pd());
2987        let r = _mm512_maskz_roundscale_pd::<0b00_00_00_00>(0b11111111, a);
2988        let e = _mm512_set1_pd(1.0);
2989        assert_eq_m512d(r, e);
2990    }
2991
2992    #[simd_test(enable = "avx512f,avx512vl")]
2993    unsafe fn test_mm256_roundscale_pd() {
2994        let a = _mm256_set1_pd(1.1);
2995        let r = _mm256_roundscale_pd::<0b00_00_00_00>(a);
2996        let e = _mm256_set1_pd(1.0);
2997        assert_eq_m256d(r, e);
2998    }
2999
3000    #[simd_test(enable = "avx512f,avx512vl")]
3001    unsafe fn test_mm256_mask_roundscale_pd() {
3002        let a = _mm256_set1_pd(1.1);
3003        let r = _mm256_mask_roundscale_pd::<0b00_00_00_00>(a, 0, a);
3004        assert_eq_m256d(r, a);
3005        let r = _mm256_mask_roundscale_pd::<0b00_00_00_00>(a, 0b00001111, a);
3006        let e = _mm256_set1_pd(1.0);
3007        assert_eq_m256d(r, e);
3008    }
3009
3010    #[simd_test(enable = "avx512f,avx512vl")]
3011    unsafe fn test_mm256_maskz_roundscale_pd() {
3012        let a = _mm256_set1_pd(1.1);
3013        let r = _mm256_maskz_roundscale_pd::<0b00_00_00_00>(0, a);
3014        assert_eq_m256d(r, _mm256_setzero_pd());
3015        let r = _mm256_maskz_roundscale_pd::<0b00_00_00_00>(0b00001111, a);
3016        let e = _mm256_set1_pd(1.0);
3017        assert_eq_m256d(r, e);
3018    }
3019
3020    #[simd_test(enable = "avx512f,avx512vl")]
3021    unsafe fn test_mm_roundscale_pd() {
3022        let a = _mm_set1_pd(1.1);
3023        let r = _mm_roundscale_pd::<0b00_00_00_00>(a);
3024        let e = _mm_set1_pd(1.0);
3025        assert_eq_m128d(r, e);
3026    }
3027
3028    #[simd_test(enable = "avx512f,avx512vl")]
3029    unsafe fn test_mm_mask_roundscale_pd() {
3030        let a = _mm_set1_pd(1.1);
3031        let r = _mm_mask_roundscale_pd::<0b00_00_00_00>(a, 0, a);
3032        let e = _mm_set1_pd(1.1);
3033        assert_eq_m128d(r, e);
3034        let r = _mm_mask_roundscale_pd::<0b00_00_00_00>(a, 0b00000011, a);
3035        let e = _mm_set1_pd(1.0);
3036        assert_eq_m128d(r, e);
3037    }
3038
3039    #[simd_test(enable = "avx512f,avx512vl")]
3040    unsafe fn test_mm_maskz_roundscale_pd() {
3041        let a = _mm_set1_pd(1.1);
3042        let r = _mm_maskz_roundscale_pd::<0b00_00_00_00>(0, a);
3043        assert_eq_m128d(r, _mm_setzero_pd());
3044        let r = _mm_maskz_roundscale_pd::<0b00_00_00_00>(0b00000011, a);
3045        let e = _mm_set1_pd(1.0);
3046        assert_eq_m128d(r, e);
3047    }
3048
3049    #[simd_test(enable = "avx512f")]
3050    unsafe fn test_mm512_scalef_pd() {
3051        let a = _mm512_set1_pd(1.);
3052        let b = _mm512_set1_pd(3.);
3053        let r = _mm512_scalef_pd(a, b);
3054        let e = _mm512_set1_pd(8.);
3055        assert_eq_m512d(r, e);
3056    }
3057
3058    #[simd_test(enable = "avx512f")]
3059    unsafe fn test_mm512_mask_scalef_pd() {
3060        let a = _mm512_set1_pd(1.);
3061        let b = _mm512_set1_pd(3.);
3062        let r = _mm512_mask_scalef_pd(a, 0, a, b);
3063        assert_eq_m512d(r, a);
3064        let r = _mm512_mask_scalef_pd(a, 0b11110000, a, b);
3065        let e = _mm512_set_pd(8., 8., 8., 8., 1., 1., 1., 1.);
3066        assert_eq_m512d(r, e);
3067    }
3068
3069    #[simd_test(enable = "avx512f")]
3070    unsafe fn test_mm512_maskz_scalef_pd() {
3071        let a = _mm512_set1_pd(1.);
3072        let b = _mm512_set1_pd(3.);
3073        let r = _mm512_maskz_scalef_pd(0, a, b);
3074        assert_eq_m512d(r, _mm512_setzero_pd());
3075        let r = _mm512_maskz_scalef_pd(0b11110000, a, b);
3076        let e = _mm512_set_pd(8., 8., 8., 8., 0., 0., 0., 0.);
3077        assert_eq_m512d(r, e);
3078    }
3079
3080    #[simd_test(enable = "avx512f,avx512vl")]
3081    unsafe fn test_mm256_scalef_pd() {
3082        let a = _mm256_set1_pd(1.);
3083        let b = _mm256_set1_pd(3.);
3084        let r = _mm256_scalef_pd(a, b);
3085        let e = _mm256_set1_pd(8.);
3086        assert_eq_m256d(r, e);
3087    }
3088
3089    #[simd_test(enable = "avx512f,avx512vl")]
3090    unsafe fn test_mm256_mask_scalef_pd() {
3091        let a = _mm256_set1_pd(1.);
3092        let b = _mm256_set1_pd(3.);
3093        let r = _mm256_mask_scalef_pd(a, 0, a, b);
3094        assert_eq_m256d(r, a);
3095        let r = _mm256_mask_scalef_pd(a, 0b00001111, a, b);
3096        let e = _mm256_set1_pd(8.);
3097        assert_eq_m256d(r, e);
3098    }
3099
3100    #[simd_test(enable = "avx512f,avx512vl")]
3101    unsafe fn test_mm256_maskz_scalef_pd() {
3102        let a = _mm256_set1_pd(1.);
3103        let b = _mm256_set1_pd(3.);
3104        let r = _mm256_maskz_scalef_pd(0, a, b);
3105        assert_eq_m256d(r, _mm256_setzero_pd());
3106        let r = _mm256_maskz_scalef_pd(0b00001111, a, b);
3107        let e = _mm256_set1_pd(8.);
3108        assert_eq_m256d(r, e);
3109    }
3110
3111    #[simd_test(enable = "avx512f,avx512vl")]
3112    unsafe fn test_mm_scalef_pd() {
3113        let a = _mm_set1_pd(1.);
3114        let b = _mm_set1_pd(3.);
3115        let r = _mm_scalef_pd(a, b);
3116        let e = _mm_set1_pd(8.);
3117        assert_eq_m128d(r, e);
3118    }
3119
3120    #[simd_test(enable = "avx512f,avx512vl")]
3121    unsafe fn test_mm_mask_scalef_pd() {
3122        let a = _mm_set1_pd(1.);
3123        let b = _mm_set1_pd(3.);
3124        let r = _mm_mask_scalef_pd(a, 0, a, b);
3125        assert_eq_m128d(r, a);
3126        let r = _mm_mask_scalef_pd(a, 0b00000011, a, b);
3127        let e = _mm_set1_pd(8.);
3128        assert_eq_m128d(r, e);
3129    }
3130
3131    #[simd_test(enable = "avx512f,avx512vl")]
3132    unsafe fn test_mm_maskz_scalef_pd() {
3133        let a = _mm_set1_pd(1.);
3134        let b = _mm_set1_pd(3.);
3135        let r = _mm_maskz_scalef_pd(0, a, b);
3136        assert_eq_m128d(r, _mm_setzero_pd());
3137        let r = _mm_maskz_scalef_pd(0b00000011, a, b);
3138        let e = _mm_set1_pd(8.);
3139        assert_eq_m128d(r, e);
3140    }
3141
3142    #[simd_test(enable = "avx512f")]
3143    unsafe fn test_mm512_fixupimm_pd() {
3144        let a = _mm512_set1_pd(f64::NAN);
3145        let b = _mm512_set1_pd(f64::MAX);
3146        let c = _mm512_set1_epi64(i32::MAX as i64);
3147        let r = _mm512_fixupimm_pd::<5>(a, b, c);
3148        let e = _mm512_set1_pd(0.0);
3149        assert_eq_m512d(r, e);
3150    }
3151
3152    #[simd_test(enable = "avx512f")]
3153    unsafe fn test_mm512_mask_fixupimm_pd() {
3154        let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.);
3155        let b = _mm512_set1_pd(f64::MAX);
3156        let c = _mm512_set1_epi64(i32::MAX as i64);
3157        let r = _mm512_mask_fixupimm_pd::<5>(a, 0b11110000, b, c);
3158        let e = _mm512_set_pd(0., 0., 0., 0., 1., 1., 1., 1.);
3159        assert_eq_m512d(r, e);
3160    }
3161
3162    #[simd_test(enable = "avx512f")]
3163    unsafe fn test_mm512_maskz_fixupimm_pd() {
3164        let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.);
3165        let b = _mm512_set1_pd(f64::MAX);
3166        let c = _mm512_set1_epi64(i32::MAX as i64);
3167        let r = _mm512_maskz_fixupimm_pd::<5>(0b11110000, a, b, c);
3168        let e = _mm512_set_pd(0., 0., 0., 0., 0., 0., 0., 0.);
3169        assert_eq_m512d(r, e);
3170    }
3171
3172    #[simd_test(enable = "avx512f,avx512vl")]
3173    unsafe fn test_mm256_fixupimm_pd() {
3174        let a = _mm256_set1_pd(f64::NAN);
3175        let b = _mm256_set1_pd(f64::MAX);
3176        let c = _mm256_set1_epi64x(i32::MAX as i64);
3177        let r = _mm256_fixupimm_pd::<5>(a, b, c);
3178        let e = _mm256_set1_pd(0.0);
3179        assert_eq_m256d(r, e);
3180    }
3181
3182    #[simd_test(enable = "avx512f,avx512vl")]
3183    unsafe fn test_mm256_mask_fixupimm_pd() {
3184        let a = _mm256_set1_pd(f64::NAN);
3185        let b = _mm256_set1_pd(f64::MAX);
3186        let c = _mm256_set1_epi64x(i32::MAX as i64);
3187        let r = _mm256_mask_fixupimm_pd::<5>(a, 0b00001111, b, c);
3188        let e = _mm256_set1_pd(0.0);
3189        assert_eq_m256d(r, e);
3190    }
3191
3192    #[simd_test(enable = "avx512f,avx512vl")]
3193    unsafe fn test_mm256_maskz_fixupimm_pd() {
3194        let a = _mm256_set1_pd(f64::NAN);
3195        let b = _mm256_set1_pd(f64::MAX);
3196        let c = _mm256_set1_epi64x(i32::MAX as i64);
3197        let r = _mm256_maskz_fixupimm_pd::<5>(0b00001111, a, b, c);
3198        let e = _mm256_set1_pd(0.0);
3199        assert_eq_m256d(r, e);
3200    }
3201
3202    #[simd_test(enable = "avx512f,avx512vl")]
3203    unsafe fn test_mm_fixupimm_pd() {
3204        let a = _mm_set1_pd(f64::NAN);
3205        let b = _mm_set1_pd(f64::MAX);
3206        let c = _mm_set1_epi64x(i32::MAX as i64);
3207        let r = _mm_fixupimm_pd::<5>(a, b, c);
3208        let e = _mm_set1_pd(0.0);
3209        assert_eq_m128d(r, e);
3210    }
3211
3212    #[simd_test(enable = "avx512f,avx512vl")]
3213    unsafe fn test_mm_mask_fixupimm_pd() {
3214        let a = _mm_set1_pd(f64::NAN);
3215        let b = _mm_set1_pd(f64::MAX);
3216        let c = _mm_set1_epi64x(i32::MAX as i64);
3217        let r = _mm_mask_fixupimm_pd::<5>(a, 0b00000011, b, c);
3218        let e = _mm_set1_pd(0.0);
3219        assert_eq_m128d(r, e);
3220    }
3221
3222    #[simd_test(enable = "avx512f,avx512vl")]
3223    unsafe fn test_mm_maskz_fixupimm_pd() {
3224        let a = _mm_set1_pd(f64::NAN);
3225        let b = _mm_set1_pd(f64::MAX);
3226        let c = _mm_set1_epi64x(i32::MAX as i64);
3227        let r = _mm_maskz_fixupimm_pd::<5>(0b00000011, a, b, c);
3228        let e = _mm_set1_pd(0.0);
3229        assert_eq_m128d(r, e);
3230    }
3231
3232    #[simd_test(enable = "avx512f")]
3233    unsafe fn test_mm512_ternarylogic_epi64() {
3234        let a = _mm512_set1_epi64(1 << 2);
3235        let b = _mm512_set1_epi64(1 << 1);
3236        let c = _mm512_set1_epi64(1 << 0);
3237        let r = _mm512_ternarylogic_epi64::<8>(a, b, c);
3238        let e = _mm512_set1_epi64(0);
3239        assert_eq_m512i(r, e);
3240    }
3241
3242    #[simd_test(enable = "avx512f")]
3243    unsafe fn test_mm512_mask_ternarylogic_epi64() {
3244        let src = _mm512_set1_epi64(1 << 2);
3245        let a = _mm512_set1_epi64(1 << 1);
3246        let b = _mm512_set1_epi64(1 << 0);
3247        let r = _mm512_mask_ternarylogic_epi64::<8>(src, 0, a, b);
3248        assert_eq_m512i(r, src);
3249        let r = _mm512_mask_ternarylogic_epi64::<8>(src, 0b11111111, a, b);
3250        let e = _mm512_set1_epi64(0);
3251        assert_eq_m512i(r, e);
3252    }
3253
3254    #[simd_test(enable = "avx512f")]
3255    unsafe fn test_mm512_maskz_ternarylogic_epi64() {
3256        let a = _mm512_set1_epi64(1 << 2);
3257        let b = _mm512_set1_epi64(1 << 1);
3258        let c = _mm512_set1_epi64(1 << 0);
3259        let r = _mm512_maskz_ternarylogic_epi64::<8>(0, a, b, c);
3260        assert_eq_m512i(r, _mm512_setzero_si512());
3261        let r = _mm512_maskz_ternarylogic_epi64::<8>(0b11111111, a, b, c);
3262        let e = _mm512_set1_epi64(0);
3263        assert_eq_m512i(r, e);
3264    }
3265
3266    #[simd_test(enable = "avx512f,avx512vl")]
3267    unsafe fn test_mm256_ternarylogic_epi64() {
3268        let a = _mm256_set1_epi64x(1 << 2);
3269        let b = _mm256_set1_epi64x(1 << 1);
3270        let c = _mm256_set1_epi64x(1 << 0);
3271        let r = _mm256_ternarylogic_epi64::<8>(a, b, c);
3272        let e = _mm256_set1_epi64x(0);
3273        assert_eq_m256i(r, e);
3274    }
3275
3276    #[simd_test(enable = "avx512f,avx512vl")]
3277    unsafe fn test_mm256_mask_ternarylogic_epi64() {
3278        let src = _mm256_set1_epi64x(1 << 2);
3279        let a = _mm256_set1_epi64x(1 << 1);
3280        let b = _mm256_set1_epi64x(1 << 0);
3281        let r = _mm256_mask_ternarylogic_epi64::<8>(src, 0, a, b);
3282        assert_eq_m256i(r, src);
3283        let r = _mm256_mask_ternarylogic_epi64::<8>(src, 0b00001111, a, b);
3284        let e = _mm256_set1_epi64x(0);
3285        assert_eq_m256i(r, e);
3286    }
3287
3288    #[simd_test(enable = "avx512f,avx512vl")]
3289    unsafe fn test_mm256_maskz_ternarylogic_epi64() {
3290        let a = _mm256_set1_epi64x(1 << 2);
3291        let b = _mm256_set1_epi64x(1 << 1);
3292        let c = _mm256_set1_epi64x(1 << 0);
3293        let r = _mm256_maskz_ternarylogic_epi64::<9>(0, a, b, c);
3294        assert_eq_m256i(r, _mm256_setzero_si256());
3295        let r = _mm256_maskz_ternarylogic_epi64::<8>(0b00001111, a, b, c);
3296        let e = _mm256_set1_epi64x(0);
3297        assert_eq_m256i(r, e);
3298    }
3299
3300    #[simd_test(enable = "avx512f,avx512vl")]
3301    unsafe fn test_mm_ternarylogic_epi64() {
3302        let a = _mm_set1_epi64x(1 << 2);
3303        let b = _mm_set1_epi64x(1 << 1);
3304        let c = _mm_set1_epi64x(1 << 0);
3305        let r = _mm_ternarylogic_epi64::<8>(a, b, c);
3306        let e = _mm_set1_epi64x(0);
3307        assert_eq_m128i(r, e);
3308    }
3309
3310    #[simd_test(enable = "avx512f,avx512vl")]
3311    unsafe fn test_mm_mask_ternarylogic_epi64() {
3312        let src = _mm_set1_epi64x(1 << 2);
3313        let a = _mm_set1_epi64x(1 << 1);
3314        let b = _mm_set1_epi64x(1 << 0);
3315        let r = _mm_mask_ternarylogic_epi64::<8>(src, 0, a, b);
3316        assert_eq_m128i(r, src);
3317        let r = _mm_mask_ternarylogic_epi64::<8>(src, 0b00000011, a, b);
3318        let e = _mm_set1_epi64x(0);
3319        assert_eq_m128i(r, e);
3320    }
3321
3322    #[simd_test(enable = "avx512f,avx512vl")]
3323    unsafe fn test_mm_maskz_ternarylogic_epi64() {
3324        let a = _mm_set1_epi64x(1 << 2);
3325        let b = _mm_set1_epi64x(1 << 1);
3326        let c = _mm_set1_epi64x(1 << 0);
3327        let r = _mm_maskz_ternarylogic_epi64::<9>(0, a, b, c);
3328        assert_eq_m128i(r, _mm_setzero_si128());
3329        let r = _mm_maskz_ternarylogic_epi64::<8>(0b00000011, a, b, c);
3330        let e = _mm_set1_epi64x(0);
3331        assert_eq_m128i(r, e);
3332    }
3333
3334    #[simd_test(enable = "avx512f")]
3335    unsafe fn test_mm512_getmant_pd() {
3336        let a = _mm512_set1_pd(10.);
3337        let r = _mm512_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a);
3338        let e = _mm512_set1_pd(1.25);
3339        assert_eq_m512d(r, e);
3340    }
3341
3342    #[simd_test(enable = "avx512f")]
3343    unsafe fn test_mm512_mask_getmant_pd() {
3344        let a = _mm512_set1_pd(10.);
3345        let r = _mm512_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0, a);
3346        assert_eq_m512d(r, a);
3347        let r = _mm512_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0b11110000, a);
3348        let e = _mm512_setr_pd(10., 10., 10., 10., 1.25, 1.25, 1.25, 1.25);
3349        assert_eq_m512d(r, e);
3350    }
3351
3352    #[simd_test(enable = "avx512f")]
3353    unsafe fn test_mm512_maskz_getmant_pd() {
3354        let a = _mm512_set1_pd(10.);
3355        let r = _mm512_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0, a);
3356        assert_eq_m512d(r, _mm512_setzero_pd());
3357        let r = _mm512_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0b11110000, a);
3358        let e = _mm512_setr_pd(0., 0., 0., 0., 1.25, 1.25, 1.25, 1.25);
3359        assert_eq_m512d(r, e);
3360    }
3361
3362    #[simd_test(enable = "avx512f,avx512vl")]
3363    unsafe fn test_mm256_getmant_pd() {
3364        let a = _mm256_set1_pd(10.);
3365        let r = _mm256_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a);
3366        let e = _mm256_set1_pd(1.25);
3367        assert_eq_m256d(r, e);
3368    }
3369
3370    #[simd_test(enable = "avx512f,avx512vl")]
3371    unsafe fn test_mm256_mask_getmant_pd() {
3372        let a = _mm256_set1_pd(10.);
3373        let r = _mm256_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0, a);
3374        assert_eq_m256d(r, a);
3375        let r = _mm256_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0b00001111, a);
3376        let e = _mm256_set1_pd(1.25);
3377        assert_eq_m256d(r, e);
3378    }
3379
3380    #[simd_test(enable = "avx512f,avx512vl")]
3381    unsafe fn test_mm256_maskz_getmant_pd() {
3382        let a = _mm256_set1_pd(10.);
3383        let r = _mm256_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0, a);
3384        assert_eq_m256d(r, _mm256_setzero_pd());
3385        let r = _mm256_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0b00001111, a);
3386        let e = _mm256_set1_pd(1.25);
3387        assert_eq_m256d(r, e);
3388    }
3389
3390    #[simd_test(enable = "avx512f,avx512vl")]
3391    unsafe fn test_mm_getmant_pd() {
3392        let a = _mm_set1_pd(10.);
3393        let r = _mm_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a);
3394        let e = _mm_set1_pd(1.25);
3395        assert_eq_m128d(r, e);
3396    }
3397
3398    #[simd_test(enable = "avx512f,avx512vl")]
3399    unsafe fn test_mm_mask_getmant_pd() {
3400        let a = _mm_set1_pd(10.);
3401        let r = _mm_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0, a);
3402        assert_eq_m128d(r, a);
3403        let r = _mm_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0b00000011, a);
3404        let e = _mm_set1_pd(1.25);
3405        assert_eq_m128d(r, e);
3406    }
3407
3408    #[simd_test(enable = "avx512f,avx512vl")]
3409    unsafe fn test_mm_maskz_getmant_pd() {
3410        let a = _mm_set1_pd(10.);
3411        let r = _mm_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0, a);
3412        assert_eq_m128d(r, _mm_setzero_pd());
3413        let r = _mm_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0b00000011, a);
3414        let e = _mm_set1_pd(1.25);
3415        assert_eq_m128d(r, e);
3416    }
3417
3418    #[simd_test(enable = "avx512f")]
3419    unsafe fn test_mm512_cvtps_pd() {
3420        let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3421        let r = _mm512_cvtps_pd(a);
3422        let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3423        assert_eq_m512d(r, e);
3424    }
3425
3426    #[simd_test(enable = "avx512f")]
3427    unsafe fn test_mm512_mask_cvtps_pd() {
3428        let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3429        let src = _mm512_set1_pd(0.);
3430        let r = _mm512_mask_cvtps_pd(src, 0, a);
3431        assert_eq_m512d(r, src);
3432        let r = _mm512_mask_cvtps_pd(src, 0b00001111, a);
3433        let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
3434        assert_eq_m512d(r, e);
3435    }
3436
3437    #[simd_test(enable = "avx512f")]
3438    unsafe fn test_mm512_maskz_cvtps_pd() {
3439        let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3440        let r = _mm512_maskz_cvtps_pd(0, a);
3441        assert_eq_m512d(r, _mm512_setzero_pd());
3442        let r = _mm512_maskz_cvtps_pd(0b00001111, a);
3443        let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
3444        assert_eq_m512d(r, e);
3445    }
3446
3447    #[simd_test(enable = "avx512f")]
3448    unsafe fn test_mm512_cvtpslo_pd() {
3449        let v2 = _mm512_setr_ps(
3450            0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 100., 100., 100., 100., 100., 100., 100., 100.,
3451        );
3452        let r = _mm512_cvtpslo_pd(v2);
3453        let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3454        assert_eq_m512d(r, e);
3455    }
3456
3457    #[simd_test(enable = "avx512f")]
3458    unsafe fn test_mm512_mask_cvtpslo_pd() {
3459        let v2 = _mm512_setr_ps(
3460            0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 100., 100., 100., 100., 100., 100., 100., 100.,
3461        );
3462        let src = _mm512_set1_pd(0.);
3463        let r = _mm512_mask_cvtpslo_pd(src, 0, v2);
3464        assert_eq_m512d(r, src);
3465        let r = _mm512_mask_cvtpslo_pd(src, 0b00001111, v2);
3466        let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
3467        assert_eq_m512d(r, e);
3468    }
3469
3470    #[simd_test(enable = "avx512f")]
3471    unsafe fn test_mm512_cvtpd_ps() {
3472        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3473        let r = _mm512_cvtpd_ps(a);
3474        let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3475        assert_eq_m256(r, e);
3476    }
3477
3478    #[simd_test(enable = "avx512f")]
3479    unsafe fn test_mm512_mask_cvtpd_ps() {
3480        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3481        let src = _mm256_set1_ps(0.);
3482        let r = _mm512_mask_cvtpd_ps(src, 0, a);
3483        assert_eq_m256(r, src);
3484        let r = _mm512_mask_cvtpd_ps(src, 0b00001111, a);
3485        let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
3486        assert_eq_m256(r, e);
3487    }
3488
3489    #[simd_test(enable = "avx512f")]
3490    unsafe fn test_mm512_maskz_cvtpd_ps() {
3491        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3492        let r = _mm512_maskz_cvtpd_ps(0, a);
3493        assert_eq_m256(r, _mm256_setzero_ps());
3494        let r = _mm512_maskz_cvtpd_ps(0b00001111, a);
3495        let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
3496        assert_eq_m256(r, e);
3497    }
3498
3499    #[simd_test(enable = "avx512f,avx512vl")]
3500    unsafe fn test_mm256_mask_cvtpd_ps() {
3501        let a = _mm256_set_pd(4., -5.5, 6., -7.5);
3502        let src = _mm_set1_ps(0.);
3503        let r = _mm256_mask_cvtpd_ps(src, 0, a);
3504        assert_eq_m128(r, src);
3505        let r = _mm256_mask_cvtpd_ps(src, 0b00001111, a);
3506        let e = _mm_set_ps(4., -5.5, 6., -7.5);
3507        assert_eq_m128(r, e);
3508    }
3509
3510    #[simd_test(enable = "avx512f,avx512vl")]
3511    unsafe fn test_mm256_maskz_cvtpd_ps() {
3512        let a = _mm256_set_pd(4., -5.5, 6., -7.5);
3513        let r = _mm256_maskz_cvtpd_ps(0, a);
3514        assert_eq_m128(r, _mm_setzero_ps());
3515        let r = _mm256_maskz_cvtpd_ps(0b00001111, a);
3516        let e = _mm_set_ps(4., -5.5, 6., -7.5);
3517        assert_eq_m128(r, e);
3518    }
3519
3520    #[simd_test(enable = "avx512f,avx512vl")]
3521    unsafe fn test_mm_mask_cvtpd_ps() {
3522        let a = _mm_set_pd(6., -7.5);
3523        let src = _mm_set1_ps(0.);
3524        let r = _mm_mask_cvtpd_ps(src, 0, a);
3525        assert_eq_m128(r, src);
3526        let r = _mm_mask_cvtpd_ps(src, 0b00000011, a);
3527        let e = _mm_set_ps(0., 0., 6., -7.5);
3528        assert_eq_m128(r, e);
3529    }
3530
3531    #[simd_test(enable = "avx512f,avx512vl")]
3532    unsafe fn test_mm_maskz_cvtpd_ps() {
3533        let a = _mm_set_pd(6., -7.5);
3534        let r = _mm_maskz_cvtpd_ps(0, a);
3535        assert_eq_m128(r, _mm_setzero_ps());
3536        let r = _mm_maskz_cvtpd_ps(0b00000011, a);
3537        let e = _mm_set_ps(0., 0., 6., -7.5);
3538        assert_eq_m128(r, e);
3539    }
3540
3541    #[simd_test(enable = "avx512f")]
3542    unsafe fn test_mm512_cvtpd_epi32() {
3543        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3544        let r = _mm512_cvtpd_epi32(a);
3545        let e = _mm256_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8);
3546        assert_eq_m256i(r, e);
3547    }
3548
3549    #[simd_test(enable = "avx512f")]
3550    unsafe fn test_mm512_mask_cvtpd_epi32() {
3551        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3552        let src = _mm256_set1_epi32(0);
3553        let r = _mm512_mask_cvtpd_epi32(src, 0, a);
3554        assert_eq_m256i(r, src);
3555        let r = _mm512_mask_cvtpd_epi32(src, 0b11111111, a);
3556        let e = _mm256_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8);
3557        assert_eq_m256i(r, e);
3558    }
3559
3560    #[simd_test(enable = "avx512f")]
3561    unsafe fn test_mm512_maskz_cvtpd_epi32() {
3562        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3563        let r = _mm512_maskz_cvtpd_epi32(0, a);
3564        assert_eq_m256i(r, _mm256_setzero_si256());
3565        let r = _mm512_maskz_cvtpd_epi32(0b11111111, a);
3566        let e = _mm256_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8);
3567        assert_eq_m256i(r, e);
3568    }
3569
3570    #[simd_test(enable = "avx512f,avx512vl")]
3571    unsafe fn test_mm256_mask_cvtpd_epi32() {
3572        let a = _mm256_set_pd(4., -5.5, 6., -7.5);
3573        let src = _mm_set1_epi32(0);
3574        let r = _mm256_mask_cvtpd_epi32(src, 0, a);
3575        assert_eq_m128i(r, src);
3576        let r = _mm256_mask_cvtpd_epi32(src, 0b00001111, a);
3577        let e = _mm_set_epi32(4, -6, 6, -8);
3578        assert_eq_m128i(r, e);
3579    }
3580
3581    #[simd_test(enable = "avx512f,avx512vl")]
3582    unsafe fn test_mm256_maskz_cvtpd_epi32() {
3583        let a = _mm256_set_pd(4., -5.5, 6., -7.5);
3584        let r = _mm256_maskz_cvtpd_epi32(0, a);
3585        assert_eq_m128i(r, _mm_setzero_si128());
3586        let r = _mm256_maskz_cvtpd_epi32(0b00001111, a);
3587        let e = _mm_set_epi32(4, -6, 6, -8);
3588        assert_eq_m128i(r, e);
3589    }
3590
3591    #[simd_test(enable = "avx512f,avx512vl")]
3592    unsafe fn test_mm_mask_cvtpd_epi32() {
3593        let a = _mm_set_pd(6., -7.5);
3594        let src = _mm_set1_epi32(0);
3595        let r = _mm_mask_cvtpd_epi32(src, 0, a);
3596        assert_eq_m128i(r, src);
3597        let r = _mm_mask_cvtpd_epi32(src, 0b00000011, a);
3598        let e = _mm_set_epi32(0, 0, 6, -8);
3599        assert_eq_m128i(r, e);
3600    }
3601
3602    #[simd_test(enable = "avx512f,avx512vl")]
3603    unsafe fn test_mm_maskz_cvtpd_epi32() {
3604        let a = _mm_set_pd(6., -7.5);
3605        let r = _mm_maskz_cvtpd_epi32(0, a);
3606        assert_eq_m128i(r, _mm_setzero_si128());
3607        let r = _mm_maskz_cvtpd_epi32(0b00000011, a);
3608        let e = _mm_set_epi32(0, 0, 6, -8);
3609        assert_eq_m128i(r, e);
3610    }
3611
3612    #[simd_test(enable = "avx512f")]
3613    unsafe fn test_mm512_cvtpd_epu32() {
3614        let a = _mm512_setr_pd(0., 1.5, 2., 3.5, 4., 5.5, 6., 7.5);
3615        let r = _mm512_cvtpd_epu32(a);
3616        let e = _mm256_setr_epi32(0, 2, 2, 4, 4, 6, 6, 8);
3617        assert_eq_m256i(r, e);
3618    }
3619
3620    #[simd_test(enable = "avx512f")]
3621    unsafe fn test_mm512_mask_cvtpd_epu32() {
3622        let a = _mm512_setr_pd(0., 1.5, 2., 3.5, 4., 5.5, 6., 7.5);
3623        let src = _mm256_set1_epi32(0);
3624        let r = _mm512_mask_cvtpd_epu32(src, 0, a);
3625        assert_eq_m256i(r, src);
3626        let r = _mm512_mask_cvtpd_epu32(src, 0b11111111, a);
3627        let e = _mm256_setr_epi32(0, 2, 2, 4, 4, 6, 6, 8);
3628        assert_eq_m256i(r, e);
3629    }
3630
3631    #[simd_test(enable = "avx512f")]
3632    unsafe fn test_mm512_maskz_cvtpd_epu32() {
3633        let a = _mm512_setr_pd(0., 1.5, 2., 3.5, 4., 5.5, 6., 7.5);
3634        let r = _mm512_maskz_cvtpd_epu32(0, a);
3635        assert_eq_m256i(r, _mm256_setzero_si256());
3636        let r = _mm512_maskz_cvtpd_epu32(0b11111111, a);
3637        let e = _mm256_setr_epi32(0, 2, 2, 4, 4, 6, 6, 8);
3638        assert_eq_m256i(r, e);
3639    }
3640
3641    #[simd_test(enable = "avx512f,avx512vl")]
3642    unsafe fn test_mm256_cvtpd_epu32() {
3643        let a = _mm256_set_pd(4., 5.5, 6., 7.5);
3644        let r = _mm256_cvtpd_epu32(a);
3645        let e = _mm_set_epi32(4, 6, 6, 8);
3646        assert_eq_m128i(r, e);
3647    }
3648
3649    #[simd_test(enable = "avx512f,avx512vl")]
3650    unsafe fn test_mm256_mask_cvtpd_epu32() {
3651        let a = _mm256_set_pd(4., 5.5, 6., 7.5);
3652        let src = _mm_set1_epi32(0);
3653        let r = _mm256_mask_cvtpd_epu32(src, 0, a);
3654        assert_eq_m128i(r, src);
3655        let r = _mm256_mask_cvtpd_epu32(src, 0b00001111, a);
3656        let e = _mm_set_epi32(4, 6, 6, 8);
3657        assert_eq_m128i(r, e);
3658    }
3659
3660    #[simd_test(enable = "avx512f,avx512vl")]
3661    unsafe fn test_mm256_maskz_cvtpd_epu32() {
3662        let a = _mm256_set_pd(4., 5.5, 6., 7.5);
3663        let r = _mm256_maskz_cvtpd_epu32(0, a);
3664        assert_eq_m128i(r, _mm_setzero_si128());
3665        let r = _mm256_maskz_cvtpd_epu32(0b00001111, a);
3666        let e = _mm_set_epi32(4, 6, 6, 8);
3667        assert_eq_m128i(r, e);
3668    }
3669
3670    #[simd_test(enable = "avx512f,avx512vl")]
3671    unsafe fn test_mm_cvtpd_epu32() {
3672        let a = _mm_set_pd(6., 7.5);
3673        let r = _mm_cvtpd_epu32(a);
3674        let e = _mm_set_epi32(0, 0, 6, 8);
3675        assert_eq_m128i(r, e);
3676    }
3677
3678    #[simd_test(enable = "avx512f,avx512vl")]
3679    unsafe fn test_mm_mask_cvtpd_epu32() {
3680        let a = _mm_set_pd(6., 7.5);
3681        let src = _mm_set1_epi32(0);
3682        let r = _mm_mask_cvtpd_epu32(src, 0, a);
3683        assert_eq_m128i(r, src);
3684        let r = _mm_mask_cvtpd_epu32(src, 0b00000011, a);
3685        let e = _mm_set_epi32(0, 0, 6, 8);
3686        assert_eq_m128i(r, e);
3687    }
3688
3689    #[simd_test(enable = "avx512f,avx512vl")]
3690    unsafe fn test_mm_maskz_cvtpd_epu32() {
3691        let a = _mm_set_pd(6., 7.5);
3692        let r = _mm_maskz_cvtpd_epu32(0, a);
3693        assert_eq_m128i(r, _mm_setzero_si128());
3694        let r = _mm_maskz_cvtpd_epu32(0b00000011, a);
3695        let e = _mm_set_epi32(0, 0, 6, 8);
3696        assert_eq_m128i(r, e);
3697    }
3698
3699    #[simd_test(enable = "avx512f")]
3700    unsafe fn test_mm512_cvtpd_pslo() {
3701        let v2 = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3702        let r = _mm512_cvtpd_pslo(v2);
3703        let e = _mm512_setr_ps(
3704            0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 0., 0., 0., 0., 0., 0., 0., 0.,
3705        );
3706        assert_eq_m512(r, e);
3707    }
3708
3709    #[simd_test(enable = "avx512f")]
3710    unsafe fn test_mm512_mask_cvtpd_pslo() {
3711        let v2 = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3712        let src = _mm512_set1_ps(0.);
3713        let r = _mm512_mask_cvtpd_pslo(src, 0, v2);
3714        assert_eq_m512(r, src);
3715        let r = _mm512_mask_cvtpd_pslo(src, 0b00001111, v2);
3716        let e = _mm512_setr_ps(
3717            0., -1.5, 2., -3.5, 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0.,
3718        );
3719        assert_eq_m512(r, e);
3720    }
3721
3722    #[simd_test(enable = "avx512f")]
3723    unsafe fn test_mm512_cvtepi8_epi64() {
3724        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3725        let r = _mm512_cvtepi8_epi64(a);
3726        let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
3727        assert_eq_m512i(r, e);
3728    }
3729
3730    #[simd_test(enable = "avx512f")]
3731    unsafe fn test_mm512_mask_cvtepi8_epi64() {
3732        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3733        let src = _mm512_set1_epi64(-1);
3734        let r = _mm512_mask_cvtepi8_epi64(src, 0, a);
3735        assert_eq_m512i(r, src);
3736        let r = _mm512_mask_cvtepi8_epi64(src, 0b00001111, a);
3737        let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
3738        assert_eq_m512i(r, e);
3739    }
3740
3741    #[simd_test(enable = "avx512f")]
3742    unsafe fn test_mm512_maskz_cvtepi8_epi64() {
3743        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3744        let r = _mm512_maskz_cvtepi8_epi64(0, a);
3745        assert_eq_m512i(r, _mm512_setzero_si512());
3746        let r = _mm512_maskz_cvtepi8_epi64(0b00001111, a);
3747        let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
3748        assert_eq_m512i(r, e);
3749    }
3750
3751    #[simd_test(enable = "avx512f,avx512vl")]
3752    unsafe fn test_mm256_mask_cvtepi8_epi64() {
3753        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3754        let src = _mm256_set1_epi64x(-1);
3755        let r = _mm256_mask_cvtepi8_epi64(src, 0, a);
3756        assert_eq_m256i(r, src);
3757        let r = _mm256_mask_cvtepi8_epi64(src, 0b00001111, a);
3758        let e = _mm256_set_epi64x(12, 13, 14, 15);
3759        assert_eq_m256i(r, e);
3760    }
3761
3762    #[simd_test(enable = "avx512f,avx512vl")]
3763    unsafe fn test_mm256_maskz_cvtepi8_epi64() {
3764        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3765        let r = _mm256_maskz_cvtepi8_epi64(0, a);
3766        assert_eq_m256i(r, _mm256_setzero_si256());
3767        let r = _mm256_maskz_cvtepi8_epi64(0b00001111, a);
3768        let e = _mm256_set_epi64x(12, 13, 14, 15);
3769        assert_eq_m256i(r, e);
3770    }
3771
3772    #[simd_test(enable = "avx512f,avx512vl")]
3773    unsafe fn test_mm_mask_cvtepi8_epi64() {
3774        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3775        let src = _mm_set1_epi64x(-1);
3776        let r = _mm_mask_cvtepi8_epi64(src, 0, a);
3777        assert_eq_m128i(r, src);
3778        let r = _mm_mask_cvtepi8_epi64(src, 0b00000011, a);
3779        let e = _mm_set_epi64x(14, 15);
3780        assert_eq_m128i(r, e);
3781    }
3782
3783    #[simd_test(enable = "avx512f,avx512vl")]
3784    unsafe fn test_mm_maskz_cvtepi8_epi64() {
3785        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3786        let r = _mm_maskz_cvtepi8_epi64(0, a);
3787        assert_eq_m128i(r, _mm_setzero_si128());
3788        let r = _mm_maskz_cvtepi8_epi64(0b00000011, a);
3789        let e = _mm_set_epi64x(14, 15);
3790        assert_eq_m128i(r, e);
3791    }
3792
3793    #[simd_test(enable = "avx512f")]
3794    unsafe fn test_mm512_cvtepu8_epi64() {
3795        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3796        let r = _mm512_cvtepu8_epi64(a);
3797        let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
3798        assert_eq_m512i(r, e);
3799    }
3800
3801    #[simd_test(enable = "avx512f")]
3802    unsafe fn test_mm512_mask_cvtepu8_epi64() {
3803        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3804        let src = _mm512_set1_epi64(-1);
3805        let r = _mm512_mask_cvtepu8_epi64(src, 0, a);
3806        assert_eq_m512i(r, src);
3807        let r = _mm512_mask_cvtepu8_epi64(src, 0b00001111, a);
3808        let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
3809        assert_eq_m512i(r, e);
3810    }
3811
3812    #[simd_test(enable = "avx512f")]
3813    unsafe fn test_mm512_maskz_cvtepu8_epi64() {
3814        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3815        let r = _mm512_maskz_cvtepu8_epi64(0, a);
3816        assert_eq_m512i(r, _mm512_setzero_si512());
3817        let r = _mm512_maskz_cvtepu8_epi64(0b00001111, a);
3818        let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
3819        assert_eq_m512i(r, e);
3820    }
3821
3822    #[simd_test(enable = "avx512f,avx512vl")]
3823    unsafe fn test_mm256_mask_cvtepu8_epi64() {
3824        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3825        let src = _mm256_set1_epi64x(-1);
3826        let r = _mm256_mask_cvtepu8_epi64(src, 0, a);
3827        assert_eq_m256i(r, src);
3828        let r = _mm256_mask_cvtepu8_epi64(src, 0b00001111, a);
3829        let e = _mm256_set_epi64x(12, 13, 14, 15);
3830        assert_eq_m256i(r, e);
3831    }
3832
3833    #[simd_test(enable = "avx512f,avx512vl")]
3834    unsafe fn test_mm256_maskz_cvtepu8_epi64() {
3835        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3836        let r = _mm256_maskz_cvtepu8_epi64(0, a);
3837        assert_eq_m256i(r, _mm256_setzero_si256());
3838        let r = _mm256_maskz_cvtepu8_epi64(0b00001111, a);
3839        let e = _mm256_set_epi64x(12, 13, 14, 15);
3840        assert_eq_m256i(r, e);
3841    }
3842
3843    #[simd_test(enable = "avx512f,avx512vl")]
3844    unsafe fn test_mm_mask_cvtepu8_epi64() {
3845        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3846        let src = _mm_set1_epi64x(-1);
3847        let r = _mm_mask_cvtepu8_epi64(src, 0, a);
3848        assert_eq_m128i(r, src);
3849        let r = _mm_mask_cvtepu8_epi64(src, 0b00000011, a);
3850        let e = _mm_set_epi64x(14, 15);
3851        assert_eq_m128i(r, e);
3852    }
3853
3854    #[simd_test(enable = "avx512f,avx512vl")]
3855    unsafe fn test_mm_maskz_cvtepu8_epi64() {
3856        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3857        let r = _mm_maskz_cvtepu8_epi64(0, a);
3858        assert_eq_m128i(r, _mm_setzero_si128());
3859        let r = _mm_maskz_cvtepu8_epi64(0b00000011, a);
3860        let e = _mm_set_epi64x(14, 15);
3861        assert_eq_m128i(r, e);
3862    }
3863
3864    #[simd_test(enable = "avx512f")]
3865    unsafe fn test_mm512_cvtepi16_epi64() {
3866        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3867        let r = _mm512_cvtepi16_epi64(a);
3868        let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
3869        assert_eq_m512i(r, e);
3870    }
3871
3872    #[simd_test(enable = "avx512f")]
3873    unsafe fn test_mm512_mask_cvtepi16_epi64() {
3874        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3875        let src = _mm512_set1_epi64(-1);
3876        let r = _mm512_mask_cvtepi16_epi64(src, 0, a);
3877        assert_eq_m512i(r, src);
3878        let r = _mm512_mask_cvtepi16_epi64(src, 0b00001111, a);
3879        let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
3880        assert_eq_m512i(r, e);
3881    }
3882
3883    #[simd_test(enable = "avx512f")]
3884    unsafe fn test_mm512_maskz_cvtepi16_epi64() {
3885        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3886        let r = _mm512_maskz_cvtepi16_epi64(0, a);
3887        assert_eq_m512i(r, _mm512_setzero_si512());
3888        let r = _mm512_maskz_cvtepi16_epi64(0b00001111, a);
3889        let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
3890        assert_eq_m512i(r, e);
3891    }
3892
3893    #[simd_test(enable = "avx512f,avx512vl")]
3894    unsafe fn test_mm256_mask_cvtepi16_epi64() {
3895        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3896        let src = _mm256_set1_epi64x(-1);
3897        let r = _mm256_mask_cvtepi16_epi64(src, 0, a);
3898        assert_eq_m256i(r, src);
3899        let r = _mm256_mask_cvtepi16_epi64(src, 0b00001111, a);
3900        let e = _mm256_set_epi64x(12, 13, 14, 15);
3901        assert_eq_m256i(r, e);
3902    }
3903
3904    #[simd_test(enable = "avx512f,avx512vl")]
3905    unsafe fn test_mm256_maskz_cvtepi16_epi64() {
3906        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3907        let r = _mm256_maskz_cvtepi16_epi64(0, a);
3908        assert_eq_m256i(r, _mm256_setzero_si256());
3909        let r = _mm256_maskz_cvtepi16_epi64(0b00001111, a);
3910        let e = _mm256_set_epi64x(12, 13, 14, 15);
3911        assert_eq_m256i(r, e);
3912    }
3913
3914    #[simd_test(enable = "avx512f,avx512vl")]
3915    unsafe fn test_mm_mask_cvtepi16_epi64() {
3916        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3917        let src = _mm_set1_epi64x(-1);
3918        let r = _mm_mask_cvtepi16_epi64(src, 0, a);
3919        assert_eq_m128i(r, src);
3920        let r = _mm_mask_cvtepi16_epi64(src, 0b00000011, a);
3921        let e = _mm_set_epi64x(14, 15);
3922        assert_eq_m128i(r, e);
3923    }
3924
3925    #[simd_test(enable = "avx512f,avx512vl")]
3926    unsafe fn test_mm_maskz_cvtepi16_epi64() {
3927        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3928        let r = _mm_maskz_cvtepi16_epi64(0, a);
3929        assert_eq_m128i(r, _mm_setzero_si128());
3930        let r = _mm_maskz_cvtepi16_epi64(0b00000011, a);
3931        let e = _mm_set_epi64x(14, 15);
3932        assert_eq_m128i(r, e);
3933    }
3934
3935    #[simd_test(enable = "avx512f")]
3936    unsafe fn test_mm512_cvtepu16_epi64() {
3937        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3938        let r = _mm512_cvtepu16_epi64(a);
3939        let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
3940        assert_eq_m512i(r, e);
3941    }
3942
3943    #[simd_test(enable = "avx512f")]
3944    unsafe fn test_mm512_mask_cvtepu16_epi64() {
3945        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3946        let src = _mm512_set1_epi64(-1);
3947        let r = _mm512_mask_cvtepu16_epi64(src, 0, a);
3948        assert_eq_m512i(r, src);
3949        let r = _mm512_mask_cvtepu16_epi64(src, 0b00001111, a);
3950        let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
3951        assert_eq_m512i(r, e);
3952    }
3953
3954    #[simd_test(enable = "avx512f")]
3955    unsafe fn test_mm512_maskz_cvtepu16_epi64() {
3956        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3957        let r = _mm512_maskz_cvtepu16_epi64(0, a);
3958        assert_eq_m512i(r, _mm512_setzero_si512());
3959        let r = _mm512_maskz_cvtepu16_epi64(0b00001111, a);
3960        let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
3961        assert_eq_m512i(r, e);
3962    }
3963
3964    #[simd_test(enable = "avx512f,avx512vl")]
3965    unsafe fn test_mm256_mask_cvtepu16_epi64() {
3966        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3967        let src = _mm256_set1_epi64x(-1);
3968        let r = _mm256_mask_cvtepu16_epi64(src, 0, a);
3969        assert_eq_m256i(r, src);
3970        let r = _mm256_mask_cvtepu16_epi64(src, 0b00001111, a);
3971        let e = _mm256_set_epi64x(12, 13, 14, 15);
3972        assert_eq_m256i(r, e);
3973    }
3974
3975    #[simd_test(enable = "avx512f,avx512vl")]
3976    unsafe fn test_mm256_maskz_cvtepu16_epi64() {
3977        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3978        let r = _mm256_maskz_cvtepu16_epi64(0, a);
3979        assert_eq_m256i(r, _mm256_setzero_si256());
3980        let r = _mm256_maskz_cvtepu16_epi64(0b00001111, a);
3981        let e = _mm256_set_epi64x(12, 13, 14, 15);
3982        assert_eq_m256i(r, e);
3983    }
3984
3985    #[simd_test(enable = "avx512f,avx512vl")]
3986    unsafe fn test_mm_mask_cvtepu16_epi64() {
3987        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3988        let src = _mm_set1_epi64x(-1);
3989        let r = _mm_mask_cvtepu16_epi64(src, 0, a);
3990        assert_eq_m128i(r, src);
3991        let r = _mm_mask_cvtepu16_epi64(src, 0b00000011, a);
3992        let e = _mm_set_epi64x(14, 15);
3993        assert_eq_m128i(r, e);
3994    }
3995
3996    #[simd_test(enable = "avx512f,avx512vl")]
3997    unsafe fn test_mm_maskz_cvtepu16_epi64() {
3998        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3999        let r = _mm_maskz_cvtepu16_epi64(0, a);
4000        assert_eq_m128i(r, _mm_setzero_si128());
4001        let r = _mm_maskz_cvtepu16_epi64(0b00000011, a);
4002        let e = _mm_set_epi64x(14, 15);
4003        assert_eq_m128i(r, e);
4004    }
4005
4006    #[simd_test(enable = "avx512f")]
4007    unsafe fn test_mm512_cvtepi32_epi64() {
4008        let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4009        let r = _mm512_cvtepi32_epi64(a);
4010        let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4011        assert_eq_m512i(r, e);
4012    }
4013
4014    #[simd_test(enable = "avx512f")]
4015    unsafe fn test_mm512_mask_cvtepi32_epi64() {
4016        let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4017        let src = _mm512_set1_epi64(-1);
4018        let r = _mm512_mask_cvtepi32_epi64(src, 0, a);
4019        assert_eq_m512i(r, src);
4020        let r = _mm512_mask_cvtepi32_epi64(src, 0b00001111, a);
4021        let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
4022        assert_eq_m512i(r, e);
4023    }
4024
4025    #[simd_test(enable = "avx512f")]
4026    unsafe fn test_mm512_maskz_cvtepi32_epi64() {
4027        let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4028        let r = _mm512_maskz_cvtepi32_epi64(0, a);
4029        assert_eq_m512i(r, _mm512_setzero_si512());
4030        let r = _mm512_maskz_cvtepi32_epi64(0b00001111, a);
4031        let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
4032        assert_eq_m512i(r, e);
4033    }
4034
4035    #[simd_test(enable = "avx512f,avx512vl")]
4036    unsafe fn test_mm256_mask_cvtepi32_epi64() {
4037        let a = _mm_set_epi32(8, 9, 10, 11);
4038        let src = _mm256_set1_epi64x(-1);
4039        let r = _mm256_mask_cvtepi32_epi64(src, 0, a);
4040        assert_eq_m256i(r, src);
4041        let r = _mm256_mask_cvtepi32_epi64(src, 0b00001111, a);
4042        let e = _mm256_set_epi64x(8, 9, 10, 11);
4043        assert_eq_m256i(r, e);
4044    }
4045
4046    #[simd_test(enable = "avx512f,avx512vl")]
4047    unsafe fn test_mm256_maskz_cvtepi32_epi64() {
4048        let a = _mm_set_epi32(8, 9, 10, 11);
4049        let r = _mm256_maskz_cvtepi32_epi64(0, a);
4050        assert_eq_m256i(r, _mm256_setzero_si256());
4051        let r = _mm256_maskz_cvtepi32_epi64(0b00001111, a);
4052        let e = _mm256_set_epi64x(8, 9, 10, 11);
4053        assert_eq_m256i(r, e);
4054    }
4055
4056    #[simd_test(enable = "avx512f,avx512vl")]
4057    unsafe fn test_mm_mask_cvtepi32_epi64() {
4058        let a = _mm_set_epi32(8, 9, 10, 11);
4059        let src = _mm_set1_epi64x(0);
4060        let r = _mm_mask_cvtepi32_epi64(src, 0, a);
4061        assert_eq_m128i(r, src);
4062        let r = _mm_mask_cvtepi32_epi64(src, 0b00000011, a);
4063        let e = _mm_set_epi64x(10, 11);
4064        assert_eq_m128i(r, e);
4065    }
4066
4067    #[simd_test(enable = "avx512f,avx512vl")]
4068    unsafe fn test_mm_maskz_cvtepi32_epi64() {
4069        let a = _mm_set_epi32(8, 9, 10, 11);
4070        let r = _mm_maskz_cvtepi32_epi64(0, a);
4071        assert_eq_m128i(r, _mm_setzero_si128());
4072        let r = _mm_maskz_cvtepi32_epi64(0b00000011, a);
4073        let e = _mm_set_epi64x(10, 11);
4074        assert_eq_m128i(r, e);
4075    }
4076
4077    #[simd_test(enable = "avx512f")]
4078    unsafe fn test_mm512_cvtepu32_epi64() {
4079        let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4080        let r = _mm512_cvtepu32_epi64(a);
4081        let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4082        assert_eq_m512i(r, e);
4083    }
4084
4085    #[simd_test(enable = "avx512f")]
4086    unsafe fn test_mm512_mask_cvtepu32_epi64() {
4087        let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4088        let src = _mm512_set1_epi64(-1);
4089        let r = _mm512_mask_cvtepu32_epi64(src, 0, a);
4090        assert_eq_m512i(r, src);
4091        let r = _mm512_mask_cvtepu32_epi64(src, 0b00001111, a);
4092        let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
4093        assert_eq_m512i(r, e);
4094    }
4095
4096    #[simd_test(enable = "avx512f")]
4097    unsafe fn test_mm512_maskz_cvtepu32_epi64() {
4098        let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4099        let r = _mm512_maskz_cvtepu32_epi64(0, a);
4100        assert_eq_m512i(r, _mm512_setzero_si512());
4101        let r = _mm512_maskz_cvtepu32_epi64(0b00001111, a);
4102        let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
4103        assert_eq_m512i(r, e);
4104    }
4105
4106    #[simd_test(enable = "avx512f,avx512vl")]
4107    unsafe fn test_mm256_mask_cvtepu32_epi64() {
4108        let a = _mm_set_epi32(12, 13, 14, 15);
4109        let src = _mm256_set1_epi64x(-1);
4110        let r = _mm256_mask_cvtepu32_epi64(src, 0, a);
4111        assert_eq_m256i(r, src);
4112        let r = _mm256_mask_cvtepu32_epi64(src, 0b00001111, a);
4113        let e = _mm256_set_epi64x(12, 13, 14, 15);
4114        assert_eq_m256i(r, e);
4115    }
4116
4117    #[simd_test(enable = "avx512f,avx512vl")]
4118    unsafe fn test_mm256_maskz_cvtepu32_epi64() {
4119        let a = _mm_set_epi32(12, 13, 14, 15);
4120        let r = _mm256_maskz_cvtepu32_epi64(0, a);
4121        assert_eq_m256i(r, _mm256_setzero_si256());
4122        let r = _mm256_maskz_cvtepu32_epi64(0b00001111, a);
4123        let e = _mm256_set_epi64x(12, 13, 14, 15);
4124        assert_eq_m256i(r, e);
4125    }
4126
4127    #[simd_test(enable = "avx512f,avx512vl")]
4128    unsafe fn test_mm_mask_cvtepu32_epi64() {
4129        let a = _mm_set_epi32(12, 13, 14, 15);
4130        let src = _mm_set1_epi64x(-1);
4131        let r = _mm_mask_cvtepu32_epi64(src, 0, a);
4132        assert_eq_m128i(r, src);
4133        let r = _mm_mask_cvtepu32_epi64(src, 0b00000011, a);
4134        let e = _mm_set_epi64x(14, 15);
4135        assert_eq_m128i(r, e);
4136    }
4137
4138    #[simd_test(enable = "avx512f,avx512vl")]
4139    unsafe fn test_mm_maskz_cvtepu32_epi64() {
4140        let a = _mm_set_epi32(12, 13, 14, 15);
4141        let r = _mm_maskz_cvtepu32_epi64(0, a);
4142        assert_eq_m128i(r, _mm_setzero_si128());
4143        let r = _mm_maskz_cvtepu32_epi64(0b00000011, a);
4144        let e = _mm_set_epi64x(14, 15);
4145        assert_eq_m128i(r, e);
4146    }
4147
4148    #[simd_test(enable = "avx512f")]
4149    unsafe fn test_mm512_cvtepi32_pd() {
4150        let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4151        let r = _mm512_cvtepi32_pd(a);
4152        let e = _mm512_set_pd(8., 9., 10., 11., 12., 13., 14., 15.);
4153        assert_eq_m512d(r, e);
4154    }
4155
4156    #[simd_test(enable = "avx512f")]
4157    unsafe fn test_mm512_mask_cvtepi32_pd() {
4158        let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4159        let src = _mm512_set1_pd(-1.);
4160        let r = _mm512_mask_cvtepi32_pd(src, 0, a);
4161        assert_eq_m512d(r, src);
4162        let r = _mm512_mask_cvtepi32_pd(src, 0b00001111, a);
4163        let e = _mm512_set_pd(-1., -1., -1., -1., 12., 13., 14., 15.);
4164        assert_eq_m512d(r, e);
4165    }
4166
4167    #[simd_test(enable = "avx512f")]
4168    unsafe fn test_mm512_maskz_cvtepi32_pd() {
4169        let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4170        let r = _mm512_maskz_cvtepi32_pd(0, a);
4171        assert_eq_m512d(r, _mm512_setzero_pd());
4172        let r = _mm512_maskz_cvtepi32_pd(0b00001111, a);
4173        let e = _mm512_set_pd(0., 0., 0., 0., 12., 13., 14., 15.);
4174        assert_eq_m512d(r, e);
4175    }
4176
4177    #[simd_test(enable = "avx512f,avx512vl")]
4178    unsafe fn test_mm256_mask_cvtepi32_pd() {
4179        let a = _mm_set_epi32(12, 13, 14, 15);
4180        let src = _mm256_set1_pd(-1.);
4181        let r = _mm256_mask_cvtepi32_pd(src, 0, a);
4182        assert_eq_m256d(r, src);
4183        let r = _mm256_mask_cvtepi32_pd(src, 0b00001111, a);
4184        let e = _mm256_set_pd(12., 13., 14., 15.);
4185        assert_eq_m256d(r, e);
4186    }
4187
4188    #[simd_test(enable = "avx512f,avx512vl")]
4189    unsafe fn test_mm256_maskz_cvtepi32_pd() {
4190        let a = _mm_set_epi32(12, 13, 14, 15);
4191        let r = _mm256_maskz_cvtepi32_pd(0, a);
4192        assert_eq_m256d(r, _mm256_setzero_pd());
4193        let r = _mm256_maskz_cvtepi32_pd(0b00001111, a);
4194        let e = _mm256_set_pd(12., 13., 14., 15.);
4195        assert_eq_m256d(r, e);
4196    }
4197
4198    #[simd_test(enable = "avx512f,avx512vl")]
4199    unsafe fn test_mm_mask_cvtepi32_pd() {
4200        let a = _mm_set_epi32(12, 13, 14, 15);
4201        let src = _mm_set1_pd(-1.);
4202        let r = _mm_mask_cvtepi32_pd(src, 0, a);
4203        assert_eq_m128d(r, src);
4204        let r = _mm_mask_cvtepi32_pd(src, 0b00000011, a);
4205        let e = _mm_set_pd(14., 15.);
4206        assert_eq_m128d(r, e);
4207    }
4208
4209    #[simd_test(enable = "avx512f,avx512vl")]
4210    unsafe fn test_mm_maskz_cvtepi32_pd() {
4211        let a = _mm_set_epi32(12, 13, 14, 15);
4212        let r = _mm_maskz_cvtepi32_pd(0, a);
4213        assert_eq_m128d(r, _mm_setzero_pd());
4214        let r = _mm_maskz_cvtepi32_pd(0b00000011, a);
4215        let e = _mm_set_pd(14., 15.);
4216        assert_eq_m128d(r, e);
4217    }
4218
4219    #[simd_test(enable = "avx512f")]
4220    unsafe fn test_mm512_cvtepu32_pd() {
4221        let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4222        let r = _mm512_cvtepu32_pd(a);
4223        let e = _mm512_set_pd(8., 9., 10., 11., 12., 13., 14., 15.);
4224        assert_eq_m512d(r, e);
4225    }
4226
4227    #[simd_test(enable = "avx512f")]
4228    unsafe fn test_mm512_mask_cvtepu32_pd() {
4229        let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4230        let src = _mm512_set1_pd(-1.);
4231        let r = _mm512_mask_cvtepu32_pd(src, 0, a);
4232        assert_eq_m512d(r, src);
4233        let r = _mm512_mask_cvtepu32_pd(src, 0b00001111, a);
4234        let e = _mm512_set_pd(-1., -1., -1., -1., 12., 13., 14., 15.);
4235        assert_eq_m512d(r, e);
4236    }
4237
4238    #[simd_test(enable = "avx512f")]
4239    unsafe fn test_mm512_maskz_cvtepu32_pd() {
4240        let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4241        let r = _mm512_maskz_cvtepu32_pd(0, a);
4242        assert_eq_m512d(r, _mm512_setzero_pd());
4243        let r = _mm512_maskz_cvtepu32_pd(0b00001111, a);
4244        let e = _mm512_set_pd(0., 0., 0., 0., 12., 13., 14., 15.);
4245        assert_eq_m512d(r, e);
4246    }
4247
4248    #[simd_test(enable = "avx512f,avx512vl")]
4249    unsafe fn test_mm256_cvtepu32_pd() {
4250        let a = _mm_set_epi32(12, 13, 14, 15);
4251        let r = _mm256_cvtepu32_pd(a);
4252        let e = _mm256_set_pd(12., 13., 14., 15.);
4253        assert_eq_m256d(r, e);
4254    }
4255
4256    #[simd_test(enable = "avx512f,avx512vl")]
4257    unsafe fn test_mm256_mask_cvtepu32_pd() {
4258        let a = _mm_set_epi32(12, 13, 14, 15);
4259        let src = _mm256_set1_pd(-1.);
4260        let r = _mm256_mask_cvtepu32_pd(src, 0, a);
4261        assert_eq_m256d(r, src);
4262        let r = _mm256_mask_cvtepu32_pd(src, 0b00001111, a);
4263        let e = _mm256_set_pd(12., 13., 14., 15.);
4264        assert_eq_m256d(r, e);
4265    }
4266
4267    #[simd_test(enable = "avx512f,avx512vl")]
4268    unsafe fn test_mm256_maskz_cvtepu32_pd() {
4269        let a = _mm_set_epi32(12, 13, 14, 15);
4270        let r = _mm256_maskz_cvtepu32_pd(0, a);
4271        assert_eq_m256d(r, _mm256_setzero_pd());
4272        let r = _mm256_maskz_cvtepu32_pd(0b00001111, a);
4273        let e = _mm256_set_pd(12., 13., 14., 15.);
4274        assert_eq_m256d(r, e);
4275    }
4276
4277    #[simd_test(enable = "avx512f,avx512vl")]
4278    unsafe fn test_mm_cvtepu32_pd() {
4279        let a = _mm_set_epi32(12, 13, 14, 15);
4280        let r = _mm_cvtepu32_pd(a);
4281        let e = _mm_set_pd(14., 15.);
4282        assert_eq_m128d(r, e);
4283    }
4284
4285    #[simd_test(enable = "avx512f,avx512vl")]
4286    unsafe fn test_mm_mask_cvtepu32_pd() {
4287        let a = _mm_set_epi32(12, 13, 14, 15);
4288        let src = _mm_set1_pd(-1.);
4289        let r = _mm_mask_cvtepu32_pd(src, 0, a);
4290        assert_eq_m128d(r, src);
4291        let r = _mm_mask_cvtepu32_pd(src, 0b00000011, a);
4292        let e = _mm_set_pd(14., 15.);
4293        assert_eq_m128d(r, e);
4294    }
4295
4296    #[simd_test(enable = "avx512f,avx512vl")]
4297    unsafe fn test_mm_maskz_cvtepu32_pd() {
4298        let a = _mm_set_epi32(12, 13, 14, 15);
4299        let r = _mm_maskz_cvtepu32_pd(0, a);
4300        assert_eq_m128d(r, _mm_setzero_pd());
4301        let r = _mm_maskz_cvtepu32_pd(0b00000011, a);
4302        let e = _mm_set_pd(14., 15.);
4303        assert_eq_m128d(r, e);
4304    }
4305
4306    #[simd_test(enable = "avx512f")]
4307    unsafe fn test_mm512_cvtepi32lo_pd() {
4308        let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
4309        let r = _mm512_cvtepi32lo_pd(a);
4310        let e = _mm512_set_pd(8., 9., 10., 11., 12., 13., 14., 15.);
4311        assert_eq_m512d(r, e);
4312    }
4313
4314    #[simd_test(enable = "avx512f")]
4315    unsafe fn test_mm512_mask_cvtepi32lo_pd() {
4316        let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
4317        let src = _mm512_set1_pd(-1.);
4318        let r = _mm512_mask_cvtepi32lo_pd(src, 0, a);
4319        assert_eq_m512d(r, src);
4320        let r = _mm512_mask_cvtepi32lo_pd(src, 0b00001111, a);
4321        let e = _mm512_set_pd(-1., -1., -1., -1., 12., 13., 14., 15.);
4322        assert_eq_m512d(r, e);
4323    }
4324
4325    #[simd_test(enable = "avx512f")]
4326    unsafe fn test_mm512_cvtepu32lo_pd() {
4327        let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
4328        let r = _mm512_cvtepu32lo_pd(a);
4329        let e = _mm512_set_pd(8., 9., 10., 11., 12., 13., 14., 15.);
4330        assert_eq_m512d(r, e);
4331    }
4332
4333    #[simd_test(enable = "avx512f")]
4334    unsafe fn test_mm512_mask_cvtepu32lo_pd() {
4335        let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
4336        let src = _mm512_set1_pd(-1.);
4337        let r = _mm512_mask_cvtepu32lo_pd(src, 0, a);
4338        assert_eq_m512d(r, src);
4339        let r = _mm512_mask_cvtepu32lo_pd(src, 0b00001111, a);
4340        let e = _mm512_set_pd(-1., -1., -1., -1., 12., 13., 14., 15.);
4341        assert_eq_m512d(r, e);
4342    }
4343
4344    #[simd_test(enable = "avx512f")]
4345    unsafe fn test_mm512_cvtepi64_epi32() {
4346        let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4347        let r = _mm512_cvtepi64_epi32(a);
4348        let e = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4349        assert_eq_m256i(r, e);
4350    }
4351
4352    #[simd_test(enable = "avx512f")]
4353    unsafe fn test_mm512_mask_cvtepi64_epi32() {
4354        let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4355        let src = _mm256_set1_epi32(-1);
4356        let r = _mm512_mask_cvtepi64_epi32(src, 0, a);
4357        assert_eq_m256i(r, src);
4358        let r = _mm512_mask_cvtepi64_epi32(src, 0b00001111, a);
4359        let e = _mm256_set_epi32(-1, -1, -1, -1, 12, 13, 14, 15);
4360        assert_eq_m256i(r, e);
4361    }
4362
4363    #[simd_test(enable = "avx512f")]
4364    unsafe fn test_mm512_maskz_cvtepi64_epi32() {
4365        let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4366        let r = _mm512_maskz_cvtepi64_epi32(0, a);
4367        assert_eq_m256i(r, _mm256_setzero_si256());
4368        let r = _mm512_maskz_cvtepi64_epi32(0b00001111, a);
4369        let e = _mm256_set_epi32(0, 0, 0, 0, 12, 13, 14, 15);
4370        assert_eq_m256i(r, e);
4371    }
4372
4373    #[simd_test(enable = "avx512f,avx512vl")]
4374    unsafe fn test_mm256_cvtepi64_epi32() {
4375        let a = _mm256_set_epi64x(1, 2, 3, 4);
4376        let r = _mm256_cvtepi64_epi32(a);
4377        let e = _mm_set_epi32(1, 2, 3, 4);
4378        assert_eq_m128i(r, e);
4379    }
4380
4381    #[simd_test(enable = "avx512f,avx512vl")]
4382    unsafe fn test_mm256_mask_cvtepi64_epi32() {
4383        let a = _mm256_set_epi64x(1, 2, 3, 4);
4384        let src = _mm_set1_epi32(0);
4385        let r = _mm256_mask_cvtepi64_epi32(src, 0, a);
4386        assert_eq_m128i(r, src);
4387        let r = _mm256_mask_cvtepi64_epi32(src, 0b00001111, a);
4388        let e = _mm_set_epi32(1, 2, 3, 4);
4389        assert_eq_m128i(r, e);
4390    }
4391
4392    #[simd_test(enable = "avx512f,avx512vl")]
4393    unsafe fn test_mm256_maskz_cvtepi64_epi32() {
4394        let a = _mm256_set_epi64x(1, 2, 3, 4);
4395        let r = _mm256_maskz_cvtepi64_epi32(0, a);
4396        assert_eq_m128i(r, _mm_setzero_si128());
4397        let r = _mm256_maskz_cvtepi64_epi32(0b00001111, a);
4398        let e = _mm_set_epi32(1, 2, 3, 4);
4399        assert_eq_m128i(r, e);
4400    }
4401
4402    #[simd_test(enable = "avx512f,avx512vl")]
4403    unsafe fn test_mm_cvtepi64_epi32() {
4404        let a = _mm_set_epi64x(3, 4);
4405        let r = _mm_cvtepi64_epi32(a);
4406        let e = _mm_set_epi32(0, 0, 3, 4);
4407        assert_eq_m128i(r, e);
4408    }
4409
4410    #[simd_test(enable = "avx512f,avx512vl")]
4411    unsafe fn test_mm_mask_cvtepi64_epi32() {
4412        let a = _mm_set_epi64x(3, 4);
4413        let src = _mm_set1_epi32(0);
4414        let r = _mm_mask_cvtepi64_epi32(src, 0, a);
4415        assert_eq_m128i(r, src);
4416        let r = _mm_mask_cvtepi64_epi32(src, 0b00000011, a);
4417        let e = _mm_set_epi32(0, 0, 3, 4);
4418        assert_eq_m128i(r, e);
4419    }
4420
4421    #[simd_test(enable = "avx512f,avx512vl")]
4422    unsafe fn test_mm_maskz_cvtepi64_epi32() {
4423        let a = _mm_set_epi64x(3, 4);
4424        let r = _mm_maskz_cvtepi64_epi32(0, a);
4425        assert_eq_m128i(r, _mm_setzero_si128());
4426        let r = _mm_maskz_cvtepi64_epi32(0b00000011, a);
4427        let e = _mm_set_epi32(0, 0, 3, 4);
4428        assert_eq_m128i(r, e);
4429    }
4430
4431    #[simd_test(enable = "avx512f")]
4432    unsafe fn test_mm512_cvtepi64_epi16() {
4433        let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4434        let r = _mm512_cvtepi64_epi16(a);
4435        let e = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
4436        assert_eq_m128i(r, e);
4437    }
4438
4439    #[simd_test(enable = "avx512f")]
4440    unsafe fn test_mm512_mask_cvtepi64_epi16() {
4441        let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4442        let src = _mm_set1_epi16(-1);
4443        let r = _mm512_mask_cvtepi64_epi16(src, 0, a);
4444        assert_eq_m128i(r, src);
4445        let r = _mm512_mask_cvtepi64_epi16(src, 0b00001111, a);
4446        let e = _mm_set_epi16(-1, -1, -1, -1, 12, 13, 14, 15);
4447        assert_eq_m128i(r, e);
4448    }
4449
4450    #[simd_test(enable = "avx512f")]
4451    unsafe fn test_mm512_maskz_cvtepi64_epi16() {
4452        let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4453        let r = _mm512_maskz_cvtepi64_epi16(0, a);
4454        assert_eq_m128i(r, _mm_setzero_si128());
4455        let r = _mm512_maskz_cvtepi64_epi16(0b00001111, a);
4456        let e = _mm_set_epi16(0, 0, 0, 0, 12, 13, 14, 15);
4457        assert_eq_m128i(r, e);
4458    }
4459
4460    #[simd_test(enable = "avx512f,avx512vl")]
4461    unsafe fn test_mm256_cvtepi64_epi16() {
4462        let a = _mm256_set_epi64x(12, 13, 14, 15);
4463        let r = _mm256_cvtepi64_epi16(a);
4464        let e = _mm_set_epi16(0, 0, 0, 0, 12, 13, 14, 15);
4465        assert_eq_m128i(r, e);
4466    }
4467
4468    #[simd_test(enable = "avx512f,avx512vl")]
4469    unsafe fn test_mm256_mask_cvtepi64_epi16() {
4470        let a = _mm256_set_epi64x(12, 13, 14, 15);
4471        let src = _mm_set1_epi16(0);
4472        let r = _mm256_mask_cvtepi64_epi16(src, 0, a);
4473        assert_eq_m128i(r, src);
4474        let r = _mm256_mask_cvtepi64_epi16(src, 0b11111111, a);
4475        let e = _mm_set_epi16(0, 0, 0, 0, 12, 13, 14, 15);
4476        assert_eq_m128i(r, e);
4477    }
4478
4479    #[simd_test(enable = "avx512f,avx512vl")]
4480    unsafe fn test_mm256_maskz_cvtepi64_epi16() {
4481        let a = _mm256_set_epi64x(12, 13, 14, 15);
4482        let r = _mm256_maskz_cvtepi64_epi16(0, a);
4483        assert_eq_m128i(r, _mm_setzero_si128());
4484        let r = _mm256_maskz_cvtepi64_epi16(0b11111111, a);
4485        let e = _mm_set_epi16(0, 0, 0, 0, 12, 13, 14, 15);
4486        assert_eq_m128i(r, e);
4487    }
4488
4489    #[simd_test(enable = "avx512f,avx512vl")]
4490    unsafe fn test_mm_cvtepi64_epi16() {
4491        let a = _mm_set_epi64x(14, 15);
4492        let r = _mm_cvtepi64_epi16(a);
4493        let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 14, 15);
4494        assert_eq_m128i(r, e);
4495    }
4496
4497    #[simd_test(enable = "avx512f,avx512vl")]
4498    unsafe fn test_mm_mask_cvtepi64_epi16() {
4499        let a = _mm_set_epi64x(14, 15);
4500        let src = _mm_set1_epi16(0);
4501        let r = _mm_mask_cvtepi64_epi16(src, 0, a);
4502        assert_eq_m128i(r, src);
4503        let r = _mm_mask_cvtepi64_epi16(src, 0b11111111, a);
4504        let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 14, 15);
4505        assert_eq_m128i(r, e);
4506    }
4507
4508    #[simd_test(enable = "avx512f,avx512vl")]
4509    unsafe fn test_mm_maskz_cvtepi64_epi16() {
4510        let a = _mm_set_epi64x(14, 15);
4511        let r = _mm_maskz_cvtepi64_epi16(0, a);
4512        assert_eq_m128i(r, _mm_setzero_si128());
4513        let r = _mm_maskz_cvtepi64_epi16(0b11111111, a);
4514        let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 14, 15);
4515        assert_eq_m128i(r, e);
4516    }
4517
4518    #[simd_test(enable = "avx512f")]
4519    unsafe fn test_mm512_cvtepi64_epi8() {
4520        let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4521        let r = _mm512_cvtepi64_epi8(a);
4522        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 8, 9, 10, 11, 12, 13, 14, 15);
4523        assert_eq_m128i(r, e);
4524    }
4525
4526    #[simd_test(enable = "avx512f")]
4527    unsafe fn test_mm512_mask_cvtepi64_epi8() {
4528        let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4529        let src = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1);
4530        let r = _mm512_mask_cvtepi64_epi8(src, 0, a);
4531        assert_eq_m128i(r, src);
4532        let r = _mm512_mask_cvtepi64_epi8(src, 0b00001111, a);
4533        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, 12, 13, 14, 15);
4534        assert_eq_m128i(r, e);
4535    }
4536
4537    #[simd_test(enable = "avx512f")]
4538    unsafe fn test_mm512_maskz_cvtepi64_epi8() {
4539        let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4540        let r = _mm512_maskz_cvtepi64_epi8(0, a);
4541        assert_eq_m128i(r, _mm_setzero_si128());
4542        let r = _mm512_maskz_cvtepi64_epi8(0b00001111, a);
4543        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 13, 14, 15);
4544        assert_eq_m128i(r, e);
4545    }
4546
4547    #[simd_test(enable = "avx512f,avx512vl")]
4548    unsafe fn test_mm256_cvtepi64_epi8() {
4549        let a = _mm256_set_epi64x(12, 13, 14, 15);
4550        let r = _mm256_cvtepi64_epi8(a);
4551        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 13, 14, 15);
4552        assert_eq_m128i(r, e);
4553    }
4554
4555    #[simd_test(enable = "avx512f,avx512vl")]
4556    unsafe fn test_mm256_mask_cvtepi64_epi8() {
4557        let a = _mm256_set_epi64x(12, 13, 14, 15);
4558        let src = _mm_set1_epi8(0);
4559        let r = _mm256_mask_cvtepi64_epi8(src, 0, a);
4560        assert_eq_m128i(r, src);
4561        let r = _mm256_mask_cvtepi64_epi8(src, 0b00001111, a);
4562        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 13, 14, 15);
4563        assert_eq_m128i(r, e);
4564    }
4565
4566    #[simd_test(enable = "avx512f,avx512vl")]
4567    unsafe fn test_mm256_maskz_cvtepi64_epi8() {
4568        let a = _mm256_set_epi64x(12, 13, 14, 15);
4569        let r = _mm256_maskz_cvtepi64_epi8(0, a);
4570        assert_eq_m128i(r, _mm_setzero_si128());
4571        let r = _mm256_maskz_cvtepi64_epi8(0b00001111, a);
4572        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 13, 14, 15);
4573        assert_eq_m128i(r, e);
4574    }
4575
4576    #[simd_test(enable = "avx512f,avx512vl")]
4577    unsafe fn test_mm_cvtepi64_epi8() {
4578        let a = _mm_set_epi64x(14, 15);
4579        let r = _mm_cvtepi64_epi8(a);
4580        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 14, 15);
4581        assert_eq_m128i(r, e);
4582    }
4583
4584    #[simd_test(enable = "avx512f,avx512vl")]
4585    unsafe fn test_mm_mask_cvtepi64_epi8() {
4586        let a = _mm_set_epi64x(14, 15);
4587        let src = _mm_set1_epi8(0);
4588        let r = _mm_mask_cvtepi64_epi8(src, 0, a);
4589        assert_eq_m128i(r, src);
4590        let r = _mm_mask_cvtepi64_epi8(src, 0b00000011, a);
4591        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 14, 15);
4592        assert_eq_m128i(r, e);
4593    }
4594
4595    #[simd_test(enable = "avx512f,avx512vl")]
4596    unsafe fn test_mm_maskz_cvtepi64_epi8() {
4597        let a = _mm_set_epi64x(14, 15);
4598        let r = _mm_maskz_cvtepi64_epi8(0, a);
4599        assert_eq_m128i(r, _mm_setzero_si128());
4600        let r = _mm_maskz_cvtepi64_epi8(0b00000011, a);
4601        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 14, 15);
4602        assert_eq_m128i(r, e);
4603    }
4604
4605    #[simd_test(enable = "avx512f")]
4606    unsafe fn test_mm512_cvtsepi64_epi32() {
4607        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4608        let r = _mm512_cvtsepi64_epi32(a);
4609        let e = _mm256_set_epi32(0, 1, 2, 3, 4, 5, i32::MIN, i32::MAX);
4610        assert_eq_m256i(r, e);
4611    }
4612
4613    #[simd_test(enable = "avx512f")]
4614    unsafe fn test_mm512_mask_cvtsepi64_epi32() {
4615        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4616        let src = _mm256_set1_epi32(-1);
4617        let r = _mm512_mask_cvtsepi64_epi32(src, 0, a);
4618        assert_eq_m256i(r, src);
4619        let r = _mm512_mask_cvtsepi64_epi32(src, 0b00001111, a);
4620        let e = _mm256_set_epi32(-1, -1, -1, -1, 4, 5, i32::MIN, i32::MAX);
4621        assert_eq_m256i(r, e);
4622    }
4623
4624    #[simd_test(enable = "avx512f")]
4625    unsafe fn test_mm512_maskz_cvtsepi64_epi32() {
4626        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4627        let r = _mm512_maskz_cvtsepi64_epi32(0, a);
4628        assert_eq_m256i(r, _mm256_setzero_si256());
4629        let r = _mm512_maskz_cvtsepi64_epi32(0b00001111, a);
4630        let e = _mm256_set_epi32(0, 0, 0, 0, 4, 5, i32::MIN, i32::MAX);
4631        assert_eq_m256i(r, e);
4632    }
4633
4634    #[simd_test(enable = "avx512f,avx512vl")]
4635    unsafe fn test_mm256_cvtsepi64_epi32() {
4636        let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4637        let r = _mm256_cvtsepi64_epi32(a);
4638        let e = _mm_set_epi32(4, 5, i32::MIN, i32::MAX);
4639        assert_eq_m128i(r, e);
4640    }
4641
4642    #[simd_test(enable = "avx512f,avx512vl")]
4643    unsafe fn test_mm256_mask_cvtsepi64_epi32() {
4644        let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4645        let src = _mm_set1_epi32(-1);
4646        let r = _mm256_mask_cvtsepi64_epi32(src, 0, a);
4647        assert_eq_m128i(r, src);
4648        let r = _mm256_mask_cvtsepi64_epi32(src, 0b00001111, a);
4649        let e = _mm_set_epi32(4, 5, i32::MIN, i32::MAX);
4650        assert_eq_m128i(r, e);
4651    }
4652
4653    #[simd_test(enable = "avx512f,avx512vl")]
4654    unsafe fn test_mm256_maskz_cvtsepi64_epi32() {
4655        let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4656        let r = _mm256_maskz_cvtsepi64_epi32(0, a);
4657        assert_eq_m128i(r, _mm_setzero_si128());
4658        let r = _mm256_maskz_cvtsepi64_epi32(0b00001111, a);
4659        let e = _mm_set_epi32(4, 5, i32::MIN, i32::MAX);
4660        assert_eq_m128i(r, e);
4661    }
4662
4663    #[simd_test(enable = "avx512f,avx512vl")]
4664    unsafe fn test_mm_cvtsepi64_epi32() {
4665        let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4666        let r = _mm_cvtsepi64_epi32(a);
4667        let e = _mm_set_epi32(0, 0, i32::MIN, i32::MAX);
4668        assert_eq_m128i(r, e);
4669    }
4670
4671    #[simd_test(enable = "avx512f,avx512vl")]
4672    unsafe fn test_mm_mask_cvtsepi64_epi32() {
4673        let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4674        let src = _mm_set1_epi32(0);
4675        let r = _mm_mask_cvtsepi64_epi32(src, 0, a);
4676        assert_eq_m128i(r, src);
4677        let r = _mm_mask_cvtsepi64_epi32(src, 0b00000011, a);
4678        let e = _mm_set_epi32(0, 0, i32::MIN, i32::MAX);
4679        assert_eq_m128i(r, e);
4680    }
4681
4682    #[simd_test(enable = "avx512f,avx512vl")]
4683    unsafe fn test_mm_maskz_cvtsepi64_epi32() {
4684        let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4685        let r = _mm_maskz_cvtsepi64_epi32(0, a);
4686        assert_eq_m128i(r, _mm_setzero_si128());
4687        let r = _mm_maskz_cvtsepi64_epi32(0b00000011, a);
4688        let e = _mm_set_epi32(0, 0, i32::MIN, i32::MAX);
4689        assert_eq_m128i(r, e);
4690    }
4691
4692    #[simd_test(enable = "avx512f")]
4693    unsafe fn test_mm512_cvtsepi64_epi16() {
4694        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4695        let r = _mm512_cvtsepi64_epi16(a);
4696        let e = _mm_set_epi16(0, 1, 2, 3, 4, 5, i16::MIN, i16::MAX);
4697        assert_eq_m128i(r, e);
4698    }
4699
4700    #[simd_test(enable = "avx512f")]
4701    unsafe fn test_mm512_mask_cvtsepi64_epi16() {
4702        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4703        let src = _mm_set1_epi16(-1);
4704        let r = _mm512_mask_cvtsepi64_epi16(src, 0, a);
4705        assert_eq_m128i(r, src);
4706        let r = _mm512_mask_cvtsepi64_epi16(src, 0b00001111, a);
4707        let e = _mm_set_epi16(-1, -1, -1, -1, 4, 5, i16::MIN, i16::MAX);
4708        assert_eq_m128i(r, e);
4709    }
4710
4711    #[simd_test(enable = "avx512f")]
4712    unsafe fn test_mm512_maskz_cvtsepi64_epi16() {
4713        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4714        let r = _mm512_maskz_cvtsepi64_epi16(0, a);
4715        assert_eq_m128i(r, _mm_setzero_si128());
4716        let r = _mm512_maskz_cvtsepi64_epi16(0b00001111, a);
4717        let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, i16::MIN, i16::MAX);
4718        assert_eq_m128i(r, e);
4719    }
4720
4721    #[simd_test(enable = "avx512f,avx512vl")]
4722    unsafe fn test_mm256_cvtsepi64_epi16() {
4723        let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4724        let r = _mm256_cvtsepi64_epi16(a);
4725        let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, i16::MIN, i16::MAX);
4726        assert_eq_m128i(r, e);
4727    }
4728
4729    #[simd_test(enable = "avx512f,avx512vl")]
4730    unsafe fn test_mm256_mask_cvtsepi64_epi16() {
4731        let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4732        let src = _mm_set1_epi16(0);
4733        let r = _mm256_mask_cvtsepi64_epi16(src, 0, a);
4734        assert_eq_m128i(r, src);
4735        let r = _mm256_mask_cvtsepi64_epi16(src, 0b00001111, a);
4736        let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, i16::MIN, i16::MAX);
4737        assert_eq_m128i(r, e);
4738    }
4739
4740    #[simd_test(enable = "avx512f,avx512vl")]
4741    unsafe fn test_mm256_maskz_cvtsepi64_epi16() {
4742        let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4743        let r = _mm256_maskz_cvtsepi64_epi16(0, a);
4744        assert_eq_m128i(r, _mm_setzero_si128());
4745        let r = _mm256_maskz_cvtsepi64_epi16(0b00001111, a);
4746        let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, i16::MIN, i16::MAX);
4747        assert_eq_m128i(r, e);
4748    }
4749
4750    #[simd_test(enable = "avx512f,avx512vl")]
4751    unsafe fn test_mm_cvtsepi64_epi16() {
4752        let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4753        let r = _mm_cvtsepi64_epi16(a);
4754        let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, i16::MIN, i16::MAX);
4755        assert_eq_m128i(r, e);
4756    }
4757
4758    #[simd_test(enable = "avx512f,avx512vl")]
4759    unsafe fn test_mm_mask_cvtsepi64_epi16() {
4760        let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4761        let src = _mm_set1_epi16(0);
4762        let r = _mm_mask_cvtsepi64_epi16(src, 0, a);
4763        assert_eq_m128i(r, src);
4764        let r = _mm_mask_cvtsepi64_epi16(src, 0b00000011, a);
4765        let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, i16::MIN, i16::MAX);
4766        assert_eq_m128i(r, e);
4767    }
4768
4769    #[simd_test(enable = "avx512f,avx512vl")]
4770    unsafe fn test_mm_maskz_cvtsepi64_epi16() {
4771        let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4772        let r = _mm_maskz_cvtsepi64_epi16(0, a);
4773        assert_eq_m128i(r, _mm_setzero_si128());
4774        let r = _mm_maskz_cvtsepi64_epi16(0b00000011, a);
4775        let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, i16::MIN, i16::MAX);
4776        assert_eq_m128i(r, e);
4777    }
4778
4779    #[simd_test(enable = "avx512f")]
4780    unsafe fn test_mm512_cvtsepi64_epi8() {
4781        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4782        let r = _mm512_cvtsepi64_epi8(a);
4783        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, i8::MIN, i8::MAX);
4784        assert_eq_m128i(r, e);
4785    }
4786
4787    #[simd_test(enable = "avx512f")]
4788    unsafe fn test_mm512_mask_cvtsepi64_epi8() {
4789        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4790        let src = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1);
4791        let r = _mm512_mask_cvtsepi64_epi8(src, 0, a);
4792        assert_eq_m128i(r, src);
4793        let r = _mm512_mask_cvtsepi64_epi8(src, 0b00001111, a);
4794        #[rustfmt::skip]
4795        let e = _mm_set_epi8(
4796            0, 0, 0, 0,
4797            0, 0, 0, 0,
4798            -1, -1, -1, -1,
4799            4, 5, i8::MIN, i8::MAX,
4800        );
4801        assert_eq_m128i(r, e);
4802    }
4803
4804    #[simd_test(enable = "avx512f")]
4805    unsafe fn test_mm512_maskz_cvtsepi64_epi8() {
4806        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4807        let r = _mm512_maskz_cvtsepi64_epi8(0, a);
4808        assert_eq_m128i(r, _mm_setzero_si128());
4809        let r = _mm512_maskz_cvtsepi64_epi8(0b00001111, a);
4810        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, i8::MIN, i8::MAX);
4811        assert_eq_m128i(r, e);
4812    }
4813
4814    #[simd_test(enable = "avx512f,avx512vl")]
4815    unsafe fn test_mm256_cvtsepi64_epi8() {
4816        let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4817        let r = _mm256_cvtsepi64_epi8(a);
4818        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, i8::MIN, i8::MAX);
4819        assert_eq_m128i(r, e);
4820    }
4821
4822    #[simd_test(enable = "avx512f,avx512vl")]
4823    unsafe fn test_mm256_mask_cvtsepi64_epi8() {
4824        let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4825        let src = _mm_set1_epi8(0);
4826        let r = _mm256_mask_cvtsepi64_epi8(src, 0, a);
4827        assert_eq_m128i(r, src);
4828        let r = _mm256_mask_cvtsepi64_epi8(src, 0b00001111, a);
4829        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, i8::MIN, i8::MAX);
4830        assert_eq_m128i(r, e);
4831    }
4832
4833    #[simd_test(enable = "avx512f,avx512vl")]
4834    unsafe fn test_mm256_maskz_cvtsepi64_epi8() {
4835        let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4836        let r = _mm256_maskz_cvtsepi64_epi8(0, a);
4837        assert_eq_m128i(r, _mm_setzero_si128());
4838        let r = _mm256_maskz_cvtsepi64_epi8(0b00001111, a);
4839        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, i8::MIN, i8::MAX);
4840        assert_eq_m128i(r, e);
4841    }
4842
4843    #[simd_test(enable = "avx512f,avx512vl")]
4844    unsafe fn test_mm_cvtsepi64_epi8() {
4845        let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4846        let r = _mm_cvtsepi64_epi8(a);
4847        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MIN, i8::MAX);
4848        assert_eq_m128i(r, e);
4849    }
4850
4851    #[simd_test(enable = "avx512f,avx512vl")]
4852    unsafe fn test_mm_mask_cvtsepi64_epi8() {
4853        let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4854        let src = _mm_set1_epi8(0);
4855        let r = _mm_mask_cvtsepi64_epi8(src, 0, a);
4856        assert_eq_m128i(r, src);
4857        let r = _mm_mask_cvtsepi64_epi8(src, 0b00000011, a);
4858        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MIN, i8::MAX);
4859        assert_eq_m128i(r, e);
4860    }
4861
4862    #[simd_test(enable = "avx512f,avx512vl")]
4863    unsafe fn test_mm_maskz_cvtsepi64_epi8() {
4864        let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4865        let r = _mm_maskz_cvtsepi64_epi8(0, a);
4866        assert_eq_m128i(r, _mm_setzero_si128());
4867        let r = _mm_maskz_cvtsepi64_epi8(0b00000011, a);
4868        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MIN, i8::MAX);
4869        assert_eq_m128i(r, e);
4870    }
4871
4872    #[simd_test(enable = "avx512f")]
4873    unsafe fn test_mm512_cvtusepi64_epi32() {
4874        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
4875        let r = _mm512_cvtusepi64_epi32(a);
4876        let e = _mm256_set_epi32(0, 1, 2, 3, 4, 5, -1, -1);
4877        assert_eq_m256i(r, e);
4878    }
4879
4880    #[simd_test(enable = "avx512f")]
4881    unsafe fn test_mm512_mask_cvtusepi64_epi32() {
4882        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
4883        let src = _mm256_set1_epi32(-1);
4884        let r = _mm512_mask_cvtusepi64_epi32(src, 0, a);
4885        assert_eq_m256i(r, src);
4886        let r = _mm512_mask_cvtusepi64_epi32(src, 0b00001111, a);
4887        let e = _mm256_set_epi32(-1, -1, -1, -1, 4, 5, -1, -1);
4888        assert_eq_m256i(r, e);
4889    }
4890
4891    #[simd_test(enable = "avx512f")]
4892    unsafe fn test_mm512_maskz_cvtusepi64_epi32() {
4893        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
4894        let r = _mm512_maskz_cvtusepi64_epi32(0, a);
4895        assert_eq_m256i(r, _mm256_setzero_si256());
4896        let r = _mm512_maskz_cvtusepi64_epi32(0b00001111, a);
4897        let e = _mm256_set_epi32(0, 0, 0, 0, 4, 5, -1, -1);
4898        assert_eq_m256i(r, e);
4899    }
4900
4901    #[simd_test(enable = "avx512f,avx512vl")]
4902    unsafe fn test_mm256_cvtusepi64_epi32() {
4903        let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
4904        let r = _mm256_cvtusepi64_epi32(a);
4905        let e = _mm_set_epi32(4, 5, 6, u32::MAX as i32);
4906        assert_eq_m128i(r, e);
4907    }
4908
4909    #[simd_test(enable = "avx512f,avx512vl")]
4910    unsafe fn test_mm256_mask_cvtusepi64_epi32() {
4911        let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
4912        let src = _mm_set1_epi32(0);
4913        let r = _mm256_mask_cvtusepi64_epi32(src, 0, a);
4914        assert_eq_m128i(r, src);
4915        let r = _mm256_mask_cvtusepi64_epi32(src, 0b00001111, a);
4916        let e = _mm_set_epi32(4, 5, 6, u32::MAX as i32);
4917        assert_eq_m128i(r, e);
4918    }
4919
4920    #[simd_test(enable = "avx512f,avx512vl")]
4921    unsafe fn test_mm256_maskz_cvtusepi64_epi32() {
4922        let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
4923        let r = _mm256_maskz_cvtusepi64_epi32(0, a);
4924        assert_eq_m128i(r, _mm_setzero_si128());
4925        let r = _mm256_maskz_cvtusepi64_epi32(0b00001111, a);
4926        let e = _mm_set_epi32(4, 5, 6, u32::MAX as i32);
4927        assert_eq_m128i(r, e);
4928    }
4929
4930    #[simd_test(enable = "avx512f,avx512vl")]
4931    unsafe fn test_mm_cvtusepi64_epi32() {
4932        let a = _mm_set_epi64x(6, i64::MAX);
4933        let r = _mm_cvtusepi64_epi32(a);
4934        let e = _mm_set_epi32(0, 0, 6, u32::MAX as i32);
4935        assert_eq_m128i(r, e);
4936    }
4937
4938    #[simd_test(enable = "avx512f,avx512vl")]
4939    unsafe fn test_mm_mask_cvtusepi64_epi32() {
4940        let a = _mm_set_epi64x(6, i64::MAX);
4941        let src = _mm_set1_epi32(0);
4942        let r = _mm_mask_cvtusepi64_epi32(src, 0, a);
4943        assert_eq_m128i(r, src);
4944        let r = _mm_mask_cvtusepi64_epi32(src, 0b00000011, a);
4945        let e = _mm_set_epi32(0, 0, 6, u32::MAX as i32);
4946        assert_eq_m128i(r, e);
4947    }
4948
4949    #[simd_test(enable = "avx512f,avx512vl")]
4950    unsafe fn test_mm_maskz_cvtusepi64_epi32() {
4951        let a = _mm_set_epi64x(6, i64::MAX);
4952        let r = _mm_maskz_cvtusepi64_epi32(0, a);
4953        assert_eq_m128i(r, _mm_setzero_si128());
4954        let r = _mm_maskz_cvtusepi64_epi32(0b00000011, a);
4955        let e = _mm_set_epi32(0, 0, 6, u32::MAX as i32);
4956        assert_eq_m128i(r, e);
4957    }
4958
4959    #[simd_test(enable = "avx512f")]
4960    unsafe fn test_mm512_cvtusepi64_epi16() {
4961        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
4962        let r = _mm512_cvtusepi64_epi16(a);
4963        let e = _mm_set_epi16(0, 1, 2, 3, 4, 5, -1, -1);
4964        assert_eq_m128i(r, e);
4965    }
4966
4967    #[simd_test(enable = "avx512f")]
4968    unsafe fn test_mm512_mask_cvtusepi64_epi16() {
4969        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
4970        let src = _mm_set1_epi16(-1);
4971        let r = _mm512_mask_cvtusepi64_epi16(src, 0, a);
4972        assert_eq_m128i(r, src);
4973        let r = _mm512_mask_cvtusepi64_epi16(src, 0b00001111, a);
4974        let e = _mm_set_epi16(-1, -1, -1, -1, 4, 5, -1, -1);
4975        assert_eq_m128i(r, e);
4976    }
4977
4978    #[simd_test(enable = "avx512f")]
4979    unsafe fn test_mm512_maskz_cvtusepi64_epi16() {
4980        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
4981        let r = _mm512_maskz_cvtusepi64_epi16(0, a);
4982        assert_eq_m128i(r, _mm_setzero_si128());
4983        let r = _mm512_maskz_cvtusepi64_epi16(0b00001111, a);
4984        let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, -1, -1);
4985        assert_eq_m128i(r, e);
4986    }
4987
4988    #[simd_test(enable = "avx512f,avx512vl")]
4989    unsafe fn test_mm256_cvtusepi64_epi16() {
4990        let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
4991        let r = _mm256_cvtusepi64_epi16(a);
4992        let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, 6, u16::MAX as i16);
4993        assert_eq_m128i(r, e);
4994    }
4995
4996    #[simd_test(enable = "avx512f,avx512vl")]
4997    unsafe fn test_mm256_mask_cvtusepi64_epi16() {
4998        let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
4999        let src = _mm_set1_epi16(0);
5000        let r = _mm256_mask_cvtusepi64_epi16(src, 0, a);
5001        assert_eq_m128i(r, src);
5002        let r = _mm256_mask_cvtusepi64_epi16(src, 0b00001111, a);
5003        let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, 6, u16::MAX as i16);
5004        assert_eq_m128i(r, e);
5005    }
5006
5007    #[simd_test(enable = "avx512f,avx512vl")]
5008    unsafe fn test_mm256_maskz_cvtusepi64_epi16() {
5009        let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
5010        let r = _mm256_maskz_cvtusepi64_epi16(0, a);
5011        assert_eq_m128i(r, _mm_setzero_si128());
5012        let r = _mm256_maskz_cvtusepi64_epi16(0b00001111, a);
5013        let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, 6, u16::MAX as i16);
5014        assert_eq_m128i(r, e);
5015    }
5016
5017    #[simd_test(enable = "avx512f,avx512vl")]
5018    unsafe fn test_mm_cvtusepi64_epi16() {
5019        let a = _mm_set_epi64x(6, i64::MAX);
5020        let r = _mm_cvtusepi64_epi16(a);
5021        let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 6, u16::MAX as i16);
5022        assert_eq_m128i(r, e);
5023    }
5024
5025    #[simd_test(enable = "avx512f,avx512vl")]
5026    unsafe fn test_mm_mask_cvtusepi64_epi16() {
5027        let a = _mm_set_epi64x(6, i64::MAX);
5028        let src = _mm_set1_epi16(0);
5029        let r = _mm_mask_cvtusepi64_epi16(src, 0, a);
5030        assert_eq_m128i(r, src);
5031        let r = _mm_mask_cvtusepi64_epi16(src, 0b00000011, a);
5032        let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 6, u16::MAX as i16);
5033        assert_eq_m128i(r, e);
5034    }
5035
5036    #[simd_test(enable = "avx512f,avx512vl")]
5037    unsafe fn test_mm_maskz_cvtusepi64_epi16() {
5038        let a = _mm_set_epi64x(6, i64::MAX);
5039        let r = _mm_maskz_cvtusepi64_epi16(0, a);
5040        assert_eq_m128i(r, _mm_setzero_si128());
5041        let r = _mm_maskz_cvtusepi64_epi16(0b00000011, a);
5042        let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 6, u16::MAX as i16);
5043        assert_eq_m128i(r, e);
5044    }
5045
5046    #[simd_test(enable = "avx512f")]
5047    unsafe fn test_mm512_cvtusepi64_epi8() {
5048        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
5049        let r = _mm512_cvtusepi64_epi8(a);
5050        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, -1, -1);
5051        assert_eq_m128i(r, e);
5052    }
5053
5054    #[simd_test(enable = "avx512f")]
5055    unsafe fn test_mm512_mask_cvtusepi64_epi8() {
5056        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
5057        let src = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1);
5058        let r = _mm512_mask_cvtusepi64_epi8(src, 0, a);
5059        assert_eq_m128i(r, src);
5060        let r = _mm512_mask_cvtusepi64_epi8(src, 0b00001111, a);
5061        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, 4, 5, -1, -1);
5062        assert_eq_m128i(r, e);
5063    }
5064
5065    #[simd_test(enable = "avx512f")]
5066    unsafe fn test_mm512_maskz_cvtusepi64_epi8() {
5067        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
5068        let r = _mm512_maskz_cvtusepi64_epi8(0, a);
5069        assert_eq_m128i(r, _mm_setzero_si128());
5070        let r = _mm512_maskz_cvtusepi64_epi8(0b00001111, a);
5071        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, -1, -1);
5072        assert_eq_m128i(r, e);
5073    }
5074
5075    #[simd_test(enable = "avx512f,avx512vl")]
5076    unsafe fn test_mm256_cvtusepi64_epi8() {
5077        let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
5078        let r = _mm256_cvtusepi64_epi8(a);
5079        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, 6, u8::MAX as i8);
5080        assert_eq_m128i(r, e);
5081    }
5082
5083    #[simd_test(enable = "avx512f,avx512vl")]
5084    unsafe fn test_mm256_mask_cvtusepi64_epi8() {
5085        let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
5086        let src = _mm_set1_epi8(0);
5087        let r = _mm256_mask_cvtusepi64_epi8(src, 0, a);
5088        assert_eq_m128i(r, src);
5089        let r = _mm256_mask_cvtusepi64_epi8(src, 0b00001111, a);
5090        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, 6, u8::MAX as i8);
5091        assert_eq_m128i(r, e);
5092    }
5093
5094    #[simd_test(enable = "avx512f,avx512vl")]
5095    unsafe fn test_mm256_maskz_cvtusepi64_epi8() {
5096        let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
5097        let r = _mm256_maskz_cvtusepi64_epi8(0, a);
5098        assert_eq_m128i(r, _mm_setzero_si128());
5099        let r = _mm256_maskz_cvtusepi64_epi8(0b00001111, a);
5100        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, 6, u8::MAX as i8);
5101        assert_eq_m128i(r, e);
5102    }
5103
5104    #[simd_test(enable = "avx512f,avx512vl")]
5105    unsafe fn test_mm_cvtusepi64_epi8() {
5106        let a = _mm_set_epi64x(6, i64::MAX);
5107        let r = _mm_cvtusepi64_epi8(a);
5108        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, u8::MAX as i8);
5109        assert_eq_m128i(r, e);
5110    }
5111
5112    #[simd_test(enable = "avx512f,avx512vl")]
5113    unsafe fn test_mm_mask_cvtusepi64_epi8() {
5114        let a = _mm_set_epi64x(6, i64::MAX);
5115        let src = _mm_set1_epi8(0);
5116        let r = _mm_mask_cvtusepi64_epi8(src, 0, a);
5117        assert_eq_m128i(r, src);
5118        let r = _mm_mask_cvtusepi64_epi8(src, 0b00000011, a);
5119        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, u8::MAX as i8);
5120        assert_eq_m128i(r, e);
5121    }
5122
5123    #[simd_test(enable = "avx512f,avx512vl")]
5124    unsafe fn test_mm_maskz_cvtusepi64_epi8() {
5125        let a = _mm_set_epi64x(6, i64::MAX);
5126        let r = _mm_maskz_cvtusepi64_epi8(0, a);
5127        assert_eq_m128i(r, _mm_setzero_si128());
5128        let r = _mm_maskz_cvtusepi64_epi8(0b00000011, a);
5129        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, u8::MAX as i8);
5130        assert_eq_m128i(r, e);
5131    }
5132
5133    #[simd_test(enable = "avx512f")]
5134    unsafe fn test_mm512_cvtt_roundpd_epi32() {
5135        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5136        let r = _mm512_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(a);
5137        let e = _mm256_setr_epi32(0, -1, 2, -3, 4, -5, 6, -7);
5138        assert_eq_m256i(r, e);
5139    }
5140
5141    #[simd_test(enable = "avx512f")]
5142    unsafe fn test_mm512_mask_cvtt_roundpd_epi32() {
5143        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5144        let src = _mm256_set1_epi32(0);
5145        let r = _mm512_mask_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(src, 0, a);
5146        assert_eq_m256i(r, src);
5147        let r = _mm512_mask_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(src, 0b00001111, a);
5148        let e = _mm256_setr_epi32(0, -1, 2, -3, 0, 0, 0, 0);
5149        assert_eq_m256i(r, e);
5150    }
5151
5152    #[simd_test(enable = "avx512f")]
5153    unsafe fn test_mm512_maskz_cvtt_roundpd_epi32() {
5154        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5155        let r = _mm512_maskz_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(0, a);
5156        assert_eq_m256i(r, _mm256_setzero_si256());
5157        let r = _mm512_maskz_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(0b00001111, a);
5158        let e = _mm256_setr_epi32(0, -1, 2, -3, 0, 0, 0, 0);
5159        assert_eq_m256i(r, e);
5160    }
5161
5162    #[simd_test(enable = "avx512f")]
5163    unsafe fn test_mm512_cvtt_roundpd_epu32() {
5164        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5165        let r = _mm512_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(a);
5166        let e = _mm256_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1);
5167        assert_eq_m256i(r, e);
5168    }
5169
5170    #[simd_test(enable = "avx512f")]
5171    unsafe fn test_mm512_mask_cvtt_roundpd_epu32() {
5172        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5173        let src = _mm256_set1_epi32(0);
5174        let r = _mm512_mask_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(src, 0, a);
5175        assert_eq_m256i(r, src);
5176        let r = _mm512_mask_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(src, 0b00001111, a);
5177        let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
5178        assert_eq_m256i(r, e);
5179    }
5180
5181    #[simd_test(enable = "avx512f")]
5182    unsafe fn test_mm512_maskz_cvtt_roundpd_epu32() {
5183        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5184        let r = _mm512_maskz_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(0, a);
5185        assert_eq_m256i(r, _mm256_setzero_si256());
5186        let r = _mm512_maskz_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(0b00001111, a);
5187        let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
5188        assert_eq_m256i(r, e);
5189    }
5190
5191    #[simd_test(enable = "avx512f")]
5192    unsafe fn test_mm512_cvttpd_epi32() {
5193        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5194        let r = _mm512_cvttpd_epi32(a);
5195        let e = _mm256_setr_epi32(0, -1, 2, -3, 4, -5, 6, -7);
5196        assert_eq_m256i(r, e);
5197    }
5198
5199    #[simd_test(enable = "avx512f")]
5200    unsafe fn test_mm512_mask_cvttpd_epi32() {
5201        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5202        let src = _mm256_set1_epi32(0);
5203        let r = _mm512_mask_cvttpd_epi32(src, 0, a);
5204        assert_eq_m256i(r, src);
5205        let r = _mm512_mask_cvttpd_epi32(src, 0b00001111, a);
5206        let e = _mm256_setr_epi32(0, -1, 2, -3, 0, 0, 0, 0);
5207        assert_eq_m256i(r, e);
5208    }
5209
5210    #[simd_test(enable = "avx512f")]
5211    unsafe fn test_mm512_maskz_cvttpd_epi32() {
5212        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5213        let r = _mm512_maskz_cvttpd_epi32(0, a);
5214        assert_eq_m256i(r, _mm256_setzero_si256());
5215        let r = _mm512_maskz_cvttpd_epi32(0b00001111, a);
5216        let e = _mm256_setr_epi32(0, -1, 2, -3, 0, 0, 0, 0);
5217        assert_eq_m256i(r, e);
5218    }
5219
5220    #[simd_test(enable = "avx512f,avx512vl")]
5221    unsafe fn test_mm256_mask_cvttpd_epi32() {
5222        let a = _mm256_setr_pd(4., -5.5, 6., -7.5);
5223        let src = _mm_set1_epi32(0);
5224        let r = _mm256_mask_cvttpd_epi32(src, 0, a);
5225        assert_eq_m128i(r, src);
5226        let r = _mm256_mask_cvttpd_epi32(src, 0b00001111, a);
5227        let e = _mm_setr_epi32(4, -5, 6, -7);
5228        assert_eq_m128i(r, e);
5229    }
5230
5231    #[simd_test(enable = "avx512f,avx512vl")]
5232    unsafe fn test_mm256_maskz_cvttpd_epi32() {
5233        let a = _mm256_setr_pd(4., -5.5, 6., -7.5);
5234        let r = _mm256_maskz_cvttpd_epi32(0, a);
5235        assert_eq_m128i(r, _mm_setzero_si128());
5236        let r = _mm256_maskz_cvttpd_epi32(0b00001111, a);
5237        let e = _mm_setr_epi32(4, -5, 6, -7);
5238        assert_eq_m128i(r, e);
5239    }
5240
5241    #[simd_test(enable = "avx512f,avx512vl")]
5242    unsafe fn test_mm_mask_cvttpd_epi32() {
5243        let a = _mm_set_pd(6., -7.5);
5244        let src = _mm_set1_epi32(0);
5245        let r = _mm_mask_cvttpd_epi32(src, 0, a);
5246        assert_eq_m128i(r, src);
5247        let r = _mm_mask_cvttpd_epi32(src, 0b00000011, a);
5248        let e = _mm_set_epi32(0, 0, 6, -7);
5249        assert_eq_m128i(r, e);
5250    }
5251
5252    #[simd_test(enable = "avx512f,avx512vl")]
5253    unsafe fn test_mm_maskz_cvttpd_epi32() {
5254        let a = _mm_set_pd(6., -7.5);
5255        let r = _mm_maskz_cvttpd_epi32(0, a);
5256        assert_eq_m128i(r, _mm_setzero_si128());
5257        let r = _mm_maskz_cvttpd_epi32(0b00000011, a);
5258        let e = _mm_set_epi32(0, 0, 6, -7);
5259        assert_eq_m128i(r, e);
5260    }
5261
5262    #[simd_test(enable = "avx512f")]
5263    unsafe fn test_mm512_cvttpd_epu32() {
5264        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5265        let r = _mm512_cvttpd_epu32(a);
5266        let e = _mm256_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1);
5267        assert_eq_m256i(r, e);
5268    }
5269
5270    #[simd_test(enable = "avx512f")]
5271    unsafe fn test_mm512_mask_cvttpd_epu32() {
5272        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5273        let src = _mm256_set1_epi32(0);
5274        let r = _mm512_mask_cvttpd_epu32(src, 0, a);
5275        assert_eq_m256i(r, src);
5276        let r = _mm512_mask_cvttpd_epu32(src, 0b00001111, a);
5277        let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
5278        assert_eq_m256i(r, e);
5279    }
5280
5281    #[simd_test(enable = "avx512f")]
5282    unsafe fn test_mm512_maskz_cvttpd_epu32() {
5283        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5284        let r = _mm512_maskz_cvttpd_epu32(0, a);
5285        assert_eq_m256i(r, _mm256_setzero_si256());
5286        let r = _mm512_maskz_cvttpd_epu32(0b00001111, a);
5287        let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
5288        assert_eq_m256i(r, e);
5289    }
5290
5291    #[simd_test(enable = "avx512f,avx512vl")]
5292    unsafe fn test_mm256_cvttpd_epu32() {
5293        let a = _mm256_set_pd(4., 5.5, 6., 7.5);
5294        let r = _mm256_cvttpd_epu32(a);
5295        let e = _mm_set_epi32(4, 5, 6, 7);
5296        assert_eq_m128i(r, e);
5297    }
5298
5299    #[simd_test(enable = "avx512f,avx512vl")]
5300    unsafe fn test_mm256_mask_cvttpd_epu32() {
5301        let a = _mm256_set_pd(4., 5.5, 6., 7.5);
5302        let src = _mm_set1_epi32(0);
5303        let r = _mm256_mask_cvttpd_epu32(src, 0, a);
5304        assert_eq_m128i(r, src);
5305        let r = _mm256_mask_cvttpd_epu32(src, 0b00001111, a);
5306        let e = _mm_set_epi32(4, 5, 6, 7);
5307        assert_eq_m128i(r, e);
5308    }
5309
5310    #[simd_test(enable = "avx512f,avx512vl")]
5311    unsafe fn test_mm256_maskz_cvttpd_epu32() {
5312        let a = _mm256_set_pd(4., 5.5, 6., 7.5);
5313        let r = _mm256_maskz_cvttpd_epu32(0, a);
5314        assert_eq_m128i(r, _mm_setzero_si128());
5315        let r = _mm256_maskz_cvttpd_epu32(0b00001111, a);
5316        let e = _mm_set_epi32(4, 5, 6, 7);
5317        assert_eq_m128i(r, e);
5318    }
5319
5320    #[simd_test(enable = "avx512f,avx512vl")]
5321    unsafe fn test_mm_cvttpd_epu32() {
5322        let a = _mm_set_pd(6., 7.5);
5323        let r = _mm_cvttpd_epu32(a);
5324        let e = _mm_set_epi32(0, 0, 6, 7);
5325        assert_eq_m128i(r, e);
5326    }
5327
5328    #[simd_test(enable = "avx512f,avx512vl")]
5329    unsafe fn test_mm_mask_cvttpd_epu32() {
5330        let a = _mm_set_pd(6., 7.5);
5331        let src = _mm_set1_epi32(0);
5332        let r = _mm_mask_cvttpd_epu32(src, 0, a);
5333        assert_eq_m128i(r, src);
5334        let r = _mm_mask_cvttpd_epu32(src, 0b00000011, a);
5335        let e = _mm_set_epi32(0, 0, 6, 7);
5336        assert_eq_m128i(r, e);
5337    }
5338
5339    #[simd_test(enable = "avx512f,avx512vl")]
5340    unsafe fn test_mm_maskz_cvttpd_epu32() {
5341        let a = _mm_set_pd(6., 7.5);
5342        let r = _mm_maskz_cvttpd_epu32(0, a);
5343        assert_eq_m128i(r, _mm_setzero_si128());
5344        let r = _mm_maskz_cvttpd_epu32(0b00000011, a);
5345        let e = _mm_set_epi32(0, 0, 6, 7);
5346        assert_eq_m128i(r, e);
5347    }
5348
5349    #[simd_test(enable = "avx512f")]
5350    unsafe fn test_mm512_add_round_pd() {
5351        let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5352        let b = _mm512_set1_pd(-1.);
5353        let r = _mm512_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
5354        let e = _mm512_setr_pd(7., 8.5, 9., 10.5, 11., 12.5, 13., -1.0);
5355        assert_eq_m512d(r, e);
5356        let r = _mm512_add_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
5357        let e = _mm512_setr_pd(7., 8.5, 9., 10.5, 11., 12.5, 13., -0.9999999999999999);
5358        assert_eq_m512d(r, e);
5359    }
5360
5361    #[simd_test(enable = "avx512f")]
5362    unsafe fn test_mm512_mask_add_round_pd() {
5363        let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5364        let b = _mm512_set1_pd(-1.);
5365        let r = _mm512_mask_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5366            a, 0, a, b,
5367        );
5368        assert_eq_m512d(r, a);
5369        let r = _mm512_mask_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5370            a, 0b11110000, a, b,
5371        );
5372        let e = _mm512_setr_pd(8., 9.5, 10., 11.5, 11., 12.5, 13., -1.0);
5373        assert_eq_m512d(r, e);
5374    }
5375
5376    #[simd_test(enable = "avx512f")]
5377    unsafe fn test_mm512_maskz_add_round_pd() {
5378        let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5379        let b = _mm512_set1_pd(-1.);
5380        let r =
5381            _mm512_maskz_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
5382        assert_eq_m512d(r, _mm512_setzero_pd());
5383        let r = _mm512_maskz_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5384            0b11110000, a, b,
5385        );
5386        let e = _mm512_setr_pd(0., 0., 0., 0., 11., 12.5, 13., -1.0);
5387        assert_eq_m512d(r, e);
5388    }
5389
5390    #[simd_test(enable = "avx512f")]
5391    unsafe fn test_mm512_sub_round_pd() {
5392        let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5393        let b = _mm512_set1_pd(1.);
5394        let r = _mm512_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
5395        let e = _mm512_setr_pd(7., 8.5, 9., 10.5, 11., 12.5, 13., -1.0);
5396        assert_eq_m512d(r, e);
5397        let r = _mm512_sub_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
5398        let e = _mm512_setr_pd(7., 8.5, 9., 10.5, 11., 12.5, 13., -0.9999999999999999);
5399        assert_eq_m512d(r, e);
5400    }
5401
5402    #[simd_test(enable = "avx512f")]
5403    unsafe fn test_mm512_mask_sub_round_pd() {
5404        let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5405        let b = _mm512_set1_pd(1.);
5406        let r = _mm512_mask_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5407            a, 0, a, b,
5408        );
5409        assert_eq_m512d(r, a);
5410        let r = _mm512_mask_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5411            a, 0b11110000, a, b,
5412        );
5413        let e = _mm512_setr_pd(8., 9.5, 10., 11.5, 11., 12.5, 13., -1.0);
5414        assert_eq_m512d(r, e);
5415    }
5416
5417    #[simd_test(enable = "avx512f")]
5418    unsafe fn test_mm512_maskz_sub_round_pd() {
5419        let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5420        let b = _mm512_set1_pd(1.);
5421        let r =
5422            _mm512_maskz_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
5423        assert_eq_m512d(r, _mm512_setzero_pd());
5424        let r = _mm512_maskz_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5425            0b11110000, a, b,
5426        );
5427        let e = _mm512_setr_pd(0., 0., 0., 0., 11., 12.5, 13., -1.0);
5428        assert_eq_m512d(r, e);
5429    }
5430
5431    #[simd_test(enable = "avx512f")]
5432    unsafe fn test_mm512_mul_round_pd() {
5433        let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.);
5434        let b = _mm512_set1_pd(0.1);
5435        let r = _mm512_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
5436        let e = _mm512_setr_pd(
5437            0.8,
5438            0.9500000000000001,
5439            1.,
5440            1.1500000000000001,
5441            1.2000000000000002,
5442            1.35,
5443            1.4000000000000001,
5444            0.,
5445        );
5446        assert_eq_m512d(r, e);
5447        let r = _mm512_mul_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
5448        let e = _mm512_setr_pd(0.8, 0.95, 1.0, 1.15, 1.2, 1.3499999999999999, 1.4, 0.0);
5449        assert_eq_m512d(r, e);
5450    }
5451
5452    #[simd_test(enable = "avx512f")]
5453    unsafe fn test_mm512_mask_mul_round_pd() {
5454        let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.);
5455        let b = _mm512_set1_pd(0.1);
5456        let r = _mm512_mask_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5457            a, 0, a, b,
5458        );
5459        assert_eq_m512d(r, a);
5460        let r = _mm512_mask_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5461            a, 0b11110000, a, b,
5462        );
5463        let e = _mm512_setr_pd(
5464            8.,
5465            9.5,
5466            10.,
5467            11.5,
5468            1.2000000000000002,
5469            1.35,
5470            1.4000000000000001,
5471            0.,
5472        );
5473        assert_eq_m512d(r, e);
5474    }
5475
5476    #[simd_test(enable = "avx512f")]
5477    unsafe fn test_mm512_maskz_mul_round_pd() {
5478        let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.);
5479        let b = _mm512_set1_pd(0.1);
5480        let r =
5481            _mm512_maskz_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
5482        assert_eq_m512d(r, _mm512_setzero_pd());
5483        let r = _mm512_maskz_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5484            0b11110000, a, b,
5485        );
5486        let e = _mm512_setr_pd(
5487            0.,
5488            0.,
5489            0.,
5490            0.,
5491            1.2000000000000002,
5492            1.35,
5493            1.4000000000000001,
5494            0.,
5495        );
5496        assert_eq_m512d(r, e);
5497    }
5498
5499    #[simd_test(enable = "avx512f")]
5500    unsafe fn test_mm512_div_round_pd() {
5501        let a = _mm512_set1_pd(1.);
5502        let b = _mm512_set1_pd(3.);
5503        let r = _mm512_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
5504        let e = _mm512_set1_pd(0.3333333333333333);
5505        assert_eq_m512d(r, e);
5506        let r = _mm512_div_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
5507        let e = _mm512_set1_pd(0.3333333333333333);
5508        assert_eq_m512d(r, e);
5509    }
5510
5511    #[simd_test(enable = "avx512f")]
5512    unsafe fn test_mm512_mask_div_round_pd() {
5513        let a = _mm512_set1_pd(1.);
5514        let b = _mm512_set1_pd(3.);
5515        let r = _mm512_mask_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5516            a, 0, a, b,
5517        );
5518        assert_eq_m512d(r, a);
5519        let r = _mm512_mask_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5520            a, 0b11110000, a, b,
5521        );
5522        let e = _mm512_setr_pd(
5523            1.,
5524            1.,
5525            1.,
5526            1.,
5527            0.3333333333333333,
5528            0.3333333333333333,
5529            0.3333333333333333,
5530            0.3333333333333333,
5531        );
5532        assert_eq_m512d(r, e);
5533    }
5534
5535    #[simd_test(enable = "avx512f")]
5536    unsafe fn test_mm512_maskz_div_round_pd() {
5537        let a = _mm512_set1_pd(1.);
5538        let b = _mm512_set1_pd(3.);
5539        let r =
5540            _mm512_maskz_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
5541        assert_eq_m512d(r, _mm512_setzero_pd());
5542        let r = _mm512_maskz_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5543            0b11110000, a, b,
5544        );
5545        let e = _mm512_setr_pd(
5546            0.,
5547            0.,
5548            0.,
5549            0.,
5550            0.3333333333333333,
5551            0.3333333333333333,
5552            0.3333333333333333,
5553            0.3333333333333333,
5554        );
5555        assert_eq_m512d(r, e);
5556    }
5557
5558    #[simd_test(enable = "avx512f")]
5559    unsafe fn test_mm512_sqrt_round_pd() {
5560        let a = _mm512_set1_pd(3.);
5561        let r = _mm512_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
5562        let e = _mm512_set1_pd(1.7320508075688772);
5563        assert_eq_m512d(r, e);
5564        let r = _mm512_sqrt_round_pd::<{ _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC }>(a);
5565        let e = _mm512_set1_pd(1.7320508075688774);
5566        assert_eq_m512d(r, e);
5567    }
5568
5569    #[simd_test(enable = "avx512f")]
5570    unsafe fn test_mm512_mask_sqrt_round_pd() {
5571        let a = _mm512_set1_pd(3.);
5572        let r =
5573            _mm512_mask_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, 0, a);
5574        assert_eq_m512d(r, a);
5575        let r = _mm512_mask_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5576            a, 0b11110000, a,
5577        );
5578        let e = _mm512_setr_pd(
5579            3.,
5580            3.,
5581            3.,
5582            3.,
5583            1.7320508075688772,
5584            1.7320508075688772,
5585            1.7320508075688772,
5586            1.7320508075688772,
5587        );
5588        assert_eq_m512d(r, e);
5589    }
5590
5591    #[simd_test(enable = "avx512f")]
5592    unsafe fn test_mm512_maskz_sqrt_round_pd() {
5593        let a = _mm512_set1_pd(3.);
5594        let r =
5595            _mm512_maskz_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a);
5596        assert_eq_m512d(r, _mm512_setzero_pd());
5597        let r = _mm512_maskz_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5598            0b11110000, a,
5599        );
5600        let e = _mm512_setr_pd(
5601            0.,
5602            0.,
5603            0.,
5604            0.,
5605            1.7320508075688772,
5606            1.7320508075688772,
5607            1.7320508075688772,
5608            1.7320508075688772,
5609        );
5610        assert_eq_m512d(r, e);
5611    }
5612
5613    #[simd_test(enable = "avx512f")]
5614    unsafe fn test_mm512_fmadd_round_pd() {
5615        let a = _mm512_set1_pd(0.000000000000000007);
5616        let b = _mm512_set1_pd(1.);
5617        let c = _mm512_set1_pd(-1.);
5618        let r = _mm512_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5619        let e = _mm512_set1_pd(-1.);
5620        assert_eq_m512d(r, e);
5621        let r = _mm512_fmadd_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5622        let e = _mm512_set1_pd(-0.9999999999999999);
5623        assert_eq_m512d(r, e);
5624    }
5625
5626    #[simd_test(enable = "avx512f")]
5627    unsafe fn test_mm512_mask_fmadd_round_pd() {
5628        let a = _mm512_set1_pd(0.000000000000000007);
5629        let b = _mm512_set1_pd(1.);
5630        let c = _mm512_set1_pd(-1.);
5631        let r = _mm512_mask_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5632            a, 0, b, c,
5633        );
5634        assert_eq_m512d(r, a);
5635        let r = _mm512_mask_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5636            a, 0b00001111, b, c,
5637        );
5638        let e = _mm512_setr_pd(
5639            -1.,
5640            -1.,
5641            -1.,
5642            -1.,
5643            0.000000000000000007,
5644            0.000000000000000007,
5645            0.000000000000000007,
5646            0.000000000000000007,
5647        );
5648        assert_eq_m512d(r, e);
5649    }
5650
5651    #[simd_test(enable = "avx512f")]
5652    unsafe fn test_mm512_maskz_fmadd_round_pd() {
5653        let a = _mm512_set1_pd(0.000000000000000007);
5654        let b = _mm512_set1_pd(1.);
5655        let c = _mm512_set1_pd(-1.);
5656        let r = _mm512_maskz_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5657            0, a, b, c,
5658        );
5659        assert_eq_m512d(r, _mm512_setzero_pd());
5660        let r = _mm512_maskz_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5661            0b00001111, a, b, c,
5662        );
5663        let e = _mm512_setr_pd(-1., -1., -1., -1., 0., 0., 0., 0.);
5664        assert_eq_m512d(r, e);
5665    }
5666
5667    #[simd_test(enable = "avx512f")]
5668    unsafe fn test_mm512_mask3_fmadd_round_pd() {
5669        let a = _mm512_set1_pd(0.000000000000000007);
5670        let b = _mm512_set1_pd(1.);
5671        let c = _mm512_set1_pd(-1.);
5672        let r = _mm512_mask3_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5673            a, b, c, 0,
5674        );
5675        assert_eq_m512d(r, c);
5676        let r = _mm512_mask3_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5677            a, b, c, 0b00001111,
5678        );
5679        let e = _mm512_setr_pd(-1., -1., -1., -1., -1., -1., -1., -1.);
5680        assert_eq_m512d(r, e);
5681    }
5682
5683    #[simd_test(enable = "avx512f")]
5684    unsafe fn test_mm512_fmsub_round_pd() {
5685        let a = _mm512_set1_pd(0.000000000000000007);
5686        let b = _mm512_set1_pd(1.);
5687        let c = _mm512_set1_pd(1.);
5688        let r = _mm512_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5689        let e = _mm512_set1_pd(-1.);
5690        assert_eq_m512d(r, e);
5691        let r = _mm512_fmsub_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5692        let e = _mm512_set1_pd(-0.9999999999999999);
5693        assert_eq_m512d(r, e);
5694    }
5695
5696    #[simd_test(enable = "avx512f")]
5697    unsafe fn test_mm512_mask_fmsub_round_pd() {
5698        let a = _mm512_set1_pd(0.000000000000000007);
5699        let b = _mm512_set1_pd(1.);
5700        let c = _mm512_set1_pd(1.);
5701        let r = _mm512_mask_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5702            a, 0, b, c,
5703        );
5704        assert_eq_m512d(r, a);
5705        let r = _mm512_mask_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5706            a, 0b00001111, b, c,
5707        );
5708        let e = _mm512_setr_pd(
5709            -1.,
5710            -1.,
5711            -1.,
5712            -1.,
5713            0.000000000000000007,
5714            0.000000000000000007,
5715            0.000000000000000007,
5716            0.000000000000000007,
5717        );
5718        assert_eq_m512d(r, e);
5719    }
5720
5721    #[simd_test(enable = "avx512f")]
5722    unsafe fn test_mm512_maskz_fmsub_round_pd() {
5723        let a = _mm512_set1_pd(0.000000000000000007);
5724        let b = _mm512_set1_pd(1.);
5725        let c = _mm512_set1_pd(1.);
5726        let r = _mm512_maskz_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5727            0, a, b, c,
5728        );
5729        assert_eq_m512d(r, _mm512_setzero_pd());
5730        let r = _mm512_maskz_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5731            0b00001111, a, b, c,
5732        );
5733        let e = _mm512_setr_pd(-1., -1., -1., -1., 0., 0., 0., 0.);
5734        assert_eq_m512d(r, e);
5735    }
5736
5737    #[simd_test(enable = "avx512f")]
5738    unsafe fn test_mm512_mask3_fmsub_round_pd() {
5739        let a = _mm512_set1_pd(0.000000000000000007);
5740        let b = _mm512_set1_pd(1.);
5741        let c = _mm512_set1_pd(1.);
5742        let r = _mm512_mask3_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5743            a, b, c, 0,
5744        );
5745        assert_eq_m512d(r, c);
5746        let r = _mm512_mask3_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5747            a, b, c, 0b00001111,
5748        );
5749        let e = _mm512_setr_pd(-1., -1., -1., -1., 1., 1., 1., 1.);
5750        assert_eq_m512d(r, e);
5751    }
5752
5753    #[simd_test(enable = "avx512f")]
5754    unsafe fn test_mm512_fmaddsub_round_pd() {
5755        let a = _mm512_set1_pd(0.000000000000000007);
5756        let b = _mm512_set1_pd(1.);
5757        let c = _mm512_set1_pd(-1.);
5758        let r =
5759            _mm512_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5760        let e = _mm512_setr_pd(1., -1., 1., -1., 1., -1., 1., -1.);
5761        assert_eq_m512d(r, e);
5762        let r = _mm512_fmaddsub_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5763        let e = _mm512_setr_pd(
5764            1.,
5765            -0.9999999999999999,
5766            1.,
5767            -0.9999999999999999,
5768            1.,
5769            -0.9999999999999999,
5770            1.,
5771            -0.9999999999999999,
5772        );
5773        assert_eq_m512d(r, e);
5774    }
5775
5776    #[simd_test(enable = "avx512f")]
5777    unsafe fn test_mm512_mask_fmaddsub_round_pd() {
5778        let a = _mm512_set1_pd(0.000000000000000007);
5779        let b = _mm512_set1_pd(1.);
5780        let c = _mm512_set1_pd(-1.);
5781        let r = _mm512_mask_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5782            a, 0, b, c,
5783        );
5784        assert_eq_m512d(r, a);
5785        let r = _mm512_mask_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5786            a, 0b00001111, b, c,
5787        );
5788        let e = _mm512_setr_pd(
5789            1.,
5790            -1.,
5791            1.,
5792            -1.,
5793            0.000000000000000007,
5794            0.000000000000000007,
5795            0.000000000000000007,
5796            0.000000000000000007,
5797        );
5798        assert_eq_m512d(r, e);
5799    }
5800
5801    #[simd_test(enable = "avx512f")]
5802    unsafe fn test_mm512_maskz_fmaddsub_round_pd() {
5803        let a = _mm512_set1_pd(0.000000000000000007);
5804        let b = _mm512_set1_pd(1.);
5805        let c = _mm512_set1_pd(-1.);
5806        let r = _mm512_maskz_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5807            0, a, b, c,
5808        );
5809        assert_eq_m512d(r, _mm512_setzero_pd());
5810        let r = _mm512_maskz_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5811            0b00001111, a, b, c,
5812        );
5813        let e = _mm512_setr_pd(1., -1., 1., -1., 0., 0., 0., 0.);
5814        assert_eq_m512d(r, e);
5815    }
5816
5817    #[simd_test(enable = "avx512f")]
5818    unsafe fn test_mm512_mask3_fmaddsub_round_pd() {
5819        let a = _mm512_set1_pd(0.000000000000000007);
5820        let b = _mm512_set1_pd(1.);
5821        let c = _mm512_set1_pd(-1.);
5822        let r = _mm512_mask3_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5823            a, b, c, 0,
5824        );
5825        assert_eq_m512d(r, c);
5826        let r = _mm512_mask3_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5827            a, b, c, 0b00001111,
5828        );
5829        let e = _mm512_setr_pd(1., -1., 1., -1., -1., -1., -1., -1.);
5830        assert_eq_m512d(r, e);
5831    }
5832
5833    #[simd_test(enable = "avx512f")]
5834    unsafe fn test_mm512_fmsubadd_round_pd() {
5835        let a = _mm512_set1_pd(0.000000000000000007);
5836        let b = _mm512_set1_pd(1.);
5837        let c = _mm512_set1_pd(-1.);
5838        let r =
5839            _mm512_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5840        let e = _mm512_setr_pd(-1., 1., -1., 1., -1., 1., -1., 1.);
5841        assert_eq_m512d(r, e);
5842        let r = _mm512_fmsubadd_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5843        let e = _mm512_setr_pd(
5844            -0.9999999999999999,
5845            1.,
5846            -0.9999999999999999,
5847            1.,
5848            -0.9999999999999999,
5849            1.,
5850            -0.9999999999999999,
5851            1.,
5852        );
5853        assert_eq_m512d(r, e);
5854    }
5855
5856    #[simd_test(enable = "avx512f")]
5857    unsafe fn test_mm512_mask_fmsubadd_round_pd() {
5858        let a = _mm512_set1_pd(0.000000000000000007);
5859        let b = _mm512_set1_pd(1.);
5860        let c = _mm512_set1_pd(-1.);
5861        let r = _mm512_mask_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5862            a, 0, b, c,
5863        );
5864        assert_eq_m512d(r, a);
5865        let r = _mm512_mask_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5866            a, 0b00001111, b, c,
5867        );
5868        let e = _mm512_setr_pd(
5869            -1.,
5870            1.,
5871            -1.,
5872            1.,
5873            0.000000000000000007,
5874            0.000000000000000007,
5875            0.000000000000000007,
5876            0.000000000000000007,
5877        );
5878        assert_eq_m512d(r, e);
5879    }
5880
5881    #[simd_test(enable = "avx512f")]
5882    unsafe fn test_mm512_maskz_fmsubadd_round_pd() {
5883        let a = _mm512_set1_pd(0.000000000000000007);
5884        let b = _mm512_set1_pd(1.);
5885        let c = _mm512_set1_pd(-1.);
5886        let r = _mm512_maskz_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5887            0, a, b, c,
5888        );
5889        assert_eq_m512d(r, _mm512_setzero_pd());
5890        let r = _mm512_maskz_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5891            0b00001111, a, b, c,
5892        );
5893        let e = _mm512_setr_pd(-1., 1., -1., 1., 0., 0., 0., 0.);
5894        assert_eq_m512d(r, e);
5895    }
5896
5897    #[simd_test(enable = "avx512f")]
5898    unsafe fn test_mm512_mask3_fmsubadd_round_pd() {
5899        let a = _mm512_set1_pd(0.000000000000000007);
5900        let b = _mm512_set1_pd(1.);
5901        let c = _mm512_set1_pd(-1.);
5902        let r = _mm512_mask3_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5903            a, b, c, 0,
5904        );
5905        assert_eq_m512d(r, c);
5906        let r = _mm512_mask3_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5907            a, b, c, 0b00001111,
5908        );
5909        let e = _mm512_setr_pd(-1., 1., -1., 1., -1., -1., -1., -1.);
5910        assert_eq_m512d(r, e);
5911    }
5912
5913    #[simd_test(enable = "avx512f")]
5914    unsafe fn test_mm512_fnmadd_round_pd() {
5915        let a = _mm512_set1_pd(0.000000000000000007);
5916        let b = _mm512_set1_pd(1.);
5917        let c = _mm512_set1_pd(1.);
5918        let r =
5919            _mm512_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5920        let e = _mm512_set1_pd(1.);
5921        assert_eq_m512d(r, e);
5922        let r = _mm512_fnmadd_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5923        let e = _mm512_set1_pd(0.9999999999999999);
5924        assert_eq_m512d(r, e);
5925    }
5926
5927    #[simd_test(enable = "avx512f")]
5928    unsafe fn test_mm512_mask_fnmadd_round_pd() {
5929        let a = _mm512_set1_pd(0.000000000000000007);
5930        let b = _mm512_set1_pd(1.);
5931        let c = _mm512_set1_pd(1.);
5932        let r = _mm512_mask_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5933            a, 0, b, c,
5934        );
5935        assert_eq_m512d(r, a);
5936        let r = _mm512_mask_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5937            a, 0b00001111, b, c,
5938        );
5939        let e = _mm512_setr_pd(
5940            1.,
5941            1.,
5942            1.,
5943            1.,
5944            0.000000000000000007,
5945            0.000000000000000007,
5946            0.000000000000000007,
5947            0.000000000000000007,
5948        );
5949        assert_eq_m512d(r, e);
5950    }
5951
5952    #[simd_test(enable = "avx512f")]
5953    unsafe fn test_mm512_maskz_fnmadd_round_pd() {
5954        let a = _mm512_set1_pd(0.000000000000000007);
5955        let b = _mm512_set1_pd(1.);
5956        let c = _mm512_set1_pd(1.);
5957        let r = _mm512_maskz_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5958            0, a, b, c,
5959        );
5960        assert_eq_m512d(r, _mm512_setzero_pd());
5961        let r = _mm512_maskz_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5962            0b00001111, a, b, c,
5963        );
5964        let e = _mm512_setr_pd(1., 1., 1., 1., 0., 0., 0., 0.);
5965        assert_eq_m512d(r, e);
5966    }
5967
5968    #[simd_test(enable = "avx512f")]
5969    unsafe fn test_mm512_mask3_fnmadd_round_pd() {
5970        let a = _mm512_set1_pd(0.000000000000000007);
5971        let b = _mm512_set1_pd(1.);
5972        let c = _mm512_set1_pd(1.);
5973        let r = _mm512_mask3_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5974            a, b, c, 0,
5975        );
5976        assert_eq_m512d(r, c);
5977        let r = _mm512_mask3_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5978            a, b, c, 0b00001111,
5979        );
5980        let e = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
5981        assert_eq_m512d(r, e);
5982    }
5983
5984    #[simd_test(enable = "avx512f")]
5985    unsafe fn test_mm512_fnmsub_round_pd() {
5986        let a = _mm512_set1_pd(0.000000000000000007);
5987        let b = _mm512_set1_pd(1.);
5988        let c = _mm512_set1_pd(-1.);
5989        let r =
5990            _mm512_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5991        let e = _mm512_set1_pd(1.);
5992        assert_eq_m512d(r, e);
5993        let r = _mm512_fnmsub_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5994        let e = _mm512_set1_pd(0.9999999999999999);
5995        assert_eq_m512d(r, e);
5996    }
5997
5998    #[simd_test(enable = "avx512f")]
5999    unsafe fn test_mm512_mask_fnmsub_round_pd() {
6000        let a = _mm512_set1_pd(0.000000000000000007);
6001        let b = _mm512_set1_pd(1.);
6002        let c = _mm512_set1_pd(-1.);
6003        let r = _mm512_mask_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6004            a, 0, b, c,
6005        );
6006        assert_eq_m512d(r, a);
6007        let r = _mm512_mask_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6008            a, 0b00001111, b, c,
6009        );
6010        let e = _mm512_setr_pd(
6011            1.,
6012            1.,
6013            1.,
6014            1.,
6015            0.000000000000000007,
6016            0.000000000000000007,
6017            0.000000000000000007,
6018            0.000000000000000007,
6019        );
6020        assert_eq_m512d(r, e);
6021    }
6022
6023    #[simd_test(enable = "avx512f")]
6024    unsafe fn test_mm512_maskz_fnmsub_round_pd() {
6025        let a = _mm512_set1_pd(0.000000000000000007);
6026        let b = _mm512_set1_pd(1.);
6027        let c = _mm512_set1_pd(-1.);
6028        let r = _mm512_maskz_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6029            0, a, b, c,
6030        );
6031        assert_eq_m512d(r, _mm512_setzero_pd());
6032        let r = _mm512_maskz_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6033            0b00001111, a, b, c,
6034        );
6035        let e = _mm512_setr_pd(1., 1., 1., 1., 0., 0., 0., 0.);
6036        assert_eq_m512d(r, e);
6037    }
6038
6039    #[simd_test(enable = "avx512f")]
6040    unsafe fn test_mm512_mask3_fnmsub_round_pd() {
6041        let a = _mm512_set1_pd(0.000000000000000007);
6042        let b = _mm512_set1_pd(1.);
6043        let c = _mm512_set1_pd(-1.);
6044        let r = _mm512_mask3_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6045            a, b, c, 0,
6046        );
6047        assert_eq_m512d(r, c);
6048        let r = _mm512_mask3_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6049            a, b, c, 0b00001111,
6050        );
6051        let e = _mm512_setr_pd(1., 1., 1., 1., -1., -1., -1., -1.);
6052        assert_eq_m512d(r, e);
6053    }
6054
6055    #[simd_test(enable = "avx512f")]
6056    unsafe fn test_mm512_max_round_pd() {
6057        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6058        let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
6059        let r = _mm512_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, b);
6060        let e = _mm512_setr_pd(7., 6., 5., 4., 4., 5., 6., 7.);
6061        assert_eq_m512d(r, e);
6062    }
6063
6064    #[simd_test(enable = "avx512f")]
6065    unsafe fn test_mm512_mask_max_round_pd() {
6066        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6067        let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
6068        let r = _mm512_mask_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0, a, b);
6069        assert_eq_m512d(r, a);
6070        let r = _mm512_mask_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0b00001111, a, b);
6071        let e = _mm512_setr_pd(7., 6., 5., 4., 4., 5., 6., 7.);
6072        assert_eq_m512d(r, e);
6073    }
6074
6075    #[simd_test(enable = "avx512f")]
6076    unsafe fn test_mm512_maskz_max_round_pd() {
6077        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6078        let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
6079        let r = _mm512_maskz_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(0, a, b);
6080        assert_eq_m512d(r, _mm512_setzero_pd());
6081        let r = _mm512_maskz_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a, b);
6082        let e = _mm512_setr_pd(7., 6., 5., 4., 0., 0., 0., 0.);
6083        assert_eq_m512d(r, e);
6084    }
6085
6086    #[simd_test(enable = "avx512f")]
6087    unsafe fn test_mm512_min_round_pd() {
6088        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6089        let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
6090        let r = _mm512_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, b);
6091        let e = _mm512_setr_pd(0., 1., 2., 3., 3., 2., 1., 0.);
6092        assert_eq_m512d(r, e);
6093    }
6094
6095    #[simd_test(enable = "avx512f")]
6096    unsafe fn test_mm512_mask_min_round_pd() {
6097        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6098        let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
6099        let r = _mm512_mask_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0, a, b);
6100        assert_eq_m512d(r, a);
6101        let r = _mm512_mask_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0b00001111, a, b);
6102        let e = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6103        assert_eq_m512d(r, e);
6104    }
6105
6106    #[simd_test(enable = "avx512f")]
6107    unsafe fn test_mm512_maskz_min_round_pd() {
6108        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6109        let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
6110        let r = _mm512_maskz_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(0, a, b);
6111        assert_eq_m512d(r, _mm512_setzero_pd());
6112        let r = _mm512_maskz_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a, b);
6113        let e = _mm512_setr_pd(0., 1., 2., 3., 0., 0., 0., 0.);
6114        assert_eq_m512d(r, e);
6115    }
6116
6117    #[simd_test(enable = "avx512f")]
6118    unsafe fn test_mm512_getexp_round_pd() {
6119        let a = _mm512_set1_pd(3.);
6120        let r = _mm512_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(a);
6121        let e = _mm512_set1_pd(1.);
6122        assert_eq_m512d(r, e);
6123    }
6124
6125    #[simd_test(enable = "avx512f")]
6126    unsafe fn test_mm512_mask_getexp_round_pd() {
6127        let a = _mm512_set1_pd(3.);
6128        let r = _mm512_mask_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0, a);
6129        assert_eq_m512d(r, a);
6130        let r = _mm512_mask_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0b11110000, a);
6131        let e = _mm512_setr_pd(3., 3., 3., 3., 1., 1., 1., 1.);
6132        assert_eq_m512d(r, e);
6133    }
6134
6135    #[simd_test(enable = "avx512f")]
6136    unsafe fn test_mm512_maskz_getexp_round_pd() {
6137        let a = _mm512_set1_pd(3.);
6138        let r = _mm512_maskz_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(0, a);
6139        assert_eq_m512d(r, _mm512_setzero_pd());
6140        let r = _mm512_maskz_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(0b11110000, a);
6141        let e = _mm512_setr_pd(0., 0., 0., 0., 1., 1., 1., 1.);
6142        assert_eq_m512d(r, e);
6143    }
6144
6145    #[simd_test(enable = "avx512f")]
6146    unsafe fn test_mm512_roundscale_round_pd() {
6147        let a = _mm512_set1_pd(1.1);
6148        let r = _mm512_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(a);
6149        let e = _mm512_set1_pd(1.0);
6150        assert_eq_m512d(r, e);
6151    }
6152
6153    #[simd_test(enable = "avx512f")]
6154    unsafe fn test_mm512_mask_roundscale_round_pd() {
6155        let a = _mm512_set1_pd(1.1);
6156        let r = _mm512_mask_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(a, 0, a);
6157        let e = _mm512_set1_pd(1.1);
6158        assert_eq_m512d(r, e);
6159        let r = _mm512_mask_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(a, 0b11111111, a);
6160        let e = _mm512_set1_pd(1.0);
6161        assert_eq_m512d(r, e);
6162    }
6163
6164    #[simd_test(enable = "avx512f")]
6165    unsafe fn test_mm512_maskz_roundscale_round_pd() {
6166        let a = _mm512_set1_pd(1.1);
6167        let r = _mm512_maskz_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(0, a);
6168        assert_eq_m512d(r, _mm512_setzero_pd());
6169        let r = _mm512_maskz_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(0b11111111, a);
6170        let e = _mm512_set1_pd(1.0);
6171        assert_eq_m512d(r, e);
6172    }
6173
6174    #[simd_test(enable = "avx512f")]
6175    unsafe fn test_mm512_scalef_round_pd() {
6176        let a = _mm512_set1_pd(1.);
6177        let b = _mm512_set1_pd(3.);
6178        let r = _mm512_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
6179        let e = _mm512_set1_pd(8.);
6180        assert_eq_m512d(r, e);
6181    }
6182
6183    #[simd_test(enable = "avx512f")]
6184    unsafe fn test_mm512_mask_scalef_round_pd() {
6185        let a = _mm512_set1_pd(1.);
6186        let b = _mm512_set1_pd(3.);
6187        let r = _mm512_mask_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6188            a, 0, a, b,
6189        );
6190        assert_eq_m512d(r, a);
6191        let r = _mm512_mask_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6192            a, 0b11110000, a, b,
6193        );
6194        let e = _mm512_set_pd(8., 8., 8., 8., 1., 1., 1., 1.);
6195        assert_eq_m512d(r, e);
6196    }
6197
6198    #[simd_test(enable = "avx512f")]
6199    unsafe fn test_mm512_maskz_scalef_round_pd() {
6200        let a = _mm512_set1_pd(1.);
6201        let b = _mm512_set1_pd(3.);
6202        let r = _mm512_maskz_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6203            0, a, b,
6204        );
6205        assert_eq_m512d(r, _mm512_setzero_pd());
6206        let r = _mm512_maskz_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6207            0b11110000, a, b,
6208        );
6209        let e = _mm512_set_pd(8., 8., 8., 8., 0., 0., 0., 0.);
6210        assert_eq_m512d(r, e);
6211    }
6212
6213    #[simd_test(enable = "avx512f")]
6214    unsafe fn test_mm512_fixupimm_round_pd() {
6215        let a = _mm512_set1_pd(f64::NAN);
6216        let b = _mm512_set1_pd(f64::MAX);
6217        let c = _mm512_set1_epi64(i32::MAX as i64);
6218        let r = _mm512_fixupimm_round_pd::<5, _MM_FROUND_CUR_DIRECTION>(a, b, c);
6219        let e = _mm512_set1_pd(0.0);
6220        assert_eq_m512d(r, e);
6221    }
6222
6223    #[simd_test(enable = "avx512f")]
6224    unsafe fn test_mm512_mask_fixupimm_round_pd() {
6225        let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.);
6226        let b = _mm512_set1_pd(f64::MAX);
6227        let c = _mm512_set1_epi64(i32::MAX as i64);
6228        let r = _mm512_mask_fixupimm_round_pd::<5, _MM_FROUND_CUR_DIRECTION>(a, 0b11110000, b, c);
6229        let e = _mm512_set_pd(0., 0., 0., 0., 1., 1., 1., 1.);
6230        assert_eq_m512d(r, e);
6231    }
6232
6233    #[simd_test(enable = "avx512f")]
6234    unsafe fn test_mm512_maskz_fixupimm_round_pd() {
6235        let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.);
6236        let b = _mm512_set1_pd(f64::MAX);
6237        let c = _mm512_set1_epi64(i32::MAX as i64);
6238        let r = _mm512_maskz_fixupimm_round_pd::<5, _MM_FROUND_CUR_DIRECTION>(0b11110000, a, b, c);
6239        let e = _mm512_set_pd(0., 0., 0., 0., 0., 0., 0., 0.);
6240        assert_eq_m512d(r, e);
6241    }
6242
6243    #[simd_test(enable = "avx512f")]
6244    unsafe fn test_mm512_getmant_round_pd() {
6245        let a = _mm512_set1_pd(10.);
6246        let r = _mm512_getmant_round_pd::<
6247            _MM_MANT_NORM_1_2,
6248            _MM_MANT_SIGN_SRC,
6249            _MM_FROUND_CUR_DIRECTION,
6250        >(a);
6251        let e = _mm512_set1_pd(1.25);
6252        assert_eq_m512d(r, e);
6253    }
6254
6255    #[simd_test(enable = "avx512f")]
6256    unsafe fn test_mm512_mask_getmant_round_pd() {
6257        let a = _mm512_set1_pd(10.);
6258        let r = _mm512_mask_getmant_round_pd::<
6259            _MM_MANT_NORM_1_2,
6260            _MM_MANT_SIGN_SRC,
6261            _MM_FROUND_CUR_DIRECTION,
6262        >(a, 0, a);
6263        assert_eq_m512d(r, a);
6264        let r = _mm512_mask_getmant_round_pd::<
6265            _MM_MANT_NORM_1_2,
6266            _MM_MANT_SIGN_SRC,
6267            _MM_FROUND_CUR_DIRECTION,
6268        >(a, 0b11110000, a);
6269        let e = _mm512_setr_pd(10., 10., 10., 10., 1.25, 1.25, 1.25, 1.25);
6270        assert_eq_m512d(r, e);
6271    }
6272
6273    #[simd_test(enable = "avx512f")]
6274    unsafe fn test_mm512_maskz_getmant_round_pd() {
6275        let a = _mm512_set1_pd(10.);
6276        let r = _mm512_maskz_getmant_round_pd::<
6277            _MM_MANT_NORM_1_2,
6278            _MM_MANT_SIGN_SRC,
6279            _MM_FROUND_CUR_DIRECTION,
6280        >(0, a);
6281        assert_eq_m512d(r, _mm512_setzero_pd());
6282        let r = _mm512_maskz_getmant_round_pd::<
6283            _MM_MANT_NORM_1_2,
6284            _MM_MANT_SIGN_SRC,
6285            _MM_FROUND_CUR_DIRECTION,
6286        >(0b11110000, a);
6287        let e = _mm512_setr_pd(0., 0., 0., 0., 1.25, 1.25, 1.25, 1.25);
6288        assert_eq_m512d(r, e);
6289    }
6290
6291    #[simd_test(enable = "avx512f")]
6292    unsafe fn test_mm512_cvt_roundps_pd() {
6293        let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6294        let r = _mm512_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(a);
6295        let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6296        assert_eq_m512d(r, e);
6297    }
6298
6299    #[simd_test(enable = "avx512f")]
6300    unsafe fn test_mm512_mask_cvt_roundps_pd() {
6301        let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6302        let src = _mm512_set1_pd(0.);
6303        let r = _mm512_mask_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(src, 0, a);
6304        assert_eq_m512d(r, src);
6305        let r = _mm512_mask_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(src, 0b00001111, a);
6306        let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
6307        assert_eq_m512d(r, e);
6308    }
6309
6310    #[simd_test(enable = "avx512f")]
6311    unsafe fn test_mm512_maskz_cvt_roundps_pd() {
6312        let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6313        let r = _mm512_maskz_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(0, a);
6314        assert_eq_m512d(r, _mm512_setzero_pd());
6315        let r = _mm512_maskz_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a);
6316        let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
6317        assert_eq_m512d(r, e);
6318    }
6319
6320    #[simd_test(enable = "avx512f")]
6321    unsafe fn test_mm512_cvt_roundpd_ps() {
6322        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6323        let r = _mm512_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(a);
6324        let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6325        assert_eq_m256(r, e);
6326    }
6327
6328    #[simd_test(enable = "avx512f")]
6329    unsafe fn test_mm512_mask_cvt_roundpd_ps() {
6330        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6331        let src = _mm256_set1_ps(0.);
6332        let r = _mm512_mask_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(src, 0, a);
6333        assert_eq_m256(r, src);
6334        let r = _mm512_mask_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(src, 0b00001111, a);
6335        let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
6336        assert_eq_m256(r, e);
6337    }
6338
6339    #[simd_test(enable = "avx512f")]
6340    unsafe fn test_mm512_maskz_cvt_roundpd_ps() {
6341        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6342        let r = _mm512_maskz_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(0, a);
6343        assert_eq_m256(r, _mm256_setzero_ps());
6344        let r = _mm512_maskz_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a);
6345        let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
6346        assert_eq_m256(r, e);
6347    }
6348
6349    #[simd_test(enable = "avx512f")]
6350    unsafe fn test_mm512_cvt_roundpd_epi32() {
6351        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6352        let r = _mm512_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(a);
6353        let e = _mm256_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8);
6354        assert_eq_m256i(r, e);
6355    }
6356
6357    #[simd_test(enable = "avx512f")]
6358    unsafe fn test_mm512_mask_cvt_roundpd_epi32() {
6359        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6360        let src = _mm256_set1_epi32(0);
6361        let r = _mm512_mask_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(src, 0, a);
6362        assert_eq_m256i(r, src);
6363        let r = _mm512_mask_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(src, 0b00001111, a);
6364        let e = _mm256_setr_epi32(0, -2, 2, -4, 0, 0, 0, 0);
6365        assert_eq_m256i(r, e);
6366    }
6367
6368    #[simd_test(enable = "avx512f")]
6369    unsafe fn test_mm512_maskz_cvt_roundpd_epi32() {
6370        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6371        let r = _mm512_maskz_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(0, a);
6372        assert_eq_m256i(r, _mm256_setzero_si256());
6373        let r = _mm512_maskz_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a);
6374        let e = _mm256_setr_epi32(0, -2, 2, -4, 0, 0, 0, 0);
6375        assert_eq_m256i(r, e);
6376    }
6377
6378    #[simd_test(enable = "avx512f")]
6379    unsafe fn test_mm512_cvt_roundpd_epu32() {
6380        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6381        let r = _mm512_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(a);
6382        let e = _mm256_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1);
6383        assert_eq_m256i(r, e);
6384    }
6385
6386    #[simd_test(enable = "avx512f")]
6387    unsafe fn test_mm512_mask_cvt_roundpd_epu32() {
6388        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6389        let src = _mm256_set1_epi32(0);
6390        let r = _mm512_mask_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(src, 0, a);
6391        assert_eq_m256i(r, src);
6392        let r = _mm512_mask_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(src, 0b00001111, a);
6393        let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
6394        assert_eq_m256i(r, e);
6395    }
6396
6397    #[simd_test(enable = "avx512f")]
6398    unsafe fn test_mm512_maskz_cvt_roundpd_epu32() {
6399        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6400        let r = _mm512_maskz_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(0, a);
6401        assert_eq_m256i(r, _mm256_setzero_si256());
6402        let r = _mm512_maskz_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a);
6403        let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
6404        assert_eq_m256i(r, e);
6405    }
6406
6407    #[simd_test(enable = "avx512f")]
6408    unsafe fn test_mm512_setzero_pd() {
6409        assert_eq_m512d(_mm512_setzero_pd(), _mm512_set1_pd(0.));
6410    }
6411
6412    unsafe fn test_mm512_set1_epi64() {
6413        let r = _mm512_set_epi64(2, 2, 2, 2, 2, 2, 2, 2);
6414        assert_eq_m512i(r, _mm512_set1_epi64(2));
6415    }
6416
6417    #[simd_test(enable = "avx512f")]
6418    unsafe fn test_mm512_set1_pd() {
6419        let expected = _mm512_set_pd(2., 2., 2., 2., 2., 2., 2., 2.);
6420        assert_eq_m512d(expected, _mm512_set1_pd(2.));
6421    }
6422
6423    unsafe fn test_mm512_set4_epi64() {
6424        let r = _mm512_set_epi64(4, 3, 2, 1, 4, 3, 2, 1);
6425        assert_eq_m512i(r, _mm512_set4_epi64(4, 3, 2, 1));
6426    }
6427
6428    #[simd_test(enable = "avx512f")]
6429    unsafe fn test_mm512_set4_pd() {
6430        let r = _mm512_set_pd(4., 3., 2., 1., 4., 3., 2., 1.);
6431        assert_eq_m512d(r, _mm512_set4_pd(4., 3., 2., 1.));
6432    }
6433
6434    unsafe fn test_mm512_setr4_epi64() {
6435        let r = _mm512_set_epi64(4, 3, 2, 1, 4, 3, 2, 1);
6436        assert_eq_m512i(r, _mm512_setr4_epi64(1, 2, 3, 4));
6437    }
6438
6439    #[simd_test(enable = "avx512f")]
6440    unsafe fn test_mm512_setr4_pd() {
6441        let r = _mm512_set_pd(4., 3., 2., 1., 4., 3., 2., 1.);
6442        assert_eq_m512d(r, _mm512_setr4_pd(1., 2., 3., 4.));
6443    }
6444
6445    #[simd_test(enable = "avx512f")]
6446    unsafe fn test_mm512_cmplt_pd_mask() {
6447        #[rustfmt::skip]
6448        let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6449        let b = _mm512_set1_pd(-1.);
6450        let m = _mm512_cmplt_pd_mask(a, b);
6451        assert_eq!(m, 0b00000101);
6452    }
6453
6454    #[simd_test(enable = "avx512f")]
6455    unsafe fn test_mm512_mask_cmplt_pd_mask() {
6456        #[rustfmt::skip]
6457        let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6458        let b = _mm512_set1_pd(-1.);
6459        let mask = 0b01100110;
6460        let r = _mm512_mask_cmplt_pd_mask(mask, a, b);
6461        assert_eq!(r, 0b00000100);
6462    }
6463
6464    #[simd_test(enable = "avx512f")]
6465    unsafe fn test_mm512_cmpnlt_pd_mask() {
6466        #[rustfmt::skip]
6467        let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6468        let b = _mm512_set1_pd(-1.);
6469        assert_eq!(_mm512_cmpnlt_pd_mask(a, b), !_mm512_cmplt_pd_mask(a, b));
6470    }
6471
6472    #[simd_test(enable = "avx512f")]
6473    unsafe fn test_mm512_mask_cmpnlt_pd_mask() {
6474        #[rustfmt::skip]
6475        let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6476        let b = _mm512_set1_pd(-1.);
6477        let mask = 0b01111010;
6478        assert_eq!(_mm512_mask_cmpnlt_pd_mask(mask, a, b), 0b01111010);
6479    }
6480
6481    #[simd_test(enable = "avx512f")]
6482    unsafe fn test_mm512_cmple_pd_mask() {
6483        #[rustfmt::skip]
6484        let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6485        let b = _mm512_set1_pd(-1.);
6486        assert_eq!(_mm512_cmple_pd_mask(a, b), 0b00100101);
6487    }
6488
6489    #[simd_test(enable = "avx512f")]
6490    unsafe fn test_mm512_mask_cmple_pd_mask() {
6491        #[rustfmt::skip]
6492        let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6493        let b = _mm512_set1_pd(-1.);
6494        let mask = 0b01111010;
6495        assert_eq!(_mm512_mask_cmple_pd_mask(mask, a, b), 0b00100000);
6496    }
6497
6498    #[simd_test(enable = "avx512f")]
6499    unsafe fn test_mm512_cmpnle_pd_mask() {
6500        #[rustfmt::skip]
6501        let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6502        let b = _mm512_set1_pd(-1.);
6503        let m = _mm512_cmpnle_pd_mask(b, a);
6504        assert_eq!(m, 0b00001101);
6505    }
6506
6507    #[simd_test(enable = "avx512f")]
6508    unsafe fn test_mm512_mask_cmpnle_pd_mask() {
6509        #[rustfmt::skip]
6510        let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6511        let b = _mm512_set1_pd(-1.);
6512        let mask = 0b01100110;
6513        let r = _mm512_mask_cmpnle_pd_mask(mask, b, a);
6514        assert_eq!(r, 0b00000100);
6515    }
6516
6517    #[simd_test(enable = "avx512f")]
6518    unsafe fn test_mm512_cmpeq_pd_mask() {
6519        let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, f64::NAN, -100.);
6520        let b = _mm512_set_pd(0., 1., 13., 42., f64::MAX, f64::MIN, f64::NAN, -100.);
6521        let m = _mm512_cmpeq_pd_mask(b, a);
6522        assert_eq!(m, 0b11001101);
6523    }
6524
6525    #[simd_test(enable = "avx512f")]
6526    unsafe fn test_mm512_mask_cmpeq_pd_mask() {
6527        let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, f64::NAN, -100.);
6528        let b = _mm512_set_pd(0., 1., 13., 42., f64::MAX, f64::MIN, f64::NAN, -100.);
6529        let mask = 0b01111010;
6530        let r = _mm512_mask_cmpeq_pd_mask(mask, b, a);
6531        assert_eq!(r, 0b01001000);
6532    }
6533
6534    #[simd_test(enable = "avx512f")]
6535    unsafe fn test_mm512_cmpneq_pd_mask() {
6536        let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, f64::NAN, -100.);
6537        let b = _mm512_set_pd(0., 1., 13., 42., f64::MAX, f64::MIN, f64::NAN, -100.);
6538        let m = _mm512_cmpneq_pd_mask(b, a);
6539        assert_eq!(m, 0b00110010);
6540    }
6541
6542    #[simd_test(enable = "avx512f")]
6543    unsafe fn test_mm512_mask_cmpneq_pd_mask() {
6544        let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, f64::NAN, -100.);
6545        let b = _mm512_set_pd(0., 1., 13., 42., f64::MAX, f64::MIN, f64::NAN, -100.);
6546        let mask = 0b01111010;
6547        let r = _mm512_mask_cmpneq_pd_mask(mask, b, a);
6548        assert_eq!(r, 0b00110010)
6549    }
6550
6551    #[simd_test(enable = "avx512f")]
6552    unsafe fn test_mm512_cmp_pd_mask() {
6553        let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.);
6554        let b = _mm512_set1_pd(-1.);
6555        let m = _mm512_cmp_pd_mask::<_CMP_LT_OQ>(a, b);
6556        assert_eq!(m, 0b00000101);
6557    }
6558
6559    #[simd_test(enable = "avx512f")]
6560    unsafe fn test_mm512_mask_cmp_pd_mask() {
6561        let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.);
6562        let b = _mm512_set1_pd(-1.);
6563        let mask = 0b01100110;
6564        let r = _mm512_mask_cmp_pd_mask::<_CMP_LT_OQ>(mask, a, b);
6565        assert_eq!(r, 0b00000100);
6566    }
6567
6568    #[simd_test(enable = "avx512f,avx512vl")]
6569    unsafe fn test_mm256_cmp_pd_mask() {
6570        let a = _mm256_set_pd(0., 1., -1., 13.);
6571        let b = _mm256_set1_pd(1.);
6572        let m = _mm256_cmp_pd_mask::<_CMP_LT_OQ>(a, b);
6573        assert_eq!(m, 0b00001010);
6574    }
6575
6576    #[simd_test(enable = "avx512f,avx512vl")]
6577    unsafe fn test_mm256_mask_cmp_pd_mask() {
6578        let a = _mm256_set_pd(0., 1., -1., 13.);
6579        let b = _mm256_set1_pd(1.);
6580        let mask = 0b11111111;
6581        let r = _mm256_mask_cmp_pd_mask::<_CMP_LT_OQ>(mask, a, b);
6582        assert_eq!(r, 0b00001010);
6583    }
6584
6585    #[simd_test(enable = "avx512f,avx512vl")]
6586    unsafe fn test_mm_cmp_pd_mask() {
6587        let a = _mm_set_pd(0., 1.);
6588        let b = _mm_set1_pd(1.);
6589        let m = _mm_cmp_pd_mask::<_CMP_LT_OQ>(a, b);
6590        assert_eq!(m, 0b00000010);
6591    }
6592
6593    #[simd_test(enable = "avx512f,avx512vl")]
6594    unsafe fn test_mm_mask_cmp_pd_mask() {
6595        let a = _mm_set_pd(0., 1.);
6596        let b = _mm_set1_pd(1.);
6597        let mask = 0b11111111;
6598        let r = _mm_mask_cmp_pd_mask::<_CMP_LT_OQ>(mask, a, b);
6599        assert_eq!(r, 0b00000010);
6600    }
6601
6602    #[simd_test(enable = "avx512f")]
6603    unsafe fn test_mm512_cmp_round_pd_mask() {
6604        #[rustfmt::skip]
6605        let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.);
6606        let b = _mm512_set1_pd(-1.);
6607        let m = _mm512_cmp_round_pd_mask::<_CMP_LT_OQ, _MM_FROUND_CUR_DIRECTION>(a, b);
6608        assert_eq!(m, 0b00000101);
6609    }
6610
6611    #[simd_test(enable = "avx512f")]
6612    unsafe fn test_mm512_mask_cmp_round_pd_mask() {
6613        #[rustfmt::skip]
6614        let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.);
6615        let b = _mm512_set1_pd(-1.);
6616        let mask = 0b01100110;
6617        let r = _mm512_mask_cmp_round_pd_mask::<_CMP_LT_OQ, _MM_FROUND_CUR_DIRECTION>(mask, a, b);
6618        assert_eq!(r, 0b00000100);
6619    }
6620
6621    #[simd_test(enable = "avx512f")]
6622    unsafe fn test_mm512_cmpord_pd_mask() {
6623        #[rustfmt::skip]
6624        let a = _mm512_set_pd(f64::NAN, f64::MAX, f64::NAN, f64::MIN, f64::NAN, -1., f64::NAN, 0.);
6625        #[rustfmt::skip]
6626        let b = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, f64::MIN, f64::MAX, -1., 0.);
6627        let m = _mm512_cmpord_pd_mask(a, b);
6628        assert_eq!(m, 0b00000101);
6629    }
6630
6631    #[simd_test(enable = "avx512f")]
6632    unsafe fn test_mm512_mask_cmpord_pd_mask() {
6633        #[rustfmt::skip]
6634        let a = _mm512_set_pd(f64::NAN, f64::MAX, f64::NAN, f64::MIN, f64::NAN, -1., f64::NAN, 0.);
6635        #[rustfmt::skip]
6636        let b = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, f64::MIN, f64::MAX, -1., 0.);
6637        let mask = 0b11000011;
6638        let m = _mm512_mask_cmpord_pd_mask(mask, a, b);
6639        assert_eq!(m, 0b00000001);
6640    }
6641
6642    #[simd_test(enable = "avx512f")]
6643    unsafe fn test_mm512_cmpunord_pd_mask() {
6644        #[rustfmt::skip]
6645        let a = _mm512_set_pd(f64::NAN, f64::MAX, f64::NAN, f64::MIN, f64::NAN, -1., f64::NAN, 0.);
6646        #[rustfmt::skip]
6647        let b = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, f64::MIN, f64::MAX, -1., 0.);
6648        let m = _mm512_cmpunord_pd_mask(a, b);
6649
6650        assert_eq!(m, 0b11111010);
6651    }
6652
6653    #[simd_test(enable = "avx512f")]
6654    unsafe fn test_mm512_mask_cmpunord_pd_mask() {
6655        #[rustfmt::skip]
6656        let a = _mm512_set_pd(f64::NAN, f64::MAX, f64::NAN, f64::MIN, f64::NAN, -1., f64::NAN, 0.);
6657        #[rustfmt::skip]
6658        let b = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, f64::MIN, f64::MAX, -1., 0.);
6659        let mask = 0b00001111;
6660        let m = _mm512_mask_cmpunord_pd_mask(mask, a, b);
6661        assert_eq!(m, 0b000001010);
6662    }
6663
6664    #[simd_test(enable = "avx512f")]
6665    unsafe fn test_mm512_cmplt_epu64_mask() {
6666        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6667        let b = _mm512_set1_epi64(-1);
6668        let m = _mm512_cmplt_epu64_mask(a, b);
6669        assert_eq!(m, 0b11001111);
6670    }
6671
6672    #[simd_test(enable = "avx512f")]
6673    unsafe fn test_mm512_mask_cmplt_epu64_mask() {
6674        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6675        let b = _mm512_set1_epi64(-1);
6676        let mask = 0b01111010;
6677        let r = _mm512_mask_cmplt_epu64_mask(mask, a, b);
6678        assert_eq!(r, 0b01001010);
6679    }
6680
6681    #[simd_test(enable = "avx512f,avx512vl")]
6682    unsafe fn test_mm256_cmplt_epu64_mask() {
6683        let a = _mm256_set_epi64x(0, 1, 2, 100);
6684        let b = _mm256_set1_epi64x(2);
6685        let r = _mm256_cmplt_epu64_mask(a, b);
6686        assert_eq!(r, 0b00001100);
6687    }
6688
6689    #[simd_test(enable = "avx512f,avx512vl")]
6690    unsafe fn test_mm256_mask_cmplt_epu64_mask() {
6691        let a = _mm256_set_epi64x(0, 1, 2, 100);
6692        let b = _mm256_set1_epi64x(2);
6693        let mask = 0b11111111;
6694        let r = _mm256_mask_cmplt_epu64_mask(mask, a, b);
6695        assert_eq!(r, 0b00001100);
6696    }
6697
6698    #[simd_test(enable = "avx512f,avx512vl")]
6699    unsafe fn test_mm_cmplt_epu64_mask() {
6700        let a = _mm_set_epi64x(0, 1);
6701        let b = _mm_set1_epi64x(2);
6702        let r = _mm_cmplt_epu64_mask(a, b);
6703        assert_eq!(r, 0b00000011);
6704    }
6705
6706    #[simd_test(enable = "avx512f,avx512vl")]
6707    unsafe fn test_mm_mask_cmplt_epu64_mask() {
6708        let a = _mm_set_epi64x(0, 1);
6709        let b = _mm_set1_epi64x(2);
6710        let mask = 0b11111111;
6711        let r = _mm_mask_cmplt_epu64_mask(mask, a, b);
6712        assert_eq!(r, 0b00000011);
6713    }
6714
6715    #[simd_test(enable = "avx512f")]
6716    unsafe fn test_mm512_cmpgt_epu64_mask() {
6717        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6718        let b = _mm512_set1_epi64(-1);
6719        let m = _mm512_cmpgt_epu64_mask(b, a);
6720        assert_eq!(m, 0b11001111);
6721    }
6722
6723    #[simd_test(enable = "avx512f")]
6724    unsafe fn test_mm512_mask_cmpgt_epu64_mask() {
6725        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6726        let b = _mm512_set1_epi64(-1);
6727        let mask = 0b01111010;
6728        let r = _mm512_mask_cmpgt_epu64_mask(mask, b, a);
6729        assert_eq!(r, 0b01001010);
6730    }
6731
6732    #[simd_test(enable = "avx512f,avx512vl")]
6733    unsafe fn test_mm256_cmpgt_epu64_mask() {
6734        let a = _mm256_set_epi64x(0, 1, 2, 3);
6735        let b = _mm256_set1_epi64x(1);
6736        let r = _mm256_cmpgt_epu64_mask(a, b);
6737        assert_eq!(r, 0b00000011);
6738    }
6739
6740    #[simd_test(enable = "avx512f,avx512vl")]
6741    unsafe fn test_mm256_mask_cmpgt_epu64_mask() {
6742        let a = _mm256_set_epi64x(0, 1, 2, 3);
6743        let b = _mm256_set1_epi64x(1);
6744        let mask = 0b11111111;
6745        let r = _mm256_mask_cmpgt_epu64_mask(mask, a, b);
6746        assert_eq!(r, 0b00000011);
6747    }
6748
6749    #[simd_test(enable = "avx512f,avx512vl")]
6750    unsafe fn test_mm_cmpgt_epu64_mask() {
6751        let a = _mm_set_epi64x(1, 2);
6752        let b = _mm_set1_epi64x(1);
6753        let r = _mm_cmpgt_epu64_mask(a, b);
6754        assert_eq!(r, 0b00000001);
6755    }
6756
6757    #[simd_test(enable = "avx512f,avx512vl")]
6758    unsafe fn test_mm_mask_cmpgt_epu64_mask() {
6759        let a = _mm_set_epi64x(1, 2);
6760        let b = _mm_set1_epi64x(1);
6761        let mask = 0b11111111;
6762        let r = _mm_mask_cmpgt_epu64_mask(mask, a, b);
6763        assert_eq!(r, 0b00000001);
6764    }
6765
6766    #[simd_test(enable = "avx512f")]
6767    unsafe fn test_mm512_cmple_epu64_mask() {
6768        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6769        let b = _mm512_set1_epi64(-1);
6770        assert_eq!(
6771            _mm512_cmple_epu64_mask(a, b),
6772            !_mm512_cmpgt_epu64_mask(a, b)
6773        )
6774    }
6775
6776    #[simd_test(enable = "avx512f")]
6777    unsafe fn test_mm512_mask_cmple_epu64_mask() {
6778        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6779        let b = _mm512_set1_epi64(-1);
6780        let mask = 0b01111010;
6781        assert_eq!(_mm512_mask_cmple_epu64_mask(mask, a, b), 0b01111010);
6782    }
6783
6784    #[simd_test(enable = "avx512f,avx512vl")]
6785    unsafe fn test_mm256_cmple_epu64_mask() {
6786        let a = _mm256_set_epi64x(0, 1, 2, 1);
6787        let b = _mm256_set1_epi64x(1);
6788        let r = _mm256_cmple_epu64_mask(a, b);
6789        assert_eq!(r, 0b00001101)
6790    }
6791
6792    #[simd_test(enable = "avx512f,avx512vl")]
6793    unsafe fn test_mm256_mask_cmple_epu64_mask() {
6794        let a = _mm256_set_epi64x(0, 1, 2, 1);
6795        let b = _mm256_set1_epi64x(1);
6796        let mask = 0b11111111;
6797        let r = _mm256_mask_cmple_epu64_mask(mask, a, b);
6798        assert_eq!(r, 0b00001101)
6799    }
6800
6801    #[simd_test(enable = "avx512f,avx512vl")]
6802    unsafe fn test_mm_cmple_epu64_mask() {
6803        let a = _mm_set_epi64x(0, 1);
6804        let b = _mm_set1_epi64x(1);
6805        let r = _mm_cmple_epu64_mask(a, b);
6806        assert_eq!(r, 0b00000011)
6807    }
6808
6809    #[simd_test(enable = "avx512f,avx512vl")]
6810    unsafe fn test_mm_mask_cmple_epu64_mask() {
6811        let a = _mm_set_epi64x(0, 1);
6812        let b = _mm_set1_epi64x(1);
6813        let mask = 0b11111111;
6814        let r = _mm_mask_cmple_epu64_mask(mask, a, b);
6815        assert_eq!(r, 0b00000011)
6816    }
6817
6818    #[simd_test(enable = "avx512f")]
6819    unsafe fn test_mm512_cmpge_epu64_mask() {
6820        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6821        let b = _mm512_set1_epi64(-1);
6822        assert_eq!(
6823            _mm512_cmpge_epu64_mask(a, b),
6824            !_mm512_cmplt_epu64_mask(a, b)
6825        );
6826    }
6827
6828    #[simd_test(enable = "avx512f")]
6829    unsafe fn test_mm512_mask_cmpge_epu64_mask() {
6830        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6831        let b = _mm512_set1_epi64(-1);
6832        let mask = 0b11111111;
6833        let r = _mm512_mask_cmpge_epu64_mask(mask, a, b);
6834        assert_eq!(r, 0b00110000);
6835    }
6836
6837    #[simd_test(enable = "avx512f,avx512vl")]
6838    unsafe fn test_mm256_cmpge_epu64_mask() {
6839        let a = _mm256_set_epi64x(0, 1, 2, u64::MAX as i64);
6840        let b = _mm256_set1_epi64x(1);
6841        let r = _mm256_cmpge_epu64_mask(a, b);
6842        assert_eq!(r, 0b00000111);
6843    }
6844
6845    #[simd_test(enable = "avx512f,avx512vl")]
6846    unsafe fn test_mm256_mask_cmpge_epu64_mask() {
6847        let a = _mm256_set_epi64x(0, 1, 2, u64::MAX as i64);
6848        let b = _mm256_set1_epi64x(1);
6849        let mask = 0b11111111;
6850        let r = _mm256_mask_cmpge_epu64_mask(mask, a, b);
6851        assert_eq!(r, 0b00000111);
6852    }
6853
6854    #[simd_test(enable = "avx512f,avx512vl")]
6855    unsafe fn test_mm_cmpge_epu64_mask() {
6856        let a = _mm_set_epi64x(0, 1);
6857        let b = _mm_set1_epi64x(1);
6858        let r = _mm_cmpge_epu64_mask(a, b);
6859        assert_eq!(r, 0b00000001);
6860    }
6861
6862    #[simd_test(enable = "avx512f,avx512vl")]
6863    unsafe fn test_mm_mask_cmpge_epu64_mask() {
6864        let a = _mm_set_epi64x(0, 1);
6865        let b = _mm_set1_epi64x(1);
6866        let mask = 0b11111111;
6867        let r = _mm_mask_cmpge_epu64_mask(mask, a, b);
6868        assert_eq!(r, 0b00000001);
6869    }
6870
6871    #[simd_test(enable = "avx512f")]
6872    unsafe fn test_mm512_cmpeq_epu64_mask() {
6873        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6874        let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
6875        let m = _mm512_cmpeq_epu64_mask(b, a);
6876        assert_eq!(m, 0b11001111);
6877    }
6878
6879    #[simd_test(enable = "avx512f")]
6880    unsafe fn test_mm512_mask_cmpeq_epu64_mask() {
6881        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6882        let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
6883        let mask = 0b01111010;
6884        let r = _mm512_mask_cmpeq_epu64_mask(mask, b, a);
6885        assert_eq!(r, 0b01001010);
6886    }
6887
6888    #[simd_test(enable = "avx512f,avx512vl")]
6889    unsafe fn test_mm256_cmpeq_epu64_mask() {
6890        let a = _mm256_set_epi64x(0, 1, -1, u64::MAX as i64);
6891        let b = _mm256_set_epi64x(0, 1, 13, 42);
6892        let m = _mm256_cmpeq_epu64_mask(b, a);
6893        assert_eq!(m, 0b00001100);
6894    }
6895
6896    #[simd_test(enable = "avx512f,avx512vl")]
6897    unsafe fn test_mm256_mask_cmpeq_epu64_mask() {
6898        let a = _mm256_set_epi64x(0, 1, -1, u64::MAX as i64);
6899        let b = _mm256_set_epi64x(0, 1, 13, 42);
6900        let mask = 0b11111111;
6901        let r = _mm256_mask_cmpeq_epu64_mask(mask, b, a);
6902        assert_eq!(r, 0b00001100);
6903    }
6904
6905    #[simd_test(enable = "avx512f,avx512vl")]
6906    unsafe fn test_mm_cmpeq_epu64_mask() {
6907        let a = _mm_set_epi64x(0, 1);
6908        let b = _mm_set_epi64x(0, 1);
6909        let m = _mm_cmpeq_epu64_mask(b, a);
6910        assert_eq!(m, 0b00000011);
6911    }
6912
6913    #[simd_test(enable = "avx512f,avx512vl")]
6914    unsafe fn test_mm_mask_cmpeq_epu64_mask() {
6915        let a = _mm_set_epi64x(0, 1);
6916        let b = _mm_set_epi64x(0, 1);
6917        let mask = 0b11111111;
6918        let r = _mm_mask_cmpeq_epu64_mask(mask, b, a);
6919        assert_eq!(r, 0b00000011);
6920    }
6921
6922    #[simd_test(enable = "avx512f")]
6923    unsafe fn test_mm512_cmpneq_epu64_mask() {
6924        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6925        let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
6926        let m = _mm512_cmpneq_epu64_mask(b, a);
6927        assert_eq!(m, !_mm512_cmpeq_epu64_mask(b, a));
6928    }
6929
6930    #[simd_test(enable = "avx512f")]
6931    unsafe fn test_mm512_mask_cmpneq_epu64_mask() {
6932        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, -100, 100);
6933        let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
6934        let mask = 0b01111010;
6935        let r = _mm512_mask_cmpneq_epu64_mask(mask, b, a);
6936        assert_eq!(r, 0b00110010);
6937    }
6938
6939    #[simd_test(enable = "avx512f,avx512vl")]
6940    unsafe fn test_mm256_cmpneq_epu64_mask() {
6941        let a = _mm256_set_epi64x(0, 1, -1, u64::MAX as i64);
6942        let b = _mm256_set_epi64x(0, 1, 13, 42);
6943        let r = _mm256_cmpneq_epu64_mask(b, a);
6944        assert_eq!(r, 0b00000011);
6945    }
6946
6947    #[simd_test(enable = "avx512f,avx512vl")]
6948    unsafe fn test_mm256_mask_cmpneq_epu64_mask() {
6949        let a = _mm256_set_epi64x(0, 1, -1, u64::MAX as i64);
6950        let b = _mm256_set_epi64x(0, 1, 13, 42);
6951        let mask = 0b11111111;
6952        let r = _mm256_mask_cmpneq_epu64_mask(mask, b, a);
6953        assert_eq!(r, 0b00000011);
6954    }
6955
6956    #[simd_test(enable = "avx512f,avx512vl")]
6957    unsafe fn test_mm_cmpneq_epu64_mask() {
6958        let a = _mm_set_epi64x(-1, u64::MAX as i64);
6959        let b = _mm_set_epi64x(13, 42);
6960        let r = _mm_cmpneq_epu64_mask(b, a);
6961        assert_eq!(r, 0b00000011);
6962    }
6963
6964    #[simd_test(enable = "avx512f,avx512vl")]
6965    unsafe fn test_mm_mask_cmpneq_epu64_mask() {
6966        let a = _mm_set_epi64x(-1, u64::MAX as i64);
6967        let b = _mm_set_epi64x(13, 42);
6968        let mask = 0b11111111;
6969        let r = _mm_mask_cmpneq_epu64_mask(mask, b, a);
6970        assert_eq!(r, 0b00000011);
6971    }
6972
6973    #[simd_test(enable = "avx512f")]
6974    unsafe fn test_mm512_cmp_epu64_mask() {
6975        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6976        let b = _mm512_set1_epi64(-1);
6977        let m = _mm512_cmp_epu64_mask::<_MM_CMPINT_LT>(a, b);
6978        assert_eq!(m, 0b11001111);
6979    }
6980
6981    #[simd_test(enable = "avx512f")]
6982    unsafe fn test_mm512_mask_cmp_epu64_mask() {
6983        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6984        let b = _mm512_set1_epi64(-1);
6985        let mask = 0b01111010;
6986        let r = _mm512_mask_cmp_epu64_mask::<_MM_CMPINT_LT>(mask, a, b);
6987        assert_eq!(r, 0b01001010);
6988    }
6989
6990    #[simd_test(enable = "avx512f,avx512vl")]
6991    unsafe fn test_mm256_cmp_epu64_mask() {
6992        let a = _mm256_set_epi64x(0, 1, -1, 100);
6993        let b = _mm256_set1_epi64x(1);
6994        let m = _mm256_cmp_epu64_mask::<_MM_CMPINT_LT>(a, b);
6995        assert_eq!(m, 0b00001000);
6996    }
6997
6998    #[simd_test(enable = "avx512f,avx512vl")]
6999    unsafe fn test_mm256_mask_cmp_epu64_mask() {
7000        let a = _mm256_set_epi64x(0, 1, -1, 100);
7001        let b = _mm256_set1_epi64x(1);
7002        let mask = 0b11111111;
7003        let r = _mm256_mask_cmp_epu64_mask::<_MM_CMPINT_LT>(mask, a, b);
7004        assert_eq!(r, 0b00001000);
7005    }
7006
7007    #[simd_test(enable = "avx512f,avx512vl")]
7008    unsafe fn test_mm_cmp_epu64_mask() {
7009        let a = _mm_set_epi64x(0, 1);
7010        let b = _mm_set1_epi64x(1);
7011        let m = _mm_cmp_epu64_mask::<_MM_CMPINT_LT>(a, b);
7012        assert_eq!(m, 0b00000010);
7013    }
7014
7015    #[simd_test(enable = "avx512f,avx512vl")]
7016    unsafe fn test_mm_mask_cmp_epu64_mask() {
7017        let a = _mm_set_epi64x(0, 1);
7018        let b = _mm_set1_epi64x(1);
7019        let mask = 0b11111111;
7020        let r = _mm_mask_cmp_epu64_mask::<_MM_CMPINT_LT>(mask, a, b);
7021        assert_eq!(r, 0b00000010);
7022    }
7023
7024    #[simd_test(enable = "avx512f")]
7025    unsafe fn test_mm512_cmplt_epi64_mask() {
7026        let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7027        let b = _mm512_set1_epi64(-1);
7028        let m = _mm512_cmplt_epi64_mask(a, b);
7029        assert_eq!(m, 0b00000101);
7030    }
7031
7032    #[simd_test(enable = "avx512f")]
7033    unsafe fn test_mm512_mask_cmplt_epi64_mask() {
7034        let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7035        let b = _mm512_set1_epi64(-1);
7036        let mask = 0b01100110;
7037        let r = _mm512_mask_cmplt_epi64_mask(mask, a, b);
7038        assert_eq!(r, 0b00000100);
7039    }
7040
7041    #[simd_test(enable = "avx512f,avx512vl")]
7042    unsafe fn test_mm256_cmplt_epi64_mask() {
7043        let a = _mm256_set_epi64x(0, 1, -1, -13);
7044        let b = _mm256_set1_epi64x(-1);
7045        let r = _mm256_cmplt_epi64_mask(a, b);
7046        assert_eq!(r, 0b00000001);
7047    }
7048
7049    #[simd_test(enable = "avx512f,avx512vl")]
7050    unsafe fn test_mm256_mask_cmplt_epi64_mask() {
7051        let a = _mm256_set_epi64x(0, 1, -1, -13);
7052        let b = _mm256_set1_epi64x(-1);
7053        let mask = 0b11111111;
7054        let r = _mm256_mask_cmplt_epi64_mask(mask, a, b);
7055        assert_eq!(r, 0b00000001);
7056    }
7057
7058    #[simd_test(enable = "avx512f,avx512vl")]
7059    unsafe fn test_mm_cmplt_epi64_mask() {
7060        let a = _mm_set_epi64x(-1, -13);
7061        let b = _mm_set1_epi64x(-1);
7062        let r = _mm_cmplt_epi64_mask(a, b);
7063        assert_eq!(r, 0b00000001);
7064    }
7065
7066    #[simd_test(enable = "avx512f,avx512vl")]
7067    unsafe fn test_mm_mask_cmplt_epi64_mask() {
7068        let a = _mm_set_epi64x(-1, -13);
7069        let b = _mm_set1_epi64x(-1);
7070        let mask = 0b11111111;
7071        let r = _mm_mask_cmplt_epi64_mask(mask, a, b);
7072        assert_eq!(r, 0b00000001);
7073    }
7074
7075    #[simd_test(enable = "avx512f")]
7076    unsafe fn test_mm512_cmpgt_epi64_mask() {
7077        let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7078        let b = _mm512_set1_epi64(-1);
7079        let m = _mm512_cmpgt_epi64_mask(b, a);
7080        assert_eq!(m, 0b00000101);
7081    }
7082
7083    #[simd_test(enable = "avx512f")]
7084    unsafe fn test_mm512_mask_cmpgt_epi64_mask() {
7085        let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7086        let b = _mm512_set1_epi64(-1);
7087        let mask = 0b01100110;
7088        let r = _mm512_mask_cmpgt_epi64_mask(mask, b, a);
7089        assert_eq!(r, 0b00000100);
7090    }
7091
7092    #[simd_test(enable = "avx512f,avx512vl")]
7093    unsafe fn test_mm256_cmpgt_epi64_mask() {
7094        let a = _mm256_set_epi64x(0, 1, -1, 13);
7095        let b = _mm256_set1_epi64x(-1);
7096        let r = _mm256_cmpgt_epi64_mask(a, b);
7097        assert_eq!(r, 0b00001101);
7098    }
7099
7100    #[simd_test(enable = "avx512f,avx512vl")]
7101    unsafe fn test_mm256_mask_cmpgt_epi64_mask() {
7102        let a = _mm256_set_epi64x(0, 1, -1, 13);
7103        let b = _mm256_set1_epi64x(-1);
7104        let mask = 0b11111111;
7105        let r = _mm256_mask_cmpgt_epi64_mask(mask, a, b);
7106        assert_eq!(r, 0b00001101);
7107    }
7108
7109    #[simd_test(enable = "avx512f,avx512vl")]
7110    unsafe fn test_mm_cmpgt_epi64_mask() {
7111        let a = _mm_set_epi64x(0, -1);
7112        let b = _mm_set1_epi64x(-1);
7113        let r = _mm_cmpgt_epi64_mask(a, b);
7114        assert_eq!(r, 0b00000010);
7115    }
7116
7117    #[simd_test(enable = "avx512f,avx512vl")]
7118    unsafe fn test_mm_mask_cmpgt_epi64_mask() {
7119        let a = _mm_set_epi64x(0, -1);
7120        let b = _mm_set1_epi64x(-1);
7121        let mask = 0b11111111;
7122        let r = _mm_mask_cmpgt_epi64_mask(mask, a, b);
7123        assert_eq!(r, 0b00000010);
7124    }
7125
7126    #[simd_test(enable = "avx512f")]
7127    unsafe fn test_mm512_cmple_epi64_mask() {
7128        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
7129        let b = _mm512_set1_epi64(-1);
7130        assert_eq!(
7131            _mm512_cmple_epi64_mask(a, b),
7132            !_mm512_cmpgt_epi64_mask(a, b)
7133        )
7134    }
7135
7136    #[simd_test(enable = "avx512f")]
7137    unsafe fn test_mm512_mask_cmple_epi64_mask() {
7138        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
7139        let b = _mm512_set1_epi64(-1);
7140        let mask = 0b01111010;
7141        assert_eq!(_mm512_mask_cmple_epi64_mask(mask, a, b), 0b00110000);
7142    }
7143
7144    #[simd_test(enable = "avx512f,avx512vl")]
7145    unsafe fn test_mm256_cmple_epi64_mask() {
7146        let a = _mm256_set_epi64x(0, 1, -1, i64::MAX);
7147        let b = _mm256_set1_epi64x(-1);
7148        let r = _mm256_cmple_epi64_mask(a, b);
7149        assert_eq!(r, 0b00000010)
7150    }
7151
7152    #[simd_test(enable = "avx512f,avx512vl")]
7153    unsafe fn test_mm256_mask_cmple_epi64_mask() {
7154        let a = _mm256_set_epi64x(0, 1, -1, i64::MAX);
7155        let b = _mm256_set1_epi64x(-1);
7156        let mask = 0b11111111;
7157        let r = _mm256_mask_cmple_epi64_mask(mask, a, b);
7158        assert_eq!(r, 0b00000010)
7159    }
7160
7161    #[simd_test(enable = "avx512f,avx512vl")]
7162    unsafe fn test_mm_cmple_epi64_mask() {
7163        let a = _mm_set_epi64x(0, 1);
7164        let b = _mm_set1_epi64x(1);
7165        let r = _mm_cmple_epi64_mask(a, b);
7166        assert_eq!(r, 0b00000011)
7167    }
7168
7169    #[simd_test(enable = "avx512f,avx512vl")]
7170    unsafe fn test_mm_mask_cmple_epi64_mask() {
7171        let a = _mm_set_epi64x(0, 1);
7172        let b = _mm_set1_epi64x(1);
7173        let mask = 0b11111111;
7174        let r = _mm_mask_cmple_epi64_mask(mask, a, b);
7175        assert_eq!(r, 0b00000011)
7176    }
7177
7178    #[simd_test(enable = "avx512f")]
7179    unsafe fn test_mm512_cmpge_epi64_mask() {
7180        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
7181        let b = _mm512_set1_epi64(-1);
7182        assert_eq!(
7183            _mm512_cmpge_epi64_mask(a, b),
7184            !_mm512_cmplt_epi64_mask(a, b)
7185        )
7186    }
7187
7188    #[simd_test(enable = "avx512f")]
7189    unsafe fn test_mm512_mask_cmpge_epi64_mask() {
7190        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
7191        let b = _mm512_set1_epi64(-1);
7192        let mask = 0b11111111;
7193        let r = _mm512_mask_cmpge_epi64_mask(mask, a, b);
7194        assert_eq!(r, 0b11111010);
7195    }
7196
7197    #[simd_test(enable = "avx512f,avx512vl")]
7198    unsafe fn test_mm256_cmpge_epi64_mask() {
7199        let a = _mm256_set_epi64x(0, 1, -1, i64::MAX);
7200        let b = _mm256_set1_epi64x(-1);
7201        let r = _mm256_cmpge_epi64_mask(a, b);
7202        assert_eq!(r, 0b00001111);
7203    }
7204
7205    #[simd_test(enable = "avx512f,avx512vl")]
7206    unsafe fn test_mm256_mask_cmpge_epi64_mask() {
7207        let a = _mm256_set_epi64x(0, 1, -1, i64::MAX);
7208        let b = _mm256_set1_epi64x(-1);
7209        let mask = 0b11111111;
7210        let r = _mm256_mask_cmpge_epi64_mask(mask, a, b);
7211        assert_eq!(r, 0b00001111);
7212    }
7213
7214    #[simd_test(enable = "avx512f,avx512vl")]
7215    unsafe fn test_mm_cmpge_epi64_mask() {
7216        let a = _mm_set_epi64x(0, 1);
7217        let b = _mm_set1_epi64x(-1);
7218        let r = _mm_cmpge_epi64_mask(a, b);
7219        assert_eq!(r, 0b00000011);
7220    }
7221
7222    #[simd_test(enable = "avx512f,avx512vl")]
7223    unsafe fn test_mm_mask_cmpge_epi64_mask() {
7224        let a = _mm_set_epi64x(0, 1);
7225        let b = _mm_set1_epi64x(-1);
7226        let mask = 0b11111111;
7227        let r = _mm_mask_cmpge_epi64_mask(mask, a, b);
7228        assert_eq!(r, 0b00000011);
7229    }
7230
7231    #[simd_test(enable = "avx512f")]
7232    unsafe fn test_mm512_cmpeq_epi64_mask() {
7233        let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7234        let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
7235        let m = _mm512_cmpeq_epi64_mask(b, a);
7236        assert_eq!(m, 0b11001111);
7237    }
7238
7239    #[simd_test(enable = "avx512f")]
7240    unsafe fn test_mm512_mask_cmpeq_epi64_mask() {
7241        let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7242        let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
7243        let mask = 0b01111010;
7244        let r = _mm512_mask_cmpeq_epi64_mask(mask, b, a);
7245        assert_eq!(r, 0b01001010);
7246    }
7247
7248    #[simd_test(enable = "avx512f,avx512vl")]
7249    unsafe fn test_mm256_cmpeq_epi64_mask() {
7250        let a = _mm256_set_epi64x(0, 1, -1, 13);
7251        let b = _mm256_set_epi64x(0, 1, 13, 42);
7252        let m = _mm256_cmpeq_epi64_mask(b, a);
7253        assert_eq!(m, 0b00001100);
7254    }
7255
7256    #[simd_test(enable = "avx512f,avx512vl")]
7257    unsafe fn test_mm256_mask_cmpeq_epi64_mask() {
7258        let a = _mm256_set_epi64x(0, 1, -1, 13);
7259        let b = _mm256_set_epi64x(0, 1, 13, 42);
7260        let mask = 0b11111111;
7261        let r = _mm256_mask_cmpeq_epi64_mask(mask, b, a);
7262        assert_eq!(r, 0b00001100);
7263    }
7264
7265    #[simd_test(enable = "avx512f,avx512vl")]
7266    unsafe fn test_mm_cmpeq_epi64_mask() {
7267        let a = _mm_set_epi64x(0, 1);
7268        let b = _mm_set_epi64x(0, 1);
7269        let m = _mm_cmpeq_epi64_mask(b, a);
7270        assert_eq!(m, 0b00000011);
7271    }
7272
7273    #[simd_test(enable = "avx512f,avx512vl")]
7274    unsafe fn test_mm_mask_cmpeq_epi64_mask() {
7275        let a = _mm_set_epi64x(0, 1);
7276        let b = _mm_set_epi64x(0, 1);
7277        let mask = 0b11111111;
7278        let r = _mm_mask_cmpeq_epi64_mask(mask, b, a);
7279        assert_eq!(r, 0b00000011);
7280    }
7281
7282    #[simd_test(enable = "avx512f")]
7283    unsafe fn test_mm512_set_epi64() {
7284        let r = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
7285        assert_eq_m512i(r, _mm512_set_epi64(7, 6, 5, 4, 3, 2, 1, 0))
7286    }
7287
7288    #[simd_test(enable = "avx512f")]
7289    unsafe fn test_mm512_setr_epi64() {
7290        let r = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
7291        assert_eq_m512i(r, _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0))
7292    }
7293
7294    unsafe fn test_mm512_cmpneq_epi64_mask() {
7295        let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7296        let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
7297        let m = _mm512_cmpneq_epi64_mask(b, a);
7298        assert_eq!(m, !_mm512_cmpeq_epi64_mask(b, a));
7299    }
7300
7301    #[simd_test(enable = "avx512f")]
7302    unsafe fn test_mm512_mask_cmpneq_epi64_mask() {
7303        let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, -100, 100);
7304        let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
7305        let mask = 0b01111010;
7306        let r = _mm512_mask_cmpneq_epi64_mask(mask, b, a);
7307        assert_eq!(r, 0b00110010)
7308    }
7309
7310    #[simd_test(enable = "avx512f,avx512vl")]
7311    unsafe fn test_mm256_cmpneq_epi64_mask() {
7312        let a = _mm256_set_epi64x(0, 1, -1, 13);
7313        let b = _mm256_set_epi64x(0, 1, 13, 42);
7314        let r = _mm256_cmpneq_epi64_mask(b, a);
7315        assert_eq!(r, 0b00000011)
7316    }
7317
7318    #[simd_test(enable = "avx512f,avx512vl")]
7319    unsafe fn test_mm256_mask_cmpneq_epi64_mask() {
7320        let a = _mm256_set_epi64x(0, 1, -1, 13);
7321        let b = _mm256_set_epi64x(0, 1, 13, 42);
7322        let mask = 0b11111111;
7323        let r = _mm256_mask_cmpneq_epi64_mask(mask, b, a);
7324        assert_eq!(r, 0b00000011)
7325    }
7326
7327    #[simd_test(enable = "avx512f,avx512vl")]
7328    unsafe fn test_mm_cmpneq_epi64_mask() {
7329        let a = _mm_set_epi64x(-1, 13);
7330        let b = _mm_set_epi64x(13, 42);
7331        let r = _mm_cmpneq_epi64_mask(b, a);
7332        assert_eq!(r, 0b00000011)
7333    }
7334
7335    #[simd_test(enable = "avx512f,avx512vl")]
7336    unsafe fn test_mm_mask_cmpneq_epi64_mask() {
7337        let a = _mm_set_epi64x(-1, 13);
7338        let b = _mm_set_epi64x(13, 42);
7339        let mask = 0b11111111;
7340        let r = _mm_mask_cmpneq_epi64_mask(mask, b, a);
7341        assert_eq!(r, 0b00000011)
7342    }
7343
7344    #[simd_test(enable = "avx512f")]
7345    unsafe fn test_mm512_cmp_epi64_mask() {
7346        let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7347        let b = _mm512_set1_epi64(-1);
7348        let m = _mm512_cmp_epi64_mask::<_MM_CMPINT_LT>(a, b);
7349        assert_eq!(m, 0b00000101);
7350    }
7351
7352    #[simd_test(enable = "avx512f")]
7353    unsafe fn test_mm512_mask_cmp_epi64_mask() {
7354        let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7355        let b = _mm512_set1_epi64(-1);
7356        let mask = 0b01100110;
7357        let r = _mm512_mask_cmp_epi64_mask::<_MM_CMPINT_LT>(mask, a, b);
7358        assert_eq!(r, 0b00000100);
7359    }
7360
7361    #[simd_test(enable = "avx512f,avx512vl")]
7362    unsafe fn test_mm256_cmp_epi64_mask() {
7363        let a = _mm256_set_epi64x(0, 1, -1, 13);
7364        let b = _mm256_set1_epi64x(1);
7365        let m = _mm256_cmp_epi64_mask::<_MM_CMPINT_LT>(a, b);
7366        assert_eq!(m, 0b00001010);
7367    }
7368
7369    #[simd_test(enable = "avx512f,avx512vl")]
7370    unsafe fn test_mm256_mask_cmp_epi64_mask() {
7371        let a = _mm256_set_epi64x(0, 1, -1, 13);
7372        let b = _mm256_set1_epi64x(1);
7373        let mask = 0b11111111;
7374        let r = _mm256_mask_cmp_epi64_mask::<_MM_CMPINT_LT>(mask, a, b);
7375        assert_eq!(r, 0b00001010);
7376    }
7377
7378    #[simd_test(enable = "avx512f,avx512vl")]
7379    unsafe fn test_mm_cmp_epi64_mask() {
7380        let a = _mm_set_epi64x(0, 1);
7381        let b = _mm_set1_epi64x(1);
7382        let m = _mm_cmp_epi64_mask::<_MM_CMPINT_LT>(a, b);
7383        assert_eq!(m, 0b00000010);
7384    }
7385
7386    #[simd_test(enable = "avx512f,avx512vl")]
7387    unsafe fn test_mm_mask_cmp_epi64_mask() {
7388        let a = _mm_set_epi64x(0, 1);
7389        let b = _mm_set1_epi64x(1);
7390        let mask = 0b11111111;
7391        let r = _mm_mask_cmp_epi64_mask::<_MM_CMPINT_LT>(mask, a, b);
7392        assert_eq!(r, 0b00000010);
7393    }
7394
7395    #[simd_test(enable = "avx512f")]
7396    unsafe fn test_mm512_i32gather_pd() {
7397        let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
7398        // A multiplier of 8 is word-addressing
7399        let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7400        let r = _mm512_i32gather_pd::<8>(index, arr.as_ptr() as *const u8);
7401        assert_eq_m512d(r, _mm512_setr_pd(0., 16., 32., 48., 64., 80., 96., 112.));
7402    }
7403
7404    #[simd_test(enable = "avx512f")]
7405    unsafe fn test_mm512_mask_i32gather_pd() {
7406        let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
7407        let src = _mm512_set1_pd(2.);
7408        let mask = 0b10101010;
7409        let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7410        // A multiplier of 8 is word-addressing
7411        let r = _mm512_mask_i32gather_pd::<8>(src, mask, index, arr.as_ptr() as *const u8);
7412        assert_eq_m512d(r, _mm512_setr_pd(2., 16., 2., 48., 2., 80., 2., 112.));
7413    }
7414
7415    #[simd_test(enable = "avx512f")]
7416    unsafe fn test_mm512_i64gather_pd() {
7417        let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
7418        // A multiplier of 8 is word-addressing
7419        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7420        let r = _mm512_i64gather_pd::<8>(index, arr.as_ptr() as *const u8);
7421        assert_eq_m512d(r, _mm512_setr_pd(0., 16., 32., 48., 64., 80., 96., 112.));
7422    }
7423
7424    #[simd_test(enable = "avx512f")]
7425    unsafe fn test_mm512_mask_i64gather_pd() {
7426        let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
7427        let src = _mm512_set1_pd(2.);
7428        let mask = 0b10101010;
7429        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7430        // A multiplier of 8 is word-addressing
7431        let r = _mm512_mask_i64gather_pd::<8>(src, mask, index, arr.as_ptr() as *const u8);
7432        assert_eq_m512d(r, _mm512_setr_pd(2., 16., 2., 48., 2., 80., 2., 112.));
7433    }
7434
7435    #[simd_test(enable = "avx512f")]
7436    unsafe fn test_mm512_i64gather_ps() {
7437        let arr: [f32; 128] = core::array::from_fn(|i| i as f32);
7438        // A multiplier of 4 is word-addressing
7439        #[rustfmt::skip]
7440        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7441        let r = _mm512_i64gather_ps::<4>(index, arr.as_ptr() as *const u8);
7442        assert_eq_m256(r, _mm256_setr_ps(0., 16., 32., 48., 64., 80., 96., 112.));
7443    }
7444
7445    #[simd_test(enable = "avx512f")]
7446    unsafe fn test_mm512_mask_i64gather_ps() {
7447        let arr: [f32; 128] = core::array::from_fn(|i| i as f32);
7448        let src = _mm256_set1_ps(2.);
7449        let mask = 0b10101010;
7450        #[rustfmt::skip]
7451        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7452        // A multiplier of 4 is word-addressing
7453        let r = _mm512_mask_i64gather_ps::<4>(src, mask, index, arr.as_ptr() as *const u8);
7454        assert_eq_m256(r, _mm256_setr_ps(2., 16., 2., 48., 2., 80., 2., 112.));
7455    }
7456
7457    #[simd_test(enable = "avx512f")]
7458    unsafe fn test_mm512_i32gather_epi64() {
7459        let mut arr = [0i64; 128];
7460        for i in 0..128i64 {
7461            arr[i as usize] = i;
7462        }
7463        // A multiplier of 8 is word-addressing
7464        let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7465        let r = _mm512_i32gather_epi64::<8>(index, arr.as_ptr() as *const u8);
7466        assert_eq_m512i(r, _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112));
7467    }
7468
7469    #[simd_test(enable = "avx512f")]
7470    unsafe fn test_mm512_mask_i32gather_epi64() {
7471        let mut arr = [0i64; 128];
7472        for i in 0..128i64 {
7473            arr[i as usize] = i;
7474        }
7475        let src = _mm512_set1_epi64(2);
7476        let mask = 0b10101010;
7477        let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7478        // A multiplier of 8 is word-addressing
7479        let r = _mm512_mask_i32gather_epi64::<8>(src, mask, index, arr.as_ptr() as *const u8);
7480        assert_eq_m512i(r, _mm512_setr_epi64(2, 16, 2, 48, 2, 80, 2, 112));
7481    }
7482
7483    #[simd_test(enable = "avx512f")]
7484    unsafe fn test_mm512_i64gather_epi64() {
7485        let mut arr = [0i64; 128];
7486        for i in 0..128i64 {
7487            arr[i as usize] = i;
7488        }
7489        // A multiplier of 8 is word-addressing
7490        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7491        let r = _mm512_i64gather_epi64::<8>(index, arr.as_ptr() as *const u8);
7492        assert_eq_m512i(r, _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112));
7493    }
7494
7495    #[simd_test(enable = "avx512f")]
7496    unsafe fn test_mm512_mask_i64gather_epi64() {
7497        let mut arr = [0i64; 128];
7498        for i in 0..128i64 {
7499            arr[i as usize] = i;
7500        }
7501        let src = _mm512_set1_epi64(2);
7502        let mask = 0b10101010;
7503        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7504        // A multiplier of 8 is word-addressing
7505        let r = _mm512_mask_i64gather_epi64::<8>(src, mask, index, arr.as_ptr() as *const u8);
7506        assert_eq_m512i(r, _mm512_setr_epi64(2, 16, 2, 48, 2, 80, 2, 112));
7507    }
7508
7509    #[simd_test(enable = "avx512f")]
7510    unsafe fn test_mm512_i64gather_epi32() {
7511        let mut arr = [0i64; 128];
7512        for i in 0..128i64 {
7513            arr[i as usize] = i;
7514        }
7515        // A multiplier of 8 is word-addressing
7516        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7517        let r = _mm512_i64gather_epi32::<8>(index, arr.as_ptr() as *const u8);
7518        assert_eq_m256i(r, _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112));
7519    }
7520
7521    #[simd_test(enable = "avx512f")]
7522    unsafe fn test_mm512_mask_i64gather_epi32() {
7523        let mut arr = [0i64; 128];
7524        for i in 0..128i64 {
7525            arr[i as usize] = i;
7526        }
7527        let src = _mm256_set1_epi32(2);
7528        let mask = 0b10101010;
7529        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7530        // A multiplier of 8 is word-addressing
7531        let r = _mm512_mask_i64gather_epi32::<8>(src, mask, index, arr.as_ptr() as *const u8);
7532        assert_eq_m256i(r, _mm256_setr_epi32(2, 16, 2, 48, 2, 80, 2, 112));
7533    }
7534
7535    #[simd_test(enable = "avx512f")]
7536    unsafe fn test_mm512_i32scatter_pd() {
7537        let mut arr = [0f64; 128];
7538        let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7539        let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
7540        // A multiplier of 8 is word-addressing
7541        _mm512_i32scatter_pd::<8>(arr.as_mut_ptr() as *mut u8, index, src);
7542        let mut expected = [0f64; 128];
7543        for i in 0..8 {
7544            expected[i * 16] = (i + 1) as f64;
7545        }
7546        assert_eq!(&arr[..], &expected[..],);
7547    }
7548
7549    #[simd_test(enable = "avx512f")]
7550    unsafe fn test_mm512_mask_i32scatter_pd() {
7551        let mut arr = [0f64; 128];
7552        let mask = 0b10101010;
7553        let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7554        let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
7555        // A multiplier of 8 is word-addressing
7556        _mm512_mask_i32scatter_pd::<8>(arr.as_mut_ptr() as *mut u8, mask, index, src);
7557        let mut expected = [0f64; 128];
7558        for i in 0..4 {
7559            expected[i * 32 + 16] = 2. * (i + 1) as f64;
7560        }
7561        assert_eq!(&arr[..], &expected[..],);
7562    }
7563
7564    #[simd_test(enable = "avx512f")]
7565    unsafe fn test_mm512_i64scatter_pd() {
7566        let mut arr = [0f64; 128];
7567        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7568        let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
7569        // A multiplier of 8 is word-addressing
7570        _mm512_i64scatter_pd::<8>(arr.as_mut_ptr() as *mut u8, index, src);
7571        let mut expected = [0f64; 128];
7572        for i in 0..8 {
7573            expected[i * 16] = (i + 1) as f64;
7574        }
7575        assert_eq!(&arr[..], &expected[..],);
7576    }
7577
7578    #[simd_test(enable = "avx512f")]
7579    unsafe fn test_mm512_mask_i64scatter_pd() {
7580        let mut arr = [0f64; 128];
7581        let mask = 0b10101010;
7582        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7583        let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
7584        // A multiplier of 8 is word-addressing
7585        _mm512_mask_i64scatter_pd::<8>(arr.as_mut_ptr() as *mut u8, mask, index, src);
7586        let mut expected = [0f64; 128];
7587        for i in 0..4 {
7588            expected[i * 32 + 16] = 2. * (i + 1) as f64;
7589        }
7590        assert_eq!(&arr[..], &expected[..],);
7591    }
7592
7593    #[simd_test(enable = "avx512f")]
7594    unsafe fn test_mm512_i64scatter_ps() {
7595        let mut arr = [0f32; 128];
7596        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7597        let src = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
7598        // A multiplier of 4 is word-addressing
7599        _mm512_i64scatter_ps::<4>(arr.as_mut_ptr() as *mut u8, index, src);
7600        let mut expected = [0f32; 128];
7601        for i in 0..8 {
7602            expected[i * 16] = (i + 1) as f32;
7603        }
7604        assert_eq!(&arr[..], &expected[..],);
7605    }
7606
7607    #[simd_test(enable = "avx512f")]
7608    unsafe fn test_mm512_mask_i64scatter_ps() {
7609        let mut arr = [0f32; 128];
7610        let mask = 0b10101010;
7611        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7612        let src = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
7613        // A multiplier of 4 is word-addressing
7614        _mm512_mask_i64scatter_ps::<4>(arr.as_mut_ptr() as *mut u8, mask, index, src);
7615        let mut expected = [0f32; 128];
7616        for i in 0..4 {
7617            expected[i * 32 + 16] = 2. * (i + 1) as f32;
7618        }
7619        assert_eq!(&arr[..], &expected[..],);
7620    }
7621
7622    #[simd_test(enable = "avx512f")]
7623    unsafe fn test_mm512_i32scatter_epi64() {
7624        let mut arr = [0i64; 128];
7625        let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7626        let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
7627        // A multiplier of 8 is word-addressing
7628        _mm512_i32scatter_epi64::<8>(arr.as_mut_ptr() as *mut u8, index, src);
7629        let mut expected = [0i64; 128];
7630        for i in 0..8 {
7631            expected[i * 16] = (i + 1) as i64;
7632        }
7633        assert_eq!(&arr[..], &expected[..],);
7634    }
7635
7636    #[simd_test(enable = "avx512f")]
7637    unsafe fn test_mm512_mask_i32scatter_epi64() {
7638        let mut arr = [0i64; 128];
7639        let mask = 0b10101010;
7640        let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7641        let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
7642        // A multiplier of 8 is word-addressing
7643        _mm512_mask_i32scatter_epi64::<8>(arr.as_mut_ptr() as *mut u8, mask, index, src);
7644        let mut expected = [0i64; 128];
7645        for i in 0..4 {
7646            expected[i * 32 + 16] = 2 * (i + 1) as i64;
7647        }
7648        assert_eq!(&arr[..], &expected[..],);
7649    }
7650
7651    #[simd_test(enable = "avx512f")]
7652    unsafe fn test_mm512_i64scatter_epi64() {
7653        let mut arr = [0i64; 128];
7654        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7655        let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
7656        // A multiplier of 8 is word-addressing
7657        _mm512_i64scatter_epi64::<8>(arr.as_mut_ptr() as *mut u8, index, src);
7658        let mut expected = [0i64; 128];
7659        for i in 0..8 {
7660            expected[i * 16] = (i + 1) as i64;
7661        }
7662        assert_eq!(&arr[..], &expected[..],);
7663    }
7664
7665    #[simd_test(enable = "avx512f")]
7666    unsafe fn test_mm512_mask_i64scatter_epi64() {
7667        let mut arr = [0i64; 128];
7668        let mask = 0b10101010;
7669        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7670        let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
7671        // A multiplier of 8 is word-addressing
7672        _mm512_mask_i64scatter_epi64::<8>(arr.as_mut_ptr() as *mut u8, mask, index, src);
7673        let mut expected = [0i64; 128];
7674        for i in 0..4 {
7675            expected[i * 32 + 16] = 2 * (i + 1) as i64;
7676        }
7677        assert_eq!(&arr[..], &expected[..],);
7678    }
7679
7680    #[simd_test(enable = "avx512f")]
7681    unsafe fn test_mm512_i64scatter_epi32() {
7682        let mut arr = [0i32; 128];
7683        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7684        let src = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
7685        // A multiplier of 4 is word-addressing
7686        _mm512_i64scatter_epi32::<4>(arr.as_mut_ptr() as *mut u8, index, src);
7687        let mut expected = [0i32; 128];
7688        for i in 0..8 {
7689            expected[i * 16] = (i + 1) as i32;
7690        }
7691        assert_eq!(&arr[..], &expected[..],);
7692    }
7693
7694    #[simd_test(enable = "avx512f")]
7695    unsafe fn test_mm512_mask_i64scatter_epi32() {
7696        let mut arr = [0i32; 128];
7697        let mask = 0b10101010;
7698        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7699        let src = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
7700        // A multiplier of 4 is word-addressing
7701        _mm512_mask_i64scatter_epi32::<4>(arr.as_mut_ptr() as *mut u8, mask, index, src);
7702        let mut expected = [0i32; 128];
7703        for i in 0..4 {
7704            expected[i * 32 + 16] = 2 * (i + 1) as i32;
7705        }
7706        assert_eq!(&arr[..], &expected[..],);
7707    }
7708
7709    #[simd_test(enable = "avx512f")]
7710    unsafe fn test_mm512_i32logather_epi64() {
7711        let base_addr: [i64; 8] = [1, 2, 3, 4, 5, 6, 7, 8];
7712        let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7713        let r = _mm512_i32logather_epi64::<8>(vindex, base_addr.as_ptr().cast());
7714        let expected = _mm512_setr_epi64(2, 3, 4, 5, 6, 7, 8, 1);
7715        assert_eq_m512i(expected, r);
7716    }
7717
7718    #[simd_test(enable = "avx512f")]
7719    unsafe fn test_mm512_mask_i32logather_epi64() {
7720        let base_addr: [i64; 8] = [1, 2, 3, 4, 5, 6, 7, 8];
7721        let src = _mm512_setr_epi64(9, 10, 11, 12, 13, 14, 15, 16);
7722        let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7723        let r =
7724            _mm512_mask_i32logather_epi64::<8>(src, 0b01010101, vindex, base_addr.as_ptr().cast());
7725        let expected = _mm512_setr_epi64(2, 10, 4, 12, 6, 14, 8, 16);
7726        assert_eq_m512i(expected, r);
7727    }
7728
7729    #[simd_test(enable = "avx512f")]
7730    unsafe fn test_mm512_i32logather_pd() {
7731        let base_addr: [f64; 8] = [1., 2., 3., 4., 5., 6., 7., 8.];
7732        let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7733        let r = _mm512_i32logather_pd::<8>(vindex, base_addr.as_ptr().cast());
7734        let expected = _mm512_setr_pd(2., 3., 4., 5., 6., 7., 8., 1.);
7735        assert_eq_m512d(expected, r);
7736    }
7737
7738    #[simd_test(enable = "avx512f")]
7739    unsafe fn test_mm512_mask_i32logather_pd() {
7740        let base_addr: [f64; 8] = [1., 2., 3., 4., 5., 6., 7., 8.];
7741        let src = _mm512_setr_pd(9., 10., 11., 12., 13., 14., 15., 16.);
7742        let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7743        let r = _mm512_mask_i32logather_pd::<8>(src, 0b01010101, vindex, base_addr.as_ptr().cast());
7744        let expected = _mm512_setr_pd(2., 10., 4., 12., 6., 14., 8., 16.);
7745        assert_eq_m512d(expected, r);
7746    }
7747
7748    #[simd_test(enable = "avx512f")]
7749    unsafe fn test_mm512_i32loscatter_epi64() {
7750        let mut base_addr: [i64; 8] = [0; 8];
7751        let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7752        let src = _mm512_setr_epi64(2, 3, 4, 5, 6, 7, 8, 1);
7753        _mm512_i32loscatter_epi64::<8>(base_addr.as_mut_ptr().cast(), vindex, src);
7754        let expected = [1, 2, 3, 4, 5, 6, 7, 8];
7755        assert_eq!(expected, base_addr);
7756    }
7757
7758    #[simd_test(enable = "avx512f")]
7759    unsafe fn test_mm512_mask_i32loscatter_epi64() {
7760        let mut base_addr: [i64; 8] = [0; 8];
7761        let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7762        let src = _mm512_setr_epi64(2, 3, 4, 5, 6, 7, 8, 1);
7763        _mm512_mask_i32loscatter_epi64::<8>(base_addr.as_mut_ptr().cast(), 0b01010101, vindex, src);
7764        let expected = [0, 2, 0, 4, 0, 6, 0, 8];
7765        assert_eq!(expected, base_addr);
7766    }
7767
7768    #[simd_test(enable = "avx512f")]
7769    unsafe fn test_mm512_i32loscatter_pd() {
7770        let mut base_addr: [f64; 8] = [0.; 8];
7771        let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7772        let src = _mm512_setr_pd(2., 3., 4., 5., 6., 7., 8., 1.);
7773        _mm512_i32loscatter_pd::<8>(base_addr.as_mut_ptr().cast(), vindex, src);
7774        let expected = [1., 2., 3., 4., 5., 6., 7., 8.];
7775        assert_eq!(expected, base_addr);
7776    }
7777
7778    #[simd_test(enable = "avx512f")]
7779    unsafe fn test_mm512_mask_i32loscatter_pd() {
7780        let mut base_addr: [f64; 8] = [0.; 8];
7781        let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7782        let src = _mm512_setr_pd(2., 3., 4., 5., 6., 7., 8., 1.);
7783        _mm512_mask_i32loscatter_pd::<8>(base_addr.as_mut_ptr().cast(), 0b01010101, vindex, src);
7784        let expected = [0., 2., 0., 4., 0., 6., 0., 8.];
7785        assert_eq!(expected, base_addr);
7786    }
7787
7788    #[simd_test(enable = "avx512f,avx512vl")]
7789    unsafe fn test_mm_mmask_i32gather_epi32() {
7790        let base_addr: [i32; 4] = [1, 2, 3, 4];
7791        let src = _mm_setr_epi32(5, 6, 7, 8);
7792        let vindex = _mm_setr_epi32(1, 2, 3, 0);
7793        let r = _mm_mmask_i32gather_epi32::<4>(src, 0b0101, vindex, base_addr.as_ptr().cast());
7794        let expected = _mm_setr_epi32(2, 6, 4, 8);
7795        assert_eq_m128i(expected, r);
7796    }
7797
7798    #[simd_test(enable = "avx512f,avx512vl")]
7799    unsafe fn test_mm_mmask_i32gather_epi64() {
7800        let base_addr: [i64; 2] = [1, 2];
7801        let src = _mm_setr_epi64x(5, 6);
7802        let vindex = _mm_setr_epi32(1, 0, -1, -1);
7803        let r = _mm_mmask_i32gather_epi64::<8>(src, 0b01, vindex, base_addr.as_ptr().cast());
7804        let expected = _mm_setr_epi64x(2, 6);
7805        assert_eq_m128i(expected, r);
7806    }
7807
7808    #[simd_test(enable = "avx512f,avx512vl")]
7809    unsafe fn test_mm_mmask_i32gather_pd() {
7810        let base_addr: [f64; 2] = [1., 2.];
7811        let src = _mm_setr_pd(5., 6.);
7812        let vindex = _mm_setr_epi32(1, 0, -1, -1);
7813        let r = _mm_mmask_i32gather_pd::<8>(src, 0b01, vindex, base_addr.as_ptr().cast());
7814        let expected = _mm_setr_pd(2., 6.);
7815        assert_eq_m128d(expected, r);
7816    }
7817
7818    #[simd_test(enable = "avx512f,avx512vl")]
7819    unsafe fn test_mm_mmask_i32gather_ps() {
7820        let base_addr: [f32; 4] = [1., 2., 3., 4.];
7821        let src = _mm_setr_ps(5., 6., 7., 8.);
7822        let vindex = _mm_setr_epi32(1, 2, 3, 0);
7823        let r = _mm_mmask_i32gather_ps::<4>(src, 0b0101, vindex, base_addr.as_ptr().cast());
7824        let expected = _mm_setr_ps(2., 6., 4., 8.);
7825        assert_eq_m128(expected, r);
7826    }
7827
7828    #[simd_test(enable = "avx512f,avx512vl")]
7829    unsafe fn test_mm_mmask_i64gather_epi32() {
7830        let base_addr: [i32; 2] = [1, 2];
7831        let src = _mm_setr_epi32(5, 6, 7, 8);
7832        let vindex = _mm_setr_epi64x(1, 0);
7833        let r = _mm_mmask_i64gather_epi32::<4>(src, 0b01, vindex, base_addr.as_ptr().cast());
7834        let expected = _mm_setr_epi32(2, 6, 0, 0);
7835        assert_eq_m128i(expected, r);
7836    }
7837
7838    #[simd_test(enable = "avx512f,avx512vl")]
7839    unsafe fn test_mm_mmask_i64gather_epi64() {
7840        let base_addr: [i64; 2] = [1, 2];
7841        let src = _mm_setr_epi64x(5, 6);
7842        let vindex = _mm_setr_epi64x(1, 0);
7843        let r = _mm_mmask_i64gather_epi64::<8>(src, 0b01, vindex, base_addr.as_ptr().cast());
7844        let expected = _mm_setr_epi64x(2, 6);
7845        assert_eq_m128i(expected, r);
7846    }
7847
7848    #[simd_test(enable = "avx512f,avx512vl")]
7849    unsafe fn test_mm_mmask_i64gather_pd() {
7850        let base_addr: [f64; 2] = [1., 2.];
7851        let src = _mm_setr_pd(5., 6.);
7852        let vindex = _mm_setr_epi64x(1, 0);
7853        let r = _mm_mmask_i64gather_pd::<8>(src, 0b01, vindex, base_addr.as_ptr().cast());
7854        let expected = _mm_setr_pd(2., 6.);
7855        assert_eq_m128d(expected, r);
7856    }
7857
7858    #[simd_test(enable = "avx512f,avx512vl")]
7859    unsafe fn test_mm_mmask_i64gather_ps() {
7860        let base_addr: [f32; 2] = [1., 2.];
7861        let src = _mm_setr_ps(5., 6., 7., 8.);
7862        let vindex = _mm_setr_epi64x(1, 0);
7863        let r = _mm_mmask_i64gather_ps::<4>(src, 0b01, vindex, base_addr.as_ptr().cast());
7864        let expected = _mm_setr_ps(2., 6., 0., 0.);
7865        assert_eq_m128(expected, r);
7866    }
7867
7868    #[simd_test(enable = "avx512f,avx512vl")]
7869    unsafe fn test_mm256_mmask_i32gather_epi32() {
7870        let base_addr: [i32; 8] = [1, 2, 3, 4, 5, 6, 7, 8];
7871        let src = _mm256_setr_epi32(9, 10, 11, 12, 13, 14, 15, 16);
7872        let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
7873        let r =
7874            _mm256_mmask_i32gather_epi32::<4>(src, 0b01010101, vindex, base_addr.as_ptr().cast());
7875        let expected = _mm256_setr_epi32(2, 10, 4, 12, 6, 14, 8, 16);
7876        assert_eq_m256i(expected, r);
7877    }
7878
7879    #[simd_test(enable = "avx512f,avx512vl")]
7880    unsafe fn test_mm256_mmask_i32gather_epi64() {
7881        let base_addr: [i64; 4] = [1, 2, 3, 4];
7882        let src = _mm256_setr_epi64x(9, 10, 11, 12);
7883        let vindex = _mm_setr_epi32(1, 2, 3, 4);
7884        let r = _mm256_mmask_i32gather_epi64::<8>(src, 0b0101, vindex, base_addr.as_ptr().cast());
7885        let expected = _mm256_setr_epi64x(2, 10, 4, 12);
7886        assert_eq_m256i(expected, r);
7887    }
7888
7889    #[simd_test(enable = "avx512f,avx512vl")]
7890    unsafe fn test_mm256_mmask_i32gather_pd() {
7891        let base_addr: [f64; 4] = [1., 2., 3., 4.];
7892        let src = _mm256_setr_pd(9., 10., 11., 12.);
7893        let vindex = _mm_setr_epi32(1, 2, 3, 4);
7894        let r = _mm256_mmask_i32gather_pd::<8>(src, 0b0101, vindex, base_addr.as_ptr().cast());
7895        let expected = _mm256_setr_pd(2., 10., 4., 12.);
7896        assert_eq_m256d(expected, r);
7897    }
7898
7899    #[simd_test(enable = "avx512f,avx512vl")]
7900    unsafe fn test_mm256_mmask_i32gather_ps() {
7901        let base_addr: [f32; 8] = [1., 2., 3., 4., 5., 6., 7., 8.];
7902        let src = _mm256_setr_ps(9., 10., 11., 12., 13., 14., 15., 16.);
7903        let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
7904        let r = _mm256_mmask_i32gather_ps::<4>(src, 0b01010101, vindex, base_addr.as_ptr().cast());
7905        let expected = _mm256_setr_ps(2., 10., 4., 12., 6., 14., 8., 16.);
7906        assert_eq_m256(expected, r);
7907    }
7908
7909    #[simd_test(enable = "avx512f,avx512vl")]
7910    unsafe fn test_mm256_mmask_i64gather_epi32() {
7911        let base_addr: [i32; 4] = [1, 2, 3, 4];
7912        let src = _mm_setr_epi32(9, 10, 11, 12);
7913        let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
7914        let r = _mm256_mmask_i64gather_epi32::<4>(src, 0b0101, vindex, base_addr.as_ptr().cast());
7915        let expected = _mm_setr_epi32(2, 10, 4, 12);
7916        assert_eq_m128i(expected, r);
7917    }
7918
7919    #[simd_test(enable = "avx512f,avx512vl")]
7920    unsafe fn test_mm256_mmask_i64gather_epi64() {
7921        let base_addr: [i64; 4] = [1, 2, 3, 4];
7922        let src = _mm256_setr_epi64x(9, 10, 11, 12);
7923        let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
7924        let r = _mm256_mmask_i64gather_epi64::<8>(src, 0b0101, vindex, base_addr.as_ptr().cast());
7925        let expected = _mm256_setr_epi64x(2, 10, 4, 12);
7926        assert_eq_m256i(expected, r);
7927    }
7928
7929    #[simd_test(enable = "avx512f,avx512vl")]
7930    unsafe fn test_mm256_mmask_i64gather_pd() {
7931        let base_addr: [f64; 4] = [1., 2., 3., 4.];
7932        let src = _mm256_setr_pd(9., 10., 11., 12.);
7933        let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
7934        let r = _mm256_mmask_i64gather_pd::<8>(src, 0b0101, vindex, base_addr.as_ptr().cast());
7935        let expected = _mm256_setr_pd(2., 10., 4., 12.);
7936        assert_eq_m256d(expected, r);
7937    }
7938
7939    #[simd_test(enable = "avx512f,avx512vl")]
7940    unsafe fn test_mm256_mmask_i64gather_ps() {
7941        let base_addr: [f32; 4] = [1., 2., 3., 4.];
7942        let src = _mm_setr_ps(9., 10., 11., 12.);
7943        let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
7944        let r = _mm256_mmask_i64gather_ps::<4>(src, 0b0101, vindex, base_addr.as_ptr().cast());
7945        let expected = _mm_setr_ps(2., 10., 4., 12.);
7946        assert_eq_m128(expected, r);
7947    }
7948
7949    #[simd_test(enable = "avx512f,avx512vl")]
7950    unsafe fn test_mm_i32scatter_epi32() {
7951        let mut base_addr: [i32; 4] = [0; 4];
7952        let vindex = _mm_setr_epi32(1, 2, 3, 0);
7953        let src = _mm_setr_epi32(2, 3, 4, 1);
7954        _mm_i32scatter_epi32::<4>(base_addr.as_mut_ptr().cast(), vindex, src);
7955        let expected = [1, 2, 3, 4];
7956        assert_eq!(expected, base_addr);
7957    }
7958
7959    #[simd_test(enable = "avx512f,avx512vl")]
7960    unsafe fn test_mm_mask_i32scatter_epi32() {
7961        let mut base_addr: [i32; 4] = [0; 4];
7962        let vindex = _mm_setr_epi32(1, 2, 3, 0);
7963        let src = _mm_setr_epi32(2, 3, 4, 1);
7964        _mm_mask_i32scatter_epi32::<4>(base_addr.as_mut_ptr().cast(), 0b0101, vindex, src);
7965        let expected = [0, 2, 0, 4];
7966        assert_eq!(expected, base_addr);
7967    }
7968
7969    #[simd_test(enable = "avx512f,avx512vl")]
7970    unsafe fn test_mm_i32scatter_epi64() {
7971        let mut base_addr: [i64; 2] = [0; 2];
7972        let vindex = _mm_setr_epi32(1, 0, -1, -1);
7973        let src = _mm_setr_epi64x(2, 1);
7974        _mm_i32scatter_epi64::<8>(base_addr.as_mut_ptr().cast(), vindex, src);
7975        let expected = [1, 2];
7976        assert_eq!(expected, base_addr);
7977    }
7978
7979    #[simd_test(enable = "avx512f,avx512vl")]
7980    unsafe fn test_mm_mask_i32scatter_epi64() {
7981        let mut base_addr: [i64; 2] = [0; 2];
7982        let vindex = _mm_setr_epi32(1, 0, -1, -1);
7983        let src = _mm_setr_epi64x(2, 1);
7984        _mm_mask_i32scatter_epi64::<8>(base_addr.as_mut_ptr().cast(), 0b01, vindex, src);
7985        let expected = [0, 2];
7986        assert_eq!(expected, base_addr);
7987    }
7988
7989    #[simd_test(enable = "avx512f,avx512vl")]
7990    unsafe fn test_mm_i32scatter_pd() {
7991        let mut base_addr: [f64; 2] = [0.; 2];
7992        let vindex = _mm_setr_epi32(1, 0, -1, -1);
7993        let src = _mm_setr_pd(2., 1.);
7994        _mm_i32scatter_pd::<8>(base_addr.as_mut_ptr().cast(), vindex, src);
7995        let expected = [1., 2.];
7996        assert_eq!(expected, base_addr);
7997    }
7998
7999    #[simd_test(enable = "avx512f,avx512vl")]
8000    unsafe fn test_mm_mask_i32scatter_pd() {
8001        let mut base_addr: [f64; 2] = [0.; 2];
8002        let vindex = _mm_setr_epi32(1, 0, -1, -1);
8003        let src = _mm_setr_pd(2., 1.);
8004        _mm_mask_i32scatter_pd::<8>(base_addr.as_mut_ptr().cast(), 0b01, vindex, src);
8005        let expected = [0., 2.];
8006        assert_eq!(expected, base_addr);
8007    }
8008
8009    #[simd_test(enable = "avx512f,avx512vl")]
8010    unsafe fn test_mm_i32scatter_ps() {
8011        let mut base_addr: [f32; 4] = [0.; 4];
8012        let vindex = _mm_setr_epi32(1, 2, 3, 0);
8013        let src = _mm_setr_ps(2., 3., 4., 1.);
8014        _mm_i32scatter_ps::<4>(base_addr.as_mut_ptr().cast(), vindex, src);
8015        let expected = [1., 2., 3., 4.];
8016        assert_eq!(expected, base_addr);
8017    }
8018
8019    #[simd_test(enable = "avx512f,avx512vl")]
8020    unsafe fn test_mm_mask_i32scatter_ps() {
8021        let mut base_addr: [f32; 4] = [0.; 4];
8022        let vindex = _mm_setr_epi32(1, 2, 3, 0);
8023        let src = _mm_setr_ps(2., 3., 4., 1.);
8024        _mm_mask_i32scatter_ps::<4>(base_addr.as_mut_ptr().cast(), 0b0101, vindex, src);
8025        let expected = [0., 2., 0., 4.];
8026        assert_eq!(expected, base_addr);
8027    }
8028
8029    #[simd_test(enable = "avx512f,avx512vl")]
8030    unsafe fn test_mm_i64scatter_epi32() {
8031        let mut base_addr: [i32; 2] = [0; 2];
8032        let vindex = _mm_setr_epi64x(1, 0);
8033        let src = _mm_setr_epi32(2, 1, -1, -1);
8034        _mm_i64scatter_epi32::<4>(base_addr.as_mut_ptr().cast(), vindex, src);
8035        let expected = [1, 2];
8036        assert_eq!(expected, base_addr);
8037    }
8038
8039    #[simd_test(enable = "avx512f,avx512vl")]
8040    unsafe fn test_mm_mask_i64scatter_epi32() {
8041        let mut base_addr: [i32; 2] = [0; 2];
8042        let vindex = _mm_setr_epi64x(1, 0);
8043        let src = _mm_setr_epi32(2, 1, -1, -1);
8044        _mm_mask_i64scatter_epi32::<4>(base_addr.as_mut_ptr().cast(), 0b01, vindex, src);
8045        let expected = [0, 2];
8046        assert_eq!(expected, base_addr);
8047    }
8048
8049    #[simd_test(enable = "avx512f,avx512vl")]
8050    unsafe fn test_mm_i64scatter_epi64() {
8051        let mut base_addr: [i64; 2] = [0; 2];
8052        let vindex = _mm_setr_epi64x(1, 0);
8053        let src = _mm_setr_epi64x(2, 1);
8054        _mm_i64scatter_epi64::<8>(base_addr.as_mut_ptr().cast(), vindex, src);
8055        let expected = [1, 2];
8056        assert_eq!(expected, base_addr);
8057    }
8058
8059    #[simd_test(enable = "avx512f,avx512vl")]
8060    unsafe fn test_mm_mask_i64scatter_epi64() {
8061        let mut base_addr: [i64; 2] = [0; 2];
8062        let vindex = _mm_setr_epi64x(1, 0);
8063        let src = _mm_setr_epi64x(2, 1);
8064        _mm_mask_i64scatter_epi64::<8>(base_addr.as_mut_ptr().cast(), 0b01, vindex, src);
8065        let expected = [0, 2];
8066        assert_eq!(expected, base_addr);
8067    }
8068
8069    #[simd_test(enable = "avx512f,avx512vl")]
8070    unsafe fn test_mm_i64scatter_pd() {
8071        let mut base_addr: [f64; 2] = [0.; 2];
8072        let vindex = _mm_setr_epi64x(1, 0);
8073        let src = _mm_setr_pd(2., 1.);
8074        _mm_i64scatter_pd::<8>(base_addr.as_mut_ptr().cast(), vindex, src);
8075        let expected = [1., 2.];
8076        assert_eq!(expected, base_addr);
8077    }
8078
8079    #[simd_test(enable = "avx512f,avx512vl")]
8080    unsafe fn test_mm_mask_i64scatter_pd() {
8081        let mut base_addr: [f64; 2] = [0.; 2];
8082        let vindex = _mm_setr_epi64x(1, 0);
8083        let src = _mm_setr_pd(2., 1.);
8084        _mm_mask_i64scatter_pd::<8>(base_addr.as_mut_ptr().cast(), 0b01, vindex, src);
8085        let expected = [0., 2.];
8086        assert_eq!(expected, base_addr);
8087    }
8088
8089    #[simd_test(enable = "avx512f,avx512vl")]
8090    unsafe fn test_mm_i64scatter_ps() {
8091        let mut base_addr: [f32; 2] = [0.; 2];
8092        let vindex = _mm_setr_epi64x(1, 0);
8093        let src = _mm_setr_ps(2., 1., -1., -1.);
8094        _mm_i64scatter_ps::<4>(base_addr.as_mut_ptr().cast(), vindex, src);
8095        let expected = [1., 2.];
8096        assert_eq!(expected, base_addr);
8097    }
8098
8099    #[simd_test(enable = "avx512f,avx512vl")]
8100    unsafe fn test_mm_mask_i64scatter_ps() {
8101        let mut base_addr: [f32; 2] = [0.; 2];
8102        let vindex = _mm_setr_epi64x(1, 0);
8103        let src = _mm_setr_ps(2., 1., -1., -1.);
8104        _mm_mask_i64scatter_ps::<4>(base_addr.as_mut_ptr().cast(), 0b01, vindex, src);
8105        let expected = [0., 2.];
8106        assert_eq!(expected, base_addr);
8107    }
8108
8109    #[simd_test(enable = "avx512f,avx512vl")]
8110    unsafe fn test_mm256_i32scatter_epi32() {
8111        let mut base_addr: [i32; 8] = [0; 8];
8112        let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
8113        let src = _mm256_setr_epi32(2, 3, 4, 5, 6, 7, 8, 1);
8114        _mm256_i32scatter_epi32::<4>(base_addr.as_mut_ptr().cast(), vindex, src);
8115        let expected = [1, 2, 3, 4, 5, 6, 7, 8];
8116        assert_eq!(expected, base_addr);
8117    }
8118
8119    #[simd_test(enable = "avx512f,avx512vl")]
8120    unsafe fn test_mm256_mask_i32scatter_epi32() {
8121        let mut base_addr: [i32; 8] = [0; 8];
8122        let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
8123        let src = _mm256_setr_epi32(2, 3, 4, 5, 6, 7, 8, 1);
8124        _mm256_mask_i32scatter_epi32::<4>(base_addr.as_mut_ptr().cast(), 0b01010101, vindex, src);
8125        let expected = [0, 2, 0, 4, 0, 6, 0, 8];
8126        assert_eq!(expected, base_addr);
8127    }
8128
8129    #[simd_test(enable = "avx512f,avx512vl")]
8130    unsafe fn test_mm256_i32scatter_epi64() {
8131        let mut base_addr: [i64; 4] = [0; 4];
8132        let vindex = _mm_setr_epi32(1, 2, 3, 0);
8133        let src = _mm256_setr_epi64x(2, 3, 4, 1);
8134        _mm256_i32scatter_epi64::<8>(base_addr.as_mut_ptr().cast(), vindex, src);
8135        let expected = [1, 2, 3, 4];
8136        assert_eq!(expected, base_addr);
8137    }
8138
8139    #[simd_test(enable = "avx512f,avx512vl")]
8140    unsafe fn test_mm256_mask_i32scatter_epi64() {
8141        let mut base_addr: [i64; 4] = [0; 4];
8142        let vindex = _mm_setr_epi32(1, 2, 3, 0);
8143        let src = _mm256_setr_epi64x(2, 3, 4, 1);
8144        _mm256_mask_i32scatter_epi64::<8>(base_addr.as_mut_ptr().cast(), 0b0101, vindex, src);
8145        let expected = [0, 2, 0, 4];
8146        assert_eq!(expected, base_addr);
8147    }
8148
8149    #[simd_test(enable = "avx512f,avx512vl")]
8150    unsafe fn test_mm256_i32scatter_pd() {
8151        let mut base_addr: [f64; 4] = [0.; 4];
8152        let vindex = _mm_setr_epi32(1, 2, 3, 0);
8153        let src = _mm256_setr_pd(2., 3., 4., 1.);
8154        _mm256_i32scatter_pd::<8>(base_addr.as_mut_ptr().cast(), vindex, src);
8155        let expected = [1., 2., 3., 4.];
8156        assert_eq!(expected, base_addr);
8157    }
8158
8159    #[simd_test(enable = "avx512f,avx512vl")]
8160    unsafe fn test_mm256_mask_i32scatter_pd() {
8161        let mut base_addr: [f64; 4] = [0.; 4];
8162        let vindex = _mm_setr_epi32(1, 2, 3, 0);
8163        let src = _mm256_setr_pd(2., 3., 4., 1.);
8164        _mm256_mask_i32scatter_pd::<8>(base_addr.as_mut_ptr().cast(), 0b0101, vindex, src);
8165        let expected = [0., 2., 0., 4.];
8166        assert_eq!(expected, base_addr);
8167    }
8168
8169    #[simd_test(enable = "avx512f,avx512vl")]
8170    unsafe fn test_mm256_i32scatter_ps() {
8171        let mut base_addr: [f32; 8] = [0.; 8];
8172        let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
8173        let src = _mm256_setr_ps(2., 3., 4., 5., 6., 7., 8., 1.);
8174        _mm256_i32scatter_ps::<4>(base_addr.as_mut_ptr().cast(), vindex, src);
8175        let expected = [1., 2., 3., 4., 5., 6., 7., 8.];
8176        assert_eq!(expected, base_addr);
8177    }
8178
8179    #[simd_test(enable = "avx512f,avx512vl")]
8180    unsafe fn test_mm256_mask_i32scatter_ps() {
8181        let mut base_addr: [f32; 8] = [0.; 8];
8182        let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
8183        let src = _mm256_setr_ps(2., 3., 4., 5., 6., 7., 8., 1.);
8184        _mm256_mask_i32scatter_ps::<4>(base_addr.as_mut_ptr().cast(), 0b01010101, vindex, src);
8185        let expected = [0., 2., 0., 4., 0., 6., 0., 8.];
8186        assert_eq!(expected, base_addr);
8187    }
8188
8189    #[simd_test(enable = "avx512f,avx512vl")]
8190    unsafe fn test_mm256_i64scatter_epi32() {
8191        let mut base_addr: [i32; 4] = [0; 4];
8192        let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8193        let src = _mm_setr_epi32(2, 3, 4, 1);
8194        _mm256_i64scatter_epi32::<4>(base_addr.as_mut_ptr().cast(), vindex, src);
8195        let expected = [1, 2, 3, 4];
8196        assert_eq!(expected, base_addr);
8197    }
8198
8199    #[simd_test(enable = "avx512f,avx512vl")]
8200    unsafe fn test_mm256_mask_i64scatter_epi32() {
8201        let mut base_addr: [i32; 4] = [0; 4];
8202        let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8203        let src = _mm_setr_epi32(2, 3, 4, 1);
8204        _mm256_mask_i64scatter_epi32::<4>(base_addr.as_mut_ptr().cast(), 0b0101, vindex, src);
8205        let expected = [0, 2, 0, 4];
8206        assert_eq!(expected, base_addr);
8207    }
8208
8209    #[simd_test(enable = "avx512f,avx512vl")]
8210    unsafe fn test_mm256_i64scatter_epi64() {
8211        let mut base_addr: [i64; 4] = [0; 4];
8212        let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8213        let src = _mm256_setr_epi64x(2, 3, 4, 1);
8214        _mm256_i64scatter_epi64::<8>(base_addr.as_mut_ptr().cast(), vindex, src);
8215        let expected = [1, 2, 3, 4];
8216        assert_eq!(expected, base_addr);
8217    }
8218
8219    #[simd_test(enable = "avx512f,avx512vl")]
8220    unsafe fn test_mm256_mask_i64scatter_epi64() {
8221        let mut base_addr: [i64; 4] = [0; 4];
8222        let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8223        let src = _mm256_setr_epi64x(2, 3, 4, 1);
8224        _mm256_mask_i64scatter_epi64::<8>(base_addr.as_mut_ptr().cast(), 0b0101, vindex, src);
8225        let expected = [0, 2, 0, 4];
8226        assert_eq!(expected, base_addr);
8227    }
8228
8229    #[simd_test(enable = "avx512f,avx512vl")]
8230    unsafe fn test_mm256_i64scatter_pd() {
8231        let mut base_addr: [f64; 4] = [0.; 4];
8232        let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8233        let src = _mm256_setr_pd(2., 3., 4., 1.);
8234        _mm256_i64scatter_pd::<8>(base_addr.as_mut_ptr().cast(), vindex, src);
8235        let expected = [1., 2., 3., 4.];
8236        assert_eq!(expected, base_addr);
8237    }
8238
8239    #[simd_test(enable = "avx512f,avx512vl")]
8240    unsafe fn test_mm256_mask_i64scatter_pd() {
8241        let mut base_addr: [f64; 4] = [0.; 4];
8242        let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8243        let src = _mm256_setr_pd(2., 3., 4., 1.);
8244        _mm256_mask_i64scatter_pd::<8>(base_addr.as_mut_ptr().cast(), 0b0101, vindex, src);
8245        let expected = [0., 2., 0., 4.];
8246        assert_eq!(expected, base_addr);
8247    }
8248
8249    #[simd_test(enable = "avx512f,avx512vl")]
8250    unsafe fn test_mm256_i64scatter_ps() {
8251        let mut base_addr: [f32; 4] = [0.; 4];
8252        let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8253        let src = _mm_setr_ps(2., 3., 4., 1.);
8254        _mm256_i64scatter_ps::<4>(base_addr.as_mut_ptr().cast(), vindex, src);
8255        let expected = [1., 2., 3., 4.];
8256        assert_eq!(expected, base_addr);
8257    }
8258
8259    #[simd_test(enable = "avx512f,avx512vl")]
8260    unsafe fn test_mm256_mask_i64scatter_ps() {
8261        let mut base_addr: [f32; 4] = [0.; 4];
8262        let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8263        let src = _mm_setr_ps(2., 3., 4., 1.);
8264        _mm256_mask_i64scatter_ps::<4>(base_addr.as_mut_ptr().cast(), 0b0101, vindex, src);
8265        let expected = [0., 2., 0., 4.];
8266        assert_eq!(expected, base_addr);
8267    }
8268
8269    #[simd_test(enable = "avx512f")]
8270    unsafe fn test_mm512_rol_epi64() {
8271        #[rustfmt::skip]
8272        let a = _mm512_set_epi64(
8273            1 << 63, 1 << 32, 1 << 32, 1 << 32,
8274            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8275        );
8276        let r = _mm512_rol_epi64::<1>(a);
8277        #[rustfmt::skip]
8278        let e = _mm512_set_epi64(
8279            1 << 0, 1 << 33, 1 << 33, 1 << 33,
8280            1 << 33, 1 << 33, 1 << 33, 1 << 33,
8281        );
8282        assert_eq_m512i(r, e);
8283    }
8284
8285    #[simd_test(enable = "avx512f")]
8286    unsafe fn test_mm512_mask_rol_epi64() {
8287        #[rustfmt::skip]
8288        let a = _mm512_set_epi64(
8289            1 << 63, 1 << 32, 1 << 32, 1 << 32,
8290            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8291        );
8292        let r = _mm512_mask_rol_epi64::<1>(a, 0, a);
8293        assert_eq_m512i(r, a);
8294        let r = _mm512_mask_rol_epi64::<1>(a, 0b11111111, a);
8295        #[rustfmt::skip]
8296        let e = _mm512_set_epi64(
8297            1 << 0,  1 << 33, 1 << 33, 1 << 33,
8298            1 << 33, 1 << 33, 1 << 33, 1 << 33,
8299        );
8300        assert_eq_m512i(r, e);
8301    }
8302
8303    #[simd_test(enable = "avx512f")]
8304    unsafe fn test_mm512_maskz_rol_epi64() {
8305        #[rustfmt::skip]
8306        let a = _mm512_set_epi64(
8307            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8308            1 << 32, 1 << 32, 1 << 32, 1 << 63,
8309        );
8310        let r = _mm512_maskz_rol_epi64::<1>(0, a);
8311        assert_eq_m512i(r, _mm512_setzero_si512());
8312        let r = _mm512_maskz_rol_epi64::<1>(0b00001111, a);
8313        let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 33, 1 << 33, 1 << 33, 1 << 0);
8314        assert_eq_m512i(r, e);
8315    }
8316
8317    #[simd_test(enable = "avx512f,avx512vl")]
8318    unsafe fn test_mm256_rol_epi64() {
8319        let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
8320        let r = _mm256_rol_epi64::<1>(a);
8321        let e = _mm256_set_epi64x(1 << 0, 1 << 33, 1 << 33, 1 << 33);
8322        assert_eq_m256i(r, e);
8323    }
8324
8325    #[simd_test(enable = "avx512f,avx512vl")]
8326    unsafe fn test_mm256_mask_rol_epi64() {
8327        let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
8328        let r = _mm256_mask_rol_epi64::<1>(a, 0, a);
8329        assert_eq_m256i(r, a);
8330        let r = _mm256_mask_rol_epi64::<1>(a, 0b00001111, a);
8331        let e = _mm256_set_epi64x(1 << 0, 1 << 33, 1 << 33, 1 << 33);
8332        assert_eq_m256i(r, e);
8333    }
8334
8335    #[simd_test(enable = "avx512f,avx512vl")]
8336    unsafe fn test_mm256_maskz_rol_epi64() {
8337        let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
8338        let r = _mm256_maskz_rol_epi64::<1>(0, a);
8339        assert_eq_m256i(r, _mm256_setzero_si256());
8340        let r = _mm256_maskz_rol_epi64::<1>(0b00001111, a);
8341        let e = _mm256_set_epi64x(1 << 0, 1 << 33, 1 << 33, 1 << 33);
8342        assert_eq_m256i(r, e);
8343    }
8344
8345    #[simd_test(enable = "avx512f,avx512vl")]
8346    unsafe fn test_mm_rol_epi64() {
8347        let a = _mm_set_epi64x(1 << 63, 1 << 32);
8348        let r = _mm_rol_epi64::<1>(a);
8349        let e = _mm_set_epi64x(1 << 0, 1 << 33);
8350        assert_eq_m128i(r, e);
8351    }
8352
8353    #[simd_test(enable = "avx512f,avx512vl")]
8354    unsafe fn test_mm_mask_rol_epi64() {
8355        let a = _mm_set_epi64x(1 << 63, 1 << 32);
8356        let r = _mm_mask_rol_epi64::<1>(a, 0, a);
8357        assert_eq_m128i(r, a);
8358        let r = _mm_mask_rol_epi64::<1>(a, 0b00000011, a);
8359        let e = _mm_set_epi64x(1 << 0, 1 << 33);
8360        assert_eq_m128i(r, e);
8361    }
8362
8363    #[simd_test(enable = "avx512f,avx512vl")]
8364    unsafe fn test_mm_maskz_rol_epi64() {
8365        let a = _mm_set_epi64x(1 << 63, 1 << 32);
8366        let r = _mm_maskz_rol_epi64::<1>(0, a);
8367        assert_eq_m128i(r, _mm_setzero_si128());
8368        let r = _mm_maskz_rol_epi64::<1>(0b00000011, a);
8369        let e = _mm_set_epi64x(1 << 0, 1 << 33);
8370        assert_eq_m128i(r, e);
8371    }
8372
8373    #[simd_test(enable = "avx512f")]
8374    unsafe fn test_mm512_ror_epi64() {
8375        #[rustfmt::skip]
8376        let a = _mm512_set_epi64(
8377            1 << 0,  1 << 32, 1 << 32, 1 << 32,
8378            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8379        );
8380        let r = _mm512_ror_epi64::<1>(a);
8381        #[rustfmt::skip]
8382        let e = _mm512_set_epi64(
8383            1 << 63, 1 << 31, 1 << 31, 1 << 31,
8384            1 << 31, 1 << 31, 1 << 31, 1 << 31,
8385        );
8386        assert_eq_m512i(r, e);
8387    }
8388
8389    #[simd_test(enable = "avx512f")]
8390    unsafe fn test_mm512_mask_ror_epi64() {
8391        #[rustfmt::skip]
8392        let a = _mm512_set_epi64(
8393            1 << 0,  1 << 32, 1 << 32, 1 << 32,
8394            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8395        );
8396        let r = _mm512_mask_ror_epi64::<1>(a, 0, a);
8397        assert_eq_m512i(r, a);
8398        let r = _mm512_mask_ror_epi64::<1>(a, 0b11111111, a);
8399        #[rustfmt::skip]
8400        let e = _mm512_set_epi64(
8401            1 << 63, 1 << 31, 1 << 31, 1 << 31,
8402            1 << 31, 1 << 31, 1 << 31, 1 << 31,
8403        );
8404        assert_eq_m512i(r, e);
8405    }
8406
8407    #[simd_test(enable = "avx512f")]
8408    unsafe fn test_mm512_maskz_ror_epi64() {
8409        #[rustfmt::skip]
8410        let a = _mm512_set_epi64(
8411            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8412            1 << 32, 1 << 32, 1 << 32, 1 << 0,
8413        );
8414        let r = _mm512_maskz_ror_epi64::<1>(0, a);
8415        assert_eq_m512i(r, _mm512_setzero_si512());
8416        let r = _mm512_maskz_ror_epi64::<1>(0b00001111, a);
8417        let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 31, 1 << 31, 1 << 31, 1 << 63);
8418        assert_eq_m512i(r, e);
8419    }
8420
8421    #[simd_test(enable = "avx512f,avx512vl")]
8422    unsafe fn test_mm256_ror_epi64() {
8423        let a = _mm256_set_epi64x(1 << 0, 1 << 32, 1 << 32, 1 << 32);
8424        let r = _mm256_ror_epi64::<1>(a);
8425        let e = _mm256_set_epi64x(1 << 63, 1 << 31, 1 << 31, 1 << 31);
8426        assert_eq_m256i(r, e);
8427    }
8428
8429    #[simd_test(enable = "avx512f,avx512vl")]
8430    unsafe fn test_mm256_mask_ror_epi64() {
8431        let a = _mm256_set_epi64x(1 << 0, 1 << 32, 1 << 32, 1 << 32);
8432        let r = _mm256_mask_ror_epi64::<1>(a, 0, a);
8433        assert_eq_m256i(r, a);
8434        let r = _mm256_mask_ror_epi64::<1>(a, 0b00001111, a);
8435        let e = _mm256_set_epi64x(1 << 63, 1 << 31, 1 << 31, 1 << 31);
8436        assert_eq_m256i(r, e);
8437    }
8438
8439    #[simd_test(enable = "avx512f,avx512vl")]
8440    unsafe fn test_mm256_maskz_ror_epi64() {
8441        let a = _mm256_set_epi64x(1 << 0, 1 << 32, 1 << 32, 1 << 32);
8442        let r = _mm256_maskz_ror_epi64::<1>(0, a);
8443        assert_eq_m256i(r, _mm256_setzero_si256());
8444        let r = _mm256_maskz_ror_epi64::<1>(0b00001111, a);
8445        let e = _mm256_set_epi64x(1 << 63, 1 << 31, 1 << 31, 1 << 31);
8446        assert_eq_m256i(r, e);
8447    }
8448
8449    #[simd_test(enable = "avx512f,avx512vl")]
8450    unsafe fn test_mm_ror_epi64() {
8451        let a = _mm_set_epi64x(1 << 0, 1 << 32);
8452        let r = _mm_ror_epi64::<1>(a);
8453        let e = _mm_set_epi64x(1 << 63, 1 << 31);
8454        assert_eq_m128i(r, e);
8455    }
8456
8457    #[simd_test(enable = "avx512f,avx512vl")]
8458    unsafe fn test_mm_mask_ror_epi64() {
8459        let a = _mm_set_epi64x(1 << 0, 1 << 32);
8460        let r = _mm_mask_ror_epi64::<1>(a, 0, a);
8461        assert_eq_m128i(r, a);
8462        let r = _mm_mask_ror_epi64::<1>(a, 0b00000011, a);
8463        let e = _mm_set_epi64x(1 << 63, 1 << 31);
8464        assert_eq_m128i(r, e);
8465    }
8466
8467    #[simd_test(enable = "avx512f,avx512vl")]
8468    unsafe fn test_mm_maskz_ror_epi64() {
8469        let a = _mm_set_epi64x(1 << 0, 1 << 32);
8470        let r = _mm_maskz_ror_epi64::<1>(0, a);
8471        assert_eq_m128i(r, _mm_setzero_si128());
8472        let r = _mm_maskz_ror_epi64::<1>(0b00000011, a);
8473        let e = _mm_set_epi64x(1 << 63, 1 << 31);
8474        assert_eq_m128i(r, e);
8475    }
8476
8477    #[simd_test(enable = "avx512f")]
8478    unsafe fn test_mm512_slli_epi64() {
8479        #[rustfmt::skip]
8480        let a = _mm512_set_epi64(
8481            1 << 63, 1 << 32, 1 << 32, 1 << 32,
8482            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8483        );
8484        let r = _mm512_slli_epi64::<1>(a);
8485        #[rustfmt::skip]
8486        let e = _mm512_set_epi64(
8487            0, 1 << 33, 1 << 33, 1 << 33,
8488            1 << 33, 1 << 33, 1 << 33, 1 << 33,
8489        );
8490        assert_eq_m512i(r, e);
8491    }
8492
8493    #[simd_test(enable = "avx512f")]
8494    unsafe fn test_mm512_mask_slli_epi64() {
8495        #[rustfmt::skip]
8496        let a = _mm512_set_epi64(
8497            1 << 63, 1 << 32, 1 << 32, 1 << 32,
8498            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8499        );
8500        let r = _mm512_mask_slli_epi64::<1>(a, 0, a);
8501        assert_eq_m512i(r, a);
8502        let r = _mm512_mask_slli_epi64::<1>(a, 0b11111111, a);
8503        #[rustfmt::skip]
8504        let e = _mm512_set_epi64(
8505            0, 1 << 33, 1 << 33, 1 << 33,
8506            1 << 33, 1 << 33, 1 << 33, 1 << 33,
8507        );
8508        assert_eq_m512i(r, e);
8509    }
8510
8511    #[simd_test(enable = "avx512f")]
8512    unsafe fn test_mm512_maskz_slli_epi64() {
8513        #[rustfmt::skip]
8514        let a = _mm512_set_epi64(
8515            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8516            1 << 32, 1 << 32, 1 << 32, 1 << 63,
8517        );
8518        let r = _mm512_maskz_slli_epi64::<1>(0, a);
8519        assert_eq_m512i(r, _mm512_setzero_si512());
8520        let r = _mm512_maskz_slli_epi64::<1>(0b00001111, a);
8521        let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 33, 1 << 33, 1 << 33, 0);
8522        assert_eq_m512i(r, e);
8523    }
8524
8525    #[simd_test(enable = "avx512f,avx512vl")]
8526    unsafe fn test_mm256_mask_slli_epi64() {
8527        let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
8528        let r = _mm256_mask_slli_epi64::<1>(a, 0, a);
8529        assert_eq_m256i(r, a);
8530        let r = _mm256_mask_slli_epi64::<1>(a, 0b00001111, a);
8531        let e = _mm256_set_epi64x(0, 1 << 33, 1 << 33, 1 << 33);
8532        assert_eq_m256i(r, e);
8533    }
8534
8535    #[simd_test(enable = "avx512f,avx512vl")]
8536    unsafe fn test_mm256_maskz_slli_epi64() {
8537        let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
8538        let r = _mm256_maskz_slli_epi64::<1>(0, a);
8539        assert_eq_m256i(r, _mm256_setzero_si256());
8540        let r = _mm256_maskz_slli_epi64::<1>(0b00001111, a);
8541        let e = _mm256_set_epi64x(0, 1 << 33, 1 << 33, 1 << 33);
8542        assert_eq_m256i(r, e);
8543    }
8544
8545    #[simd_test(enable = "avx512f,avx512vl")]
8546    unsafe fn test_mm_mask_slli_epi64() {
8547        let a = _mm_set_epi64x(1 << 63, 1 << 32);
8548        let r = _mm_mask_slli_epi64::<1>(a, 0, a);
8549        assert_eq_m128i(r, a);
8550        let r = _mm_mask_slli_epi64::<1>(a, 0b00000011, a);
8551        let e = _mm_set_epi64x(0, 1 << 33);
8552        assert_eq_m128i(r, e);
8553    }
8554
8555    #[simd_test(enable = "avx512f,avx512vl")]
8556    unsafe fn test_mm_maskz_slli_epi64() {
8557        let a = _mm_set_epi64x(1 << 63, 1 << 32);
8558        let r = _mm_maskz_slli_epi64::<1>(0, a);
8559        assert_eq_m128i(r, _mm_setzero_si128());
8560        let r = _mm_maskz_slli_epi64::<1>(0b00000011, a);
8561        let e = _mm_set_epi64x(0, 1 << 33);
8562        assert_eq_m128i(r, e);
8563    }
8564
8565    #[simd_test(enable = "avx512f")]
8566    unsafe fn test_mm512_srli_epi64() {
8567        #[rustfmt::skip]
8568        let a = _mm512_set_epi64(
8569            1 << 0, 1 << 32, 1 << 32, 1 << 32,
8570            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8571        );
8572        let r = _mm512_srli_epi64::<1>(a);
8573        #[rustfmt::skip]
8574        let e = _mm512_set_epi64(
8575            0, 1 << 31, 1 << 31, 1 << 31,
8576            1 << 31, 1 << 31, 1 << 31, 1 << 31,
8577        );
8578        assert_eq_m512i(r, e);
8579    }
8580
8581    #[simd_test(enable = "avx512f")]
8582    unsafe fn test_mm512_mask_srli_epi64() {
8583        #[rustfmt::skip]
8584        let a = _mm512_set_epi64(
8585            1 << 0, 1 << 32, 1 << 32, 1 << 32,
8586            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8587        );
8588        let r = _mm512_mask_srli_epi64::<1>(a, 0, a);
8589        assert_eq_m512i(r, a);
8590        let r = _mm512_mask_srli_epi64::<1>(a, 0b11111111, a);
8591        #[rustfmt::skip]
8592        let e = _mm512_set_epi64(
8593            0, 1 << 31, 1 << 31, 1 << 31,
8594            1 << 31, 1 << 31, 1 << 31, 1 << 31,
8595        );
8596        assert_eq_m512i(r, e);
8597    }
8598
8599    #[simd_test(enable = "avx512f")]
8600    unsafe fn test_mm512_maskz_srli_epi64() {
8601        #[rustfmt::skip]
8602        let a = _mm512_set_epi64(
8603            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8604            1 << 32, 1 << 32, 1 << 32, 1 << 0,
8605        );
8606        let r = _mm512_maskz_srli_epi64::<1>(0, a);
8607        assert_eq_m512i(r, _mm512_setzero_si512());
8608        let r = _mm512_maskz_srli_epi64::<1>(0b00001111, a);
8609        let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 31, 1 << 31, 1 << 31, 0);
8610        assert_eq_m512i(r, e);
8611    }
8612
8613    #[simd_test(enable = "avx512f,avx512vl")]
8614    unsafe fn test_mm256_mask_srli_epi64() {
8615        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
8616        let r = _mm256_mask_srli_epi64::<1>(a, 0, a);
8617        assert_eq_m256i(r, a);
8618        let r = _mm256_mask_srli_epi64::<1>(a, 0b00001111, a);
8619        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
8620        assert_eq_m256i(r, e);
8621    }
8622
8623    #[simd_test(enable = "avx512f,avx512vl")]
8624    unsafe fn test_mm256_maskz_srli_epi64() {
8625        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
8626        let r = _mm256_maskz_srli_epi64::<1>(0, a);
8627        assert_eq_m256i(r, _mm256_setzero_si256());
8628        let r = _mm256_maskz_srli_epi64::<1>(0b00001111, a);
8629        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
8630        assert_eq_m256i(r, e);
8631    }
8632
8633    #[simd_test(enable = "avx512f,avx512vl")]
8634    unsafe fn test_mm_mask_srli_epi64() {
8635        let a = _mm_set_epi64x(1 << 5, 0);
8636        let r = _mm_mask_srli_epi64::<1>(a, 0, a);
8637        assert_eq_m128i(r, a);
8638        let r = _mm_mask_srli_epi64::<1>(a, 0b00000011, a);
8639        let e = _mm_set_epi64x(1 << 4, 0);
8640        assert_eq_m128i(r, e);
8641    }
8642
8643    #[simd_test(enable = "avx512f,avx512vl")]
8644    unsafe fn test_mm_maskz_srli_epi64() {
8645        let a = _mm_set_epi64x(1 << 5, 0);
8646        let r = _mm_maskz_srli_epi64::<1>(0, a);
8647        assert_eq_m128i(r, _mm_setzero_si128());
8648        let r = _mm_maskz_srli_epi64::<1>(0b00000011, a);
8649        let e = _mm_set_epi64x(1 << 4, 0);
8650        assert_eq_m128i(r, e);
8651    }
8652
8653    #[simd_test(enable = "avx512f")]
8654    unsafe fn test_mm512_rolv_epi64() {
8655        #[rustfmt::skip]
8656        let a = _mm512_set_epi64(
8657            1 << 32, 1 << 63, 1 << 32, 1 << 32,
8658            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8659        );
8660        let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8661        let r = _mm512_rolv_epi64(a, b);
8662        #[rustfmt::skip]
8663        let e = _mm512_set_epi64(
8664            1 << 32, 1 << 0,  1 << 34, 1 << 35,
8665            1 << 36, 1 << 37, 1 << 38, 1 << 39,
8666        );
8667        assert_eq_m512i(r, e);
8668    }
8669
8670    #[simd_test(enable = "avx512f")]
8671    unsafe fn test_mm512_mask_rolv_epi64() {
8672        #[rustfmt::skip]
8673        let a = _mm512_set_epi64(
8674            1 << 32, 1 << 63, 1 << 32, 1 << 32,
8675            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8676        );
8677        let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8678        let r = _mm512_mask_rolv_epi64(a, 0, a, b);
8679        assert_eq_m512i(r, a);
8680        let r = _mm512_mask_rolv_epi64(a, 0b11111111, a, b);
8681        #[rustfmt::skip]
8682        let e = _mm512_set_epi64(
8683            1 << 32, 1 << 0,  1 << 34, 1 << 35,
8684            1 << 36, 1 << 37, 1 << 38, 1 << 39,
8685        );
8686        assert_eq_m512i(r, e);
8687    }
8688
8689    #[simd_test(enable = "avx512f")]
8690    unsafe fn test_mm512_maskz_rolv_epi64() {
8691        #[rustfmt::skip]
8692        let a = _mm512_set_epi64(
8693            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8694            1 << 32, 1 << 32, 1 << 32, 1 << 62,
8695        );
8696        let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 2);
8697        let r = _mm512_maskz_rolv_epi64(0, a, b);
8698        assert_eq_m512i(r, _mm512_setzero_si512());
8699        let r = _mm512_maskz_rolv_epi64(0b00001111, a, b);
8700        let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 36, 1 << 37, 1 << 38, 1 << 0);
8701        assert_eq_m512i(r, e);
8702    }
8703
8704    #[simd_test(enable = "avx512f,avx512vl")]
8705    unsafe fn test_mm256_rolv_epi64() {
8706        let a = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 32, 1 << 32);
8707        let b = _mm256_set_epi64x(0, 1, 2, 3);
8708        let r = _mm256_rolv_epi64(a, b);
8709        let e = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 34, 1 << 35);
8710        assert_eq_m256i(r, e);
8711    }
8712
8713    #[simd_test(enable = "avx512f,avx512vl")]
8714    unsafe fn test_mm256_mask_rolv_epi64() {
8715        let a = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 32, 1 << 32);
8716        let b = _mm256_set_epi64x(0, 1, 2, 3);
8717        let r = _mm256_mask_rolv_epi64(a, 0, a, b);
8718        assert_eq_m256i(r, a);
8719        let r = _mm256_mask_rolv_epi64(a, 0b00001111, a, b);
8720        let e = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 34, 1 << 35);
8721        assert_eq_m256i(r, e);
8722    }
8723
8724    #[simd_test(enable = "avx512f,avx512vl")]
8725    unsafe fn test_mm256_maskz_rolv_epi64() {
8726        let a = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 32, 1 << 32);
8727        let b = _mm256_set_epi64x(0, 1, 2, 3);
8728        let r = _mm256_maskz_rolv_epi64(0, a, b);
8729        assert_eq_m256i(r, _mm256_setzero_si256());
8730        let r = _mm256_maskz_rolv_epi64(0b00001111, a, b);
8731        let e = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 34, 1 << 35);
8732        assert_eq_m256i(r, e);
8733    }
8734
8735    #[simd_test(enable = "avx512f,avx512vl")]
8736    unsafe fn test_mm_rolv_epi64() {
8737        let a = _mm_set_epi64x(1 << 32, 1 << 63);
8738        let b = _mm_set_epi64x(0, 1);
8739        let r = _mm_rolv_epi64(a, b);
8740        let e = _mm_set_epi64x(1 << 32, 1 << 0);
8741        assert_eq_m128i(r, e);
8742    }
8743
8744    #[simd_test(enable = "avx512f,avx512vl")]
8745    unsafe fn test_mm_mask_rolv_epi64() {
8746        let a = _mm_set_epi64x(1 << 32, 1 << 63);
8747        let b = _mm_set_epi64x(0, 1);
8748        let r = _mm_mask_rolv_epi64(a, 0, a, b);
8749        assert_eq_m128i(r, a);
8750        let r = _mm_mask_rolv_epi64(a, 0b00000011, a, b);
8751        let e = _mm_set_epi64x(1 << 32, 1 << 0);
8752        assert_eq_m128i(r, e);
8753    }
8754
8755    #[simd_test(enable = "avx512f,avx512vl")]
8756    unsafe fn test_mm_maskz_rolv_epi64() {
8757        let a = _mm_set_epi64x(1 << 32, 1 << 63);
8758        let b = _mm_set_epi64x(0, 1);
8759        let r = _mm_maskz_rolv_epi64(0, a, b);
8760        assert_eq_m128i(r, _mm_setzero_si128());
8761        let r = _mm_maskz_rolv_epi64(0b00000011, a, b);
8762        let e = _mm_set_epi64x(1 << 32, 1 << 0);
8763        assert_eq_m128i(r, e);
8764    }
8765
8766    #[simd_test(enable = "avx512f")]
8767    unsafe fn test_mm512_rorv_epi64() {
8768        #[rustfmt::skip]
8769        let a = _mm512_set_epi64(
8770            1 << 32, 1 << 0, 1 << 32, 1 << 32,
8771            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8772        );
8773        let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8774        let r = _mm512_rorv_epi64(a, b);
8775        #[rustfmt::skip]
8776        let e = _mm512_set_epi64(
8777            1 << 32, 1 << 63, 1 << 30, 1 << 29,
8778            1 << 28, 1 << 27, 1 << 26, 1 << 25,
8779        );
8780        assert_eq_m512i(r, e);
8781    }
8782
8783    #[simd_test(enable = "avx512f")]
8784    unsafe fn test_mm512_mask_rorv_epi64() {
8785        #[rustfmt::skip]
8786        let a = _mm512_set_epi64(
8787            1 << 32, 1 << 0, 1 << 32, 1 << 32,
8788            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8789        );
8790        let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8791        let r = _mm512_mask_rorv_epi64(a, 0, a, b);
8792        assert_eq_m512i(r, a);
8793        let r = _mm512_mask_rorv_epi64(a, 0b11111111, a, b);
8794        #[rustfmt::skip]
8795        let e = _mm512_set_epi64(
8796            1 << 32, 1 << 63, 1 << 30, 1 << 29,
8797            1 << 28, 1 << 27, 1 << 26, 1 << 25,
8798        );
8799        assert_eq_m512i(r, e);
8800    }
8801
8802    #[simd_test(enable = "avx512f")]
8803    unsafe fn test_mm512_maskz_rorv_epi64() {
8804        #[rustfmt::skip]
8805        let a = _mm512_set_epi64(
8806            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8807            1 << 32, 1 << 32, 1 << 32, 1 << 0,
8808        );
8809        let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 2);
8810        let r = _mm512_maskz_rorv_epi64(0, a, b);
8811        assert_eq_m512i(r, _mm512_setzero_si512());
8812        let r = _mm512_maskz_rorv_epi64(0b00001111, a, b);
8813        let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 28, 1 << 27, 1 << 26, 1 << 62);
8814        assert_eq_m512i(r, e);
8815    }
8816
8817    #[simd_test(enable = "avx512f,avx512vl")]
8818    unsafe fn test_mm256_rorv_epi64() {
8819        let a = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 32, 1 << 32);
8820        let b = _mm256_set_epi64x(0, 1, 2, 3);
8821        let r = _mm256_rorv_epi64(a, b);
8822        let e = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 30, 1 << 29);
8823        assert_eq_m256i(r, e);
8824    }
8825
8826    #[simd_test(enable = "avx512f,avx512vl")]
8827    unsafe fn test_mm256_mask_rorv_epi64() {
8828        let a = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 32, 1 << 32);
8829        let b = _mm256_set_epi64x(0, 1, 2, 3);
8830        let r = _mm256_mask_rorv_epi64(a, 0, a, b);
8831        assert_eq_m256i(r, a);
8832        let r = _mm256_mask_rorv_epi64(a, 0b00001111, a, b);
8833        let e = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 30, 1 << 29);
8834        assert_eq_m256i(r, e);
8835    }
8836
8837    #[simd_test(enable = "avx512f,avx512vl")]
8838    unsafe fn test_mm256_maskz_rorv_epi64() {
8839        let a = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 32, 1 << 32);
8840        let b = _mm256_set_epi64x(0, 1, 2, 3);
8841        let r = _mm256_maskz_rorv_epi64(0, a, b);
8842        assert_eq_m256i(r, _mm256_setzero_si256());
8843        let r = _mm256_maskz_rorv_epi64(0b00001111, a, b);
8844        let e = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 30, 1 << 29);
8845        assert_eq_m256i(r, e);
8846    }
8847
8848    #[simd_test(enable = "avx512f,avx512vl")]
8849    unsafe fn test_mm_rorv_epi64() {
8850        let a = _mm_set_epi64x(1 << 32, 1 << 0);
8851        let b = _mm_set_epi64x(0, 1);
8852        let r = _mm_rorv_epi64(a, b);
8853        let e = _mm_set_epi64x(1 << 32, 1 << 63);
8854        assert_eq_m128i(r, e);
8855    }
8856
8857    #[simd_test(enable = "avx512f,avx512vl")]
8858    unsafe fn test_mm_mask_rorv_epi64() {
8859        let a = _mm_set_epi64x(1 << 32, 1 << 0);
8860        let b = _mm_set_epi64x(0, 1);
8861        let r = _mm_mask_rorv_epi64(a, 0, a, b);
8862        assert_eq_m128i(r, a);
8863        let r = _mm_mask_rorv_epi64(a, 0b00000011, a, b);
8864        let e = _mm_set_epi64x(1 << 32, 1 << 63);
8865        assert_eq_m128i(r, e);
8866    }
8867
8868    #[simd_test(enable = "avx512f,avx512vl")]
8869    unsafe fn test_mm_maskz_rorv_epi64() {
8870        let a = _mm_set_epi64x(1 << 32, 1 << 0);
8871        let b = _mm_set_epi64x(0, 1);
8872        let r = _mm_maskz_rorv_epi64(0, a, b);
8873        assert_eq_m128i(r, _mm_setzero_si128());
8874        let r = _mm_maskz_rorv_epi64(0b00000011, a, b);
8875        let e = _mm_set_epi64x(1 << 32, 1 << 63);
8876        assert_eq_m128i(r, e);
8877    }
8878
8879    #[simd_test(enable = "avx512f")]
8880    unsafe fn test_mm512_sllv_epi64() {
8881        #[rustfmt::skip]
8882        let a = _mm512_set_epi64(
8883            1 << 32, 1 << 63, 1 << 32, 1 << 32,
8884            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8885        );
8886        let count = _mm512_set_epi64(0, 2, 2, 3, 4, 5, 6, 7);
8887        let r = _mm512_sllv_epi64(a, count);
8888        #[rustfmt::skip]
8889        let e = _mm512_set_epi64(
8890            1 << 32, 0, 1 << 34, 1 << 35,
8891            1 << 36, 1 << 37, 1 << 38, 1 << 39,
8892        );
8893        assert_eq_m512i(r, e);
8894    }
8895
8896    #[simd_test(enable = "avx512f")]
8897    unsafe fn test_mm512_mask_sllv_epi64() {
8898        #[rustfmt::skip]
8899        let a = _mm512_set_epi64(
8900            1 << 32, 1 << 32, 1 << 63, 1 << 32,
8901            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8902        );
8903        let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8904        let r = _mm512_mask_sllv_epi64(a, 0, a, count);
8905        assert_eq_m512i(r, a);
8906        let r = _mm512_mask_sllv_epi64(a, 0b11111111, a, count);
8907        #[rustfmt::skip]
8908        let e = _mm512_set_epi64(
8909            1 << 32, 1 << 33, 0, 1 << 35,
8910            1 << 36, 1 << 37, 1 << 38, 1 << 39,
8911        );
8912        assert_eq_m512i(r, e);
8913    }
8914
8915    #[simd_test(enable = "avx512f")]
8916    unsafe fn test_mm512_maskz_sllv_epi64() {
8917        #[rustfmt::skip]
8918        let a = _mm512_set_epi64(
8919            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8920            1 << 32, 1 << 32, 1 << 32, 1 << 63,
8921        );
8922        let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 1);
8923        let r = _mm512_maskz_sllv_epi64(0, a, count);
8924        assert_eq_m512i(r, _mm512_setzero_si512());
8925        let r = _mm512_maskz_sllv_epi64(0b00001111, a, count);
8926        let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 36, 1 << 37, 1 << 38, 0);
8927        assert_eq_m512i(r, e);
8928    }
8929
8930    #[simd_test(enable = "avx512f,avx512vl")]
8931    unsafe fn test_mm256_mask_sllv_epi64() {
8932        let a = _mm256_set_epi64x(1 << 32, 1 << 32, 1 << 63, 1 << 32);
8933        let count = _mm256_set_epi64x(0, 1, 2, 3);
8934        let r = _mm256_mask_sllv_epi64(a, 0, a, count);
8935        assert_eq_m256i(r, a);
8936        let r = _mm256_mask_sllv_epi64(a, 0b00001111, a, count);
8937        let e = _mm256_set_epi64x(1 << 32, 1 << 33, 0, 1 << 35);
8938        assert_eq_m256i(r, e);
8939    }
8940
8941    #[simd_test(enable = "avx512f,avx512vl")]
8942    unsafe fn test_mm256_maskz_sllv_epi64() {
8943        let a = _mm256_set_epi64x(1 << 32, 1 << 32, 1 << 63, 1 << 32);
8944        let count = _mm256_set_epi64x(0, 1, 2, 3);
8945        let r = _mm256_maskz_sllv_epi64(0, a, count);
8946        assert_eq_m256i(r, _mm256_setzero_si256());
8947        let r = _mm256_maskz_sllv_epi64(0b00001111, a, count);
8948        let e = _mm256_set_epi64x(1 << 32, 1 << 33, 0, 1 << 35);
8949        assert_eq_m256i(r, e);
8950    }
8951
8952    #[simd_test(enable = "avx512f,avx512vl")]
8953    unsafe fn test_mm_mask_sllv_epi64() {
8954        let a = _mm_set_epi64x(1 << 63, 1 << 32);
8955        let count = _mm_set_epi64x(2, 3);
8956        let r = _mm_mask_sllv_epi64(a, 0, a, count);
8957        assert_eq_m128i(r, a);
8958        let r = _mm_mask_sllv_epi64(a, 0b00000011, a, count);
8959        let e = _mm_set_epi64x(0, 1 << 35);
8960        assert_eq_m128i(r, e);
8961    }
8962
8963    #[simd_test(enable = "avx512f,avx512vl")]
8964    unsafe fn test_mm_maskz_sllv_epi64() {
8965        let a = _mm_set_epi64x(1 << 63, 1 << 32);
8966        let count = _mm_set_epi64x(2, 3);
8967        let r = _mm_maskz_sllv_epi64(0, a, count);
8968        assert_eq_m128i(r, _mm_setzero_si128());
8969        let r = _mm_maskz_sllv_epi64(0b00000011, a, count);
8970        let e = _mm_set_epi64x(0, 1 << 35);
8971        assert_eq_m128i(r, e);
8972    }
8973
8974    #[simd_test(enable = "avx512f")]
8975    unsafe fn test_mm512_srlv_epi64() {
8976        #[rustfmt::skip]
8977        let a = _mm512_set_epi64(
8978            1 << 32, 1 << 0, 1 << 32, 1 << 32,
8979            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8980        );
8981        let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8982        let r = _mm512_srlv_epi64(a, count);
8983        #[rustfmt::skip]
8984        let e = _mm512_set_epi64(
8985            1 << 32, 0, 1 << 30, 1 << 29,
8986            1 << 28, 1 << 27, 1 << 26, 1 << 25,
8987        );
8988        assert_eq_m512i(r, e);
8989    }
8990
8991    #[simd_test(enable = "avx512f")]
8992    unsafe fn test_mm512_mask_srlv_epi64() {
8993        #[rustfmt::skip]
8994        let a = _mm512_set_epi64(
8995            1 << 32, 1 << 0, 1 << 32, 1 << 32,
8996            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8997        );
8998        let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8999        let r = _mm512_mask_srlv_epi64(a, 0, a, count);
9000        assert_eq_m512i(r, a);
9001        let r = _mm512_mask_srlv_epi64(a, 0b11111111, a, count);
9002        #[rustfmt::skip]
9003        let e = _mm512_set_epi64(
9004            1 << 32, 0, 1 << 30, 1 << 29,
9005            1 << 28, 1 << 27, 1 << 26, 1 << 25,
9006        );
9007        assert_eq_m512i(r, e);
9008    }
9009
9010    #[simd_test(enable = "avx512f")]
9011    unsafe fn test_mm512_maskz_srlv_epi64() {
9012        #[rustfmt::skip]
9013        let a = _mm512_set_epi64(
9014            1 << 32, 1 << 32, 1 << 32, 1 << 32,
9015            1 << 32, 1 << 32, 1 << 32, 1 << 0,
9016        );
9017        let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9018        let r = _mm512_maskz_srlv_epi64(0, a, count);
9019        assert_eq_m512i(r, _mm512_setzero_si512());
9020        let r = _mm512_maskz_srlv_epi64(0b00001111, a, count);
9021        let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 28, 1 << 27, 1 << 26, 0);
9022        assert_eq_m512i(r, e);
9023    }
9024
9025    #[simd_test(enable = "avx512f,avx512vl")]
9026    unsafe fn test_mm256_mask_srlv_epi64() {
9027        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9028        let count = _mm256_set1_epi64x(1);
9029        let r = _mm256_mask_srlv_epi64(a, 0, a, count);
9030        assert_eq_m256i(r, a);
9031        let r = _mm256_mask_srlv_epi64(a, 0b00001111, a, count);
9032        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9033        assert_eq_m256i(r, e);
9034    }
9035
9036    #[simd_test(enable = "avx512f,avx512vl")]
9037    unsafe fn test_mm256_maskz_srlv_epi64() {
9038        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9039        let count = _mm256_set1_epi64x(1);
9040        let r = _mm256_maskz_srlv_epi64(0, a, count);
9041        assert_eq_m256i(r, _mm256_setzero_si256());
9042        let r = _mm256_maskz_srlv_epi64(0b00001111, a, count);
9043        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9044        assert_eq_m256i(r, e);
9045    }
9046
9047    #[simd_test(enable = "avx512f,avx512vl")]
9048    unsafe fn test_mm_mask_srlv_epi64() {
9049        let a = _mm_set_epi64x(1 << 5, 0);
9050        let count = _mm_set1_epi64x(1);
9051        let r = _mm_mask_srlv_epi64(a, 0, a, count);
9052        assert_eq_m128i(r, a);
9053        let r = _mm_mask_srlv_epi64(a, 0b00000011, a, count);
9054        let e = _mm_set_epi64x(1 << 4, 0);
9055        assert_eq_m128i(r, e);
9056    }
9057
9058    #[simd_test(enable = "avx512f,avx512vl")]
9059    unsafe fn test_mm_maskz_srlv_epi64() {
9060        let a = _mm_set_epi64x(1 << 5, 0);
9061        let count = _mm_set1_epi64x(1);
9062        let r = _mm_maskz_srlv_epi64(0, a, count);
9063        assert_eq_m128i(r, _mm_setzero_si128());
9064        let r = _mm_maskz_srlv_epi64(0b00000011, a, count);
9065        let e = _mm_set_epi64x(1 << 4, 0);
9066        assert_eq_m128i(r, e);
9067    }
9068
9069    #[simd_test(enable = "avx512f")]
9070    unsafe fn test_mm512_sll_epi64() {
9071        #[rustfmt::skip]
9072        let a = _mm512_set_epi64(
9073            1 << 63, 1 << 32, 1 << 32, 1 << 32,
9074            1 << 32, 1 << 32, 1 << 32, 1 << 32,
9075        );
9076        let count = _mm_set_epi64x(0, 1);
9077        let r = _mm512_sll_epi64(a, count);
9078        #[rustfmt::skip]
9079        let e = _mm512_set_epi64(
9080            0, 1 << 33, 1 << 33, 1 << 33,
9081            1 << 33, 1 << 33, 1 << 33, 1 << 33,
9082        );
9083        assert_eq_m512i(r, e);
9084        let count = _mm_set_epi64x(1, 0);
9085        let r = _mm512_sll_epi64(a, count);
9086        assert_eq_m512i(r, a);
9087    }
9088
9089    #[simd_test(enable = "avx512f")]
9090    unsafe fn test_mm512_mask_sll_epi64() {
9091        #[rustfmt::skip]
9092        let a = _mm512_set_epi64(
9093            1 << 63, 1 << 32, 1 << 32, 1 << 32,
9094            1 << 32, 1 << 32, 1 << 32, 1 << 32,
9095        );
9096        let count = _mm_set_epi64x(0, 1);
9097        let r = _mm512_mask_sll_epi64(a, 0, a, count);
9098        assert_eq_m512i(r, a);
9099        let r = _mm512_mask_sll_epi64(a, 0b11111111, a, count);
9100        #[rustfmt::skip]
9101        let e = _mm512_set_epi64(
9102            0, 1 << 33, 1 << 33, 1 << 33,
9103            1 << 33, 1 << 33, 1 << 33, 1 << 33,
9104        );
9105        assert_eq_m512i(r, e);
9106    }
9107
9108    #[simd_test(enable = "avx512f")]
9109    unsafe fn test_mm512_maskz_sll_epi64() {
9110        #[rustfmt::skip]
9111        let a = _mm512_set_epi64(
9112            1 << 32, 1 << 32, 1 << 32, 1 << 32,
9113            1 << 32, 1 << 32, 1 << 32, 1 << 63,
9114        );
9115        let count = _mm_set_epi64x(0, 1);
9116        let r = _mm512_maskz_sll_epi64(0, a, count);
9117        assert_eq_m512i(r, _mm512_setzero_si512());
9118        let r = _mm512_maskz_sll_epi64(0b00001111, a, count);
9119        let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 33, 1 << 33, 1 << 33, 0);
9120        assert_eq_m512i(r, e);
9121    }
9122
9123    #[simd_test(enable = "avx512f,avx512vl")]
9124    unsafe fn test_mm256_mask_sll_epi64() {
9125        let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
9126        let count = _mm_set_epi64x(0, 1);
9127        let r = _mm256_mask_sll_epi64(a, 0, a, count);
9128        assert_eq_m256i(r, a);
9129        let r = _mm256_mask_sll_epi64(a, 0b00001111, a, count);
9130        let e = _mm256_set_epi64x(0, 1 << 33, 1 << 33, 1 << 33);
9131        assert_eq_m256i(r, e);
9132    }
9133
9134    #[simd_test(enable = "avx512f,avx512vl")]
9135    unsafe fn test_mm256_maskz_sll_epi64() {
9136        let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
9137        let count = _mm_set_epi64x(0, 1);
9138        let r = _mm256_maskz_sll_epi64(0, a, count);
9139        assert_eq_m256i(r, _mm256_setzero_si256());
9140        let r = _mm256_maskz_sll_epi64(0b00001111, a, count);
9141        let e = _mm256_set_epi64x(0, 1 << 33, 1 << 33, 1 << 33);
9142        assert_eq_m256i(r, e);
9143    }
9144
9145    #[simd_test(enable = "avx512f,avx512vl")]
9146    unsafe fn test_mm_mask_sll_epi64() {
9147        let a = _mm_set_epi64x(1 << 63, 1 << 32);
9148        let count = _mm_set_epi64x(0, 1);
9149        let r = _mm_mask_sll_epi64(a, 0, a, count);
9150        assert_eq_m128i(r, a);
9151        let r = _mm_mask_sll_epi64(a, 0b00000011, a, count);
9152        let e = _mm_set_epi64x(0, 1 << 33);
9153        assert_eq_m128i(r, e);
9154    }
9155
9156    #[simd_test(enable = "avx512f,avx512vl")]
9157    unsafe fn test_mm_maskz_sll_epi64() {
9158        let a = _mm_set_epi64x(1 << 63, 1 << 32);
9159        let count = _mm_set_epi64x(0, 1);
9160        let r = _mm_maskz_sll_epi64(0, a, count);
9161        assert_eq_m128i(r, _mm_setzero_si128());
9162        let r = _mm_maskz_sll_epi64(0b00000011, a, count);
9163        let e = _mm_set_epi64x(0, 1 << 33);
9164        assert_eq_m128i(r, e);
9165    }
9166
9167    #[simd_test(enable = "avx512f")]
9168    unsafe fn test_mm512_srl_epi64() {
9169        #[rustfmt::skip]
9170        let a = _mm512_set_epi64(
9171            1 << 0, 1 << 32, 1 << 32, 1 << 32,
9172            1 << 32, 1 << 32, 1 << 32, 1 << 32,
9173        );
9174        let count = _mm_set_epi64x(0, 1);
9175        let r = _mm512_srl_epi64(a, count);
9176        #[rustfmt::skip]
9177        let e = _mm512_set_epi64(
9178            0, 1 << 31, 1 << 31, 1 << 31,
9179            1 << 31, 1 << 31, 1 << 31, 1 << 31,
9180        );
9181        assert_eq_m512i(r, e);
9182    }
9183
9184    #[simd_test(enable = "avx512f")]
9185    unsafe fn test_mm512_mask_srl_epi64() {
9186        #[rustfmt::skip]
9187        let a = _mm512_set_epi64(
9188            1 << 0, 1 << 32, 1 << 32, 1 << 32,
9189            1 << 32, 1 << 32, 1 << 32, 1 << 32,
9190        );
9191        let count = _mm_set_epi64x(0, 1);
9192        let r = _mm512_mask_srl_epi64(a, 0, a, count);
9193        assert_eq_m512i(r, a);
9194        let r = _mm512_mask_srl_epi64(a, 0b11111111, a, count);
9195        #[rustfmt::skip]
9196        let e = _mm512_set_epi64(
9197            0, 1 << 31, 1 << 31, 1 << 31,
9198            1 << 31, 1 << 31, 1 << 31, 1 << 31,
9199        );
9200        assert_eq_m512i(r, e);
9201    }
9202
9203    #[simd_test(enable = "avx512f")]
9204    unsafe fn test_mm512_maskz_srl_epi64() {
9205        #[rustfmt::skip]
9206        let a = _mm512_set_epi64(
9207            1 << 32, 1 << 32, 1 << 32, 1 << 32,
9208            1 << 32, 1 << 32, 1 << 32, 1 << 0,
9209        );
9210        let count = _mm_set_epi64x(0, 1);
9211        let r = _mm512_maskz_srl_epi64(0, a, count);
9212        assert_eq_m512i(r, _mm512_setzero_si512());
9213        let r = _mm512_maskz_srl_epi64(0b00001111, a, count);
9214        let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 31, 1 << 31, 1 << 31, 0);
9215        assert_eq_m512i(r, e);
9216    }
9217
9218    #[simd_test(enable = "avx512f,avx512vl")]
9219    unsafe fn test_mm256_mask_srl_epi64() {
9220        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9221        let count = _mm_set_epi64x(0, 1);
9222        let r = _mm256_mask_srl_epi64(a, 0, a, count);
9223        assert_eq_m256i(r, a);
9224        let r = _mm256_mask_srl_epi64(a, 0b00001111, a, count);
9225        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9226        assert_eq_m256i(r, e);
9227    }
9228
9229    #[simd_test(enable = "avx512f,avx512vl")]
9230    unsafe fn test_mm256_maskz_srl_epi64() {
9231        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9232        let count = _mm_set_epi64x(0, 1);
9233        let r = _mm256_maskz_srl_epi64(0, a, count);
9234        assert_eq_m256i(r, _mm256_setzero_si256());
9235        let r = _mm256_maskz_srl_epi64(0b00001111, a, count);
9236        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9237        assert_eq_m256i(r, e);
9238    }
9239
9240    #[simd_test(enable = "avx512f,avx512vl")]
9241    unsafe fn test_mm_mask_srl_epi64() {
9242        let a = _mm_set_epi64x(1 << 5, 0);
9243        let count = _mm_set_epi64x(0, 1);
9244        let r = _mm_mask_srl_epi64(a, 0, a, count);
9245        assert_eq_m128i(r, a);
9246        let r = _mm_mask_srl_epi64(a, 0b00000011, a, count);
9247        let e = _mm_set_epi64x(1 << 4, 0);
9248        assert_eq_m128i(r, e);
9249    }
9250
9251    #[simd_test(enable = "avx512f,avx512vl")]
9252    unsafe fn test_mm_maskz_srl_epi64() {
9253        let a = _mm_set_epi64x(1 << 5, 0);
9254        let count = _mm_set_epi64x(0, 1);
9255        let r = _mm_maskz_srl_epi64(0, a, count);
9256        assert_eq_m128i(r, _mm_setzero_si128());
9257        let r = _mm_maskz_srl_epi64(0b00000011, a, count);
9258        let e = _mm_set_epi64x(1 << 4, 0);
9259        assert_eq_m128i(r, e);
9260    }
9261
9262    #[simd_test(enable = "avx512f")]
9263    unsafe fn test_mm512_sra_epi64() {
9264        let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
9265        let count = _mm_set_epi64x(0, 2);
9266        let r = _mm512_sra_epi64(a, count);
9267        let e = _mm512_set_epi64(0, -2, 0, 0, 0, 0, 3, -4);
9268        assert_eq_m512i(r, e);
9269    }
9270
9271    #[simd_test(enable = "avx512f")]
9272    unsafe fn test_mm512_mask_sra_epi64() {
9273        let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
9274        let count = _mm_set_epi64x(0, 2);
9275        let r = _mm512_mask_sra_epi64(a, 0, a, count);
9276        assert_eq_m512i(r, a);
9277        let r = _mm512_mask_sra_epi64(a, 0b11111111, a, count);
9278        let e = _mm512_set_epi64(0, -2, 0, 0, 0, 0, 3, -4);
9279        assert_eq_m512i(r, e);
9280    }
9281
9282    #[simd_test(enable = "avx512f")]
9283    unsafe fn test_mm512_maskz_sra_epi64() {
9284        let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
9285        let count = _mm_set_epi64x(0, 2);
9286        let r = _mm512_maskz_sra_epi64(0, a, count);
9287        assert_eq_m512i(r, _mm512_setzero_si512());
9288        let r = _mm512_maskz_sra_epi64(0b00001111, a, count);
9289        let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 3, -4);
9290        assert_eq_m512i(r, e);
9291    }
9292
9293    #[simd_test(enable = "avx512f,avx512vl")]
9294    unsafe fn test_mm256_sra_epi64() {
9295        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9296        let count = _mm_set_epi64x(0, 1);
9297        let r = _mm256_sra_epi64(a, count);
9298        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9299        assert_eq_m256i(r, e);
9300    }
9301
9302    #[simd_test(enable = "avx512f,avx512vl")]
9303    unsafe fn test_mm256_mask_sra_epi64() {
9304        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9305        let count = _mm_set_epi64x(0, 1);
9306        let r = _mm256_mask_sra_epi64(a, 0, a, count);
9307        assert_eq_m256i(r, a);
9308        let r = _mm256_mask_sra_epi64(a, 0b00001111, a, count);
9309        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9310        assert_eq_m256i(r, e);
9311    }
9312
9313    #[simd_test(enable = "avx512f,avx512vl")]
9314    unsafe fn test_mm256_maskz_sra_epi64() {
9315        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9316        let count = _mm_set_epi64x(0, 1);
9317        let r = _mm256_maskz_sra_epi64(0, a, count);
9318        assert_eq_m256i(r, _mm256_setzero_si256());
9319        let r = _mm256_maskz_sra_epi64(0b00001111, a, count);
9320        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9321        assert_eq_m256i(r, e);
9322    }
9323
9324    #[simd_test(enable = "avx512f,avx512vl")]
9325    unsafe fn test_mm_sra_epi64() {
9326        let a = _mm_set_epi64x(1 << 5, 0);
9327        let count = _mm_set_epi64x(0, 1);
9328        let r = _mm_sra_epi64(a, count);
9329        let e = _mm_set_epi64x(1 << 4, 0);
9330        assert_eq_m128i(r, e);
9331    }
9332
9333    #[simd_test(enable = "avx512f,avx512vl")]
9334    unsafe fn test_mm_mask_sra_epi64() {
9335        let a = _mm_set_epi64x(1 << 5, 0);
9336        let count = _mm_set_epi64x(0, 1);
9337        let r = _mm_mask_sra_epi64(a, 0, a, count);
9338        assert_eq_m128i(r, a);
9339        let r = _mm_mask_sra_epi64(a, 0b00000011, a, count);
9340        let e = _mm_set_epi64x(1 << 4, 0);
9341        assert_eq_m128i(r, e);
9342    }
9343
9344    #[simd_test(enable = "avx512f,avx512vl")]
9345    unsafe fn test_mm_maskz_sra_epi64() {
9346        let a = _mm_set_epi64x(1 << 5, 0);
9347        let count = _mm_set_epi64x(0, 1);
9348        let r = _mm_maskz_sra_epi64(0, a, count);
9349        assert_eq_m128i(r, _mm_setzero_si128());
9350        let r = _mm_maskz_sra_epi64(0b00000011, a, count);
9351        let e = _mm_set_epi64x(1 << 4, 0);
9352        assert_eq_m128i(r, e);
9353    }
9354
9355    #[simd_test(enable = "avx512f")]
9356    unsafe fn test_mm512_srav_epi64() {
9357        let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
9358        let count = _mm512_set_epi64(2, 2, 0, 0, 0, 0, 2, 1);
9359        let r = _mm512_srav_epi64(a, count);
9360        let e = _mm512_set_epi64(0, -2, 0, 0, 0, 0, 3, -8);
9361        assert_eq_m512i(r, e);
9362    }
9363
9364    #[simd_test(enable = "avx512f")]
9365    unsafe fn test_mm512_mask_srav_epi64() {
9366        let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
9367        let count = _mm512_set_epi64(2, 2, 0, 0, 0, 0, 2, 1);
9368        let r = _mm512_mask_srav_epi64(a, 0, a, count);
9369        assert_eq_m512i(r, a);
9370        let r = _mm512_mask_srav_epi64(a, 0b11111111, a, count);
9371        let e = _mm512_set_epi64(0, -2, 0, 0, 0, 0, 3, -8);
9372        assert_eq_m512i(r, e);
9373    }
9374
9375    #[simd_test(enable = "avx512f")]
9376    unsafe fn test_mm512_maskz_srav_epi64() {
9377        let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
9378        let count = _mm512_set_epi64(2, 2, 0, 0, 0, 0, 2, 1);
9379        let r = _mm512_maskz_srav_epi64(0, a, count);
9380        assert_eq_m512i(r, _mm512_setzero_si512());
9381        let r = _mm512_maskz_srav_epi64(0b00001111, a, count);
9382        let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 3, -8);
9383        assert_eq_m512i(r, e);
9384    }
9385
9386    #[simd_test(enable = "avx512f,avx512vl")]
9387    unsafe fn test_mm256_srav_epi64() {
9388        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9389        let count = _mm256_set1_epi64x(1);
9390        let r = _mm256_srav_epi64(a, count);
9391        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9392        assert_eq_m256i(r, e);
9393    }
9394
9395    #[simd_test(enable = "avx512f,avx512vl")]
9396    unsafe fn test_mm256_mask_srav_epi64() {
9397        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9398        let count = _mm256_set1_epi64x(1);
9399        let r = _mm256_mask_srav_epi64(a, 0, a, count);
9400        assert_eq_m256i(r, a);
9401        let r = _mm256_mask_srav_epi64(a, 0b00001111, a, count);
9402        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9403        assert_eq_m256i(r, e);
9404    }
9405
9406    #[simd_test(enable = "avx512f,avx512vl")]
9407    unsafe fn test_mm256_maskz_srav_epi64() {
9408        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9409        let count = _mm256_set1_epi64x(1);
9410        let r = _mm256_maskz_srav_epi64(0, a, count);
9411        assert_eq_m256i(r, _mm256_setzero_si256());
9412        let r = _mm256_maskz_srav_epi64(0b00001111, a, count);
9413        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9414        assert_eq_m256i(r, e);
9415    }
9416
9417    #[simd_test(enable = "avx512f,avx512vl")]
9418    unsafe fn test_mm_srav_epi64() {
9419        let a = _mm_set_epi64x(1 << 5, 0);
9420        let count = _mm_set1_epi64x(1);
9421        let r = _mm_srav_epi64(a, count);
9422        let e = _mm_set_epi64x(1 << 4, 0);
9423        assert_eq_m128i(r, e);
9424    }
9425
9426    #[simd_test(enable = "avx512f,avx512vl")]
9427    unsafe fn test_mm_mask_srav_epi64() {
9428        let a = _mm_set_epi64x(1 << 5, 0);
9429        let count = _mm_set1_epi64x(1);
9430        let r = _mm_mask_srav_epi64(a, 0, a, count);
9431        assert_eq_m128i(r, a);
9432        let r = _mm_mask_srav_epi64(a, 0b00000011, a, count);
9433        let e = _mm_set_epi64x(1 << 4, 0);
9434        assert_eq_m128i(r, e);
9435    }
9436
9437    #[simd_test(enable = "avx512f,avx512vl")]
9438    unsafe fn test_mm_maskz_srav_epi64() {
9439        let a = _mm_set_epi64x(1 << 5, 0);
9440        let count = _mm_set1_epi64x(1);
9441        let r = _mm_maskz_srav_epi64(0, a, count);
9442        assert_eq_m128i(r, _mm_setzero_si128());
9443        let r = _mm_maskz_srav_epi64(0b00000011, a, count);
9444        let e = _mm_set_epi64x(1 << 4, 0);
9445        assert_eq_m128i(r, e);
9446    }
9447
9448    #[simd_test(enable = "avx512f")]
9449    unsafe fn test_mm512_srai_epi64() {
9450        let a = _mm512_set_epi64(1, -4, 15, 0, 0, 0, 0, -16);
9451        let r = _mm512_srai_epi64::<2>(a);
9452        let e = _mm512_set_epi64(0, -1, 3, 0, 0, 0, 0, -4);
9453        assert_eq_m512i(r, e);
9454    }
9455
9456    #[simd_test(enable = "avx512f")]
9457    unsafe fn test_mm512_mask_srai_epi64() {
9458        let a = _mm512_set_epi64(1, -4, 15, 0, 0, 0, 0, -16);
9459        let r = _mm512_mask_srai_epi64::<2>(a, 0, a);
9460        assert_eq_m512i(r, a);
9461        let r = _mm512_mask_srai_epi64::<2>(a, 0b11111111, a);
9462        let e = _mm512_set_epi64(0, -1, 3, 0, 0, 0, 0, -4);
9463        assert_eq_m512i(r, e);
9464    }
9465
9466    #[simd_test(enable = "avx512f")]
9467    unsafe fn test_mm512_maskz_srai_epi64() {
9468        let a = _mm512_set_epi64(1, -4, 15, 0, 0, 0, 0, -16);
9469        let r = _mm512_maskz_srai_epi64::<2>(0, a);
9470        assert_eq_m512i(r, _mm512_setzero_si512());
9471        let r = _mm512_maskz_srai_epi64::<2>(0b00001111, a);
9472        let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, -4);
9473        assert_eq_m512i(r, e);
9474    }
9475
9476    #[simd_test(enable = "avx512f,avx512vl")]
9477    unsafe fn test_mm256_srai_epi64() {
9478        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9479        let r = _mm256_srai_epi64::<1>(a);
9480        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9481        assert_eq_m256i(r, e);
9482    }
9483
9484    #[simd_test(enable = "avx512f,avx512vl")]
9485    unsafe fn test_mm256_mask_srai_epi64() {
9486        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9487        let r = _mm256_mask_srai_epi64::<1>(a, 0, a);
9488        assert_eq_m256i(r, a);
9489        let r = _mm256_mask_srai_epi64::<1>(a, 0b00001111, a);
9490        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9491        assert_eq_m256i(r, e);
9492    }
9493
9494    #[simd_test(enable = "avx512f,avx512vl")]
9495    unsafe fn test_mm256_maskz_srai_epi64() {
9496        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9497        let r = _mm256_maskz_srai_epi64::<1>(0, a);
9498        assert_eq_m256i(r, _mm256_setzero_si256());
9499        let r = _mm256_maskz_srai_epi64::<1>(0b00001111, a);
9500        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9501        assert_eq_m256i(r, e);
9502    }
9503
9504    #[simd_test(enable = "avx512f,avx512vl")]
9505    unsafe fn test_mm_srai_epi64() {
9506        let a = _mm_set_epi64x(1 << 5, 0);
9507        let r = _mm_srai_epi64::<1>(a);
9508        let e = _mm_set_epi64x(1 << 4, 0);
9509        assert_eq_m128i(r, e);
9510    }
9511
9512    #[simd_test(enable = "avx512f,avx512vl")]
9513    unsafe fn test_mm_mask_srai_epi64() {
9514        let a = _mm_set_epi64x(1 << 5, 0);
9515        let r = _mm_mask_srai_epi64::<1>(a, 0, a);
9516        assert_eq_m128i(r, a);
9517        let r = _mm_mask_srai_epi64::<1>(a, 0b00000011, a);
9518        let e = _mm_set_epi64x(1 << 4, 0);
9519        assert_eq_m128i(r, e);
9520    }
9521
9522    #[simd_test(enable = "avx512f,avx512vl")]
9523    unsafe fn test_mm_maskz_srai_epi64() {
9524        let a = _mm_set_epi64x(1 << 5, 0);
9525        let r = _mm_maskz_srai_epi64::<1>(0, a);
9526        assert_eq_m128i(r, _mm_setzero_si128());
9527        let r = _mm_maskz_srai_epi64::<1>(0b00000011, a);
9528        let e = _mm_set_epi64x(1 << 4, 0);
9529        assert_eq_m128i(r, e);
9530    }
9531
9532    #[simd_test(enable = "avx512f")]
9533    unsafe fn test_mm512_permute_pd() {
9534        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9535        let r = _mm512_permute_pd::<0b11_11_11_11>(a);
9536        let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
9537        assert_eq_m512d(r, e);
9538    }
9539
9540    #[simd_test(enable = "avx512f")]
9541    unsafe fn test_mm512_mask_permute_pd() {
9542        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9543        let r = _mm512_mask_permute_pd::<0b11_11_11_11>(a, 0, a);
9544        assert_eq_m512d(r, a);
9545        let r = _mm512_mask_permute_pd::<0b11_11_11_11>(a, 0b11111111, a);
9546        let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
9547        assert_eq_m512d(r, e);
9548    }
9549
9550    #[simd_test(enable = "avx512f")]
9551    unsafe fn test_mm512_maskz_permute_pd() {
9552        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9553        let r = _mm512_maskz_permute_pd::<0b11_11_11_11>(0, a);
9554        assert_eq_m512d(r, _mm512_setzero_pd());
9555        let r = _mm512_maskz_permute_pd::<0b11_11_11_11>(0b11111111, a);
9556        let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
9557        assert_eq_m512d(r, e);
9558    }
9559
9560    #[simd_test(enable = "avx512f,avx512vl")]
9561    unsafe fn test_mm256_mask_permute_pd() {
9562        let a = _mm256_set_pd(3., 2., 1., 0.);
9563        let r = _mm256_mask_permute_pd::<0b11_11>(a, 0, a);
9564        assert_eq_m256d(r, a);
9565        let r = _mm256_mask_permute_pd::<0b11_11>(a, 0b00001111, a);
9566        let e = _mm256_set_pd(3., 3., 1., 1.);
9567        assert_eq_m256d(r, e);
9568    }
9569
9570    #[simd_test(enable = "avx512f,avx512vl")]
9571    unsafe fn test_mm256_maskz_permute_pd() {
9572        let a = _mm256_set_pd(3., 2., 1., 0.);
9573        let r = _mm256_maskz_permute_pd::<0b11_11>(0, a);
9574        assert_eq_m256d(r, _mm256_setzero_pd());
9575        let r = _mm256_maskz_permute_pd::<0b11_11>(0b00001111, a);
9576        let e = _mm256_set_pd(3., 3., 1., 1.);
9577        assert_eq_m256d(r, e);
9578    }
9579
9580    #[simd_test(enable = "avx512f,avx512vl")]
9581    unsafe fn test_mm_mask_permute_pd() {
9582        let a = _mm_set_pd(1., 0.);
9583        let r = _mm_mask_permute_pd::<0b11>(a, 0, a);
9584        assert_eq_m128d(r, a);
9585        let r = _mm_mask_permute_pd::<0b11>(a, 0b00000011, a);
9586        let e = _mm_set_pd(1., 1.);
9587        assert_eq_m128d(r, e);
9588    }
9589
9590    #[simd_test(enable = "avx512f,avx512vl")]
9591    unsafe fn test_mm_maskz_permute_pd() {
9592        let a = _mm_set_pd(1., 0.);
9593        let r = _mm_maskz_permute_pd::<0b11>(0, a);
9594        assert_eq_m128d(r, _mm_setzero_pd());
9595        let r = _mm_maskz_permute_pd::<0b11>(0b00000011, a);
9596        let e = _mm_set_pd(1., 1.);
9597        assert_eq_m128d(r, e);
9598    }
9599
9600    #[simd_test(enable = "avx512f")]
9601    unsafe fn test_mm512_permutex_epi64() {
9602        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9603        let r = _mm512_permutex_epi64::<0b11_11_11_11>(a);
9604        let e = _mm512_setr_epi64(3, 3, 3, 3, 7, 7, 7, 7);
9605        assert_eq_m512i(r, e);
9606    }
9607
9608    #[simd_test(enable = "avx512f")]
9609    unsafe fn test_mm512_mask_permutex_epi64() {
9610        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9611        let r = _mm512_mask_permutex_epi64::<0b11_11_11_11>(a, 0, a);
9612        assert_eq_m512i(r, a);
9613        let r = _mm512_mask_permutex_epi64::<0b11_11_11_11>(a, 0b11111111, a);
9614        let e = _mm512_setr_epi64(3, 3, 3, 3, 7, 7, 7, 7);
9615        assert_eq_m512i(r, e);
9616    }
9617
9618    #[simd_test(enable = "avx512f")]
9619    unsafe fn test_mm512_maskz_permutex_epi64() {
9620        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9621        let r = _mm512_maskz_permutex_epi64::<0b11_11_11_11>(0, a);
9622        assert_eq_m512i(r, _mm512_setzero_si512());
9623        let r = _mm512_maskz_permutex_epi64::<0b11_11_11_11>(0b11111111, a);
9624        let e = _mm512_setr_epi64(3, 3, 3, 3, 7, 7, 7, 7);
9625        assert_eq_m512i(r, e);
9626    }
9627
9628    #[simd_test(enable = "avx512f,avx512vl")]
9629    unsafe fn test_mm256_permutex_epi64() {
9630        let a = _mm256_set_epi64x(3, 2, 1, 0);
9631        let r = _mm256_permutex_epi64::<0b11_11_11_11>(a);
9632        let e = _mm256_set_epi64x(3, 3, 3, 3);
9633        assert_eq_m256i(r, e);
9634    }
9635
9636    #[simd_test(enable = "avx512f,avx512vl")]
9637    unsafe fn test_mm256_mask_permutex_epi64() {
9638        let a = _mm256_set_epi64x(3, 2, 1, 0);
9639        let r = _mm256_mask_permutex_epi64::<0b11_11_11_11>(a, 0, a);
9640        assert_eq_m256i(r, a);
9641        let r = _mm256_mask_permutex_epi64::<0b11_11_11_11>(a, 0b00001111, a);
9642        let e = _mm256_set_epi64x(3, 3, 3, 3);
9643        assert_eq_m256i(r, e);
9644    }
9645
9646    #[simd_test(enable = "avx512f")]
9647    unsafe fn test_mm256_maskz_permutex_epi64() {
9648        let a = _mm256_set_epi64x(3, 2, 1, 0);
9649        let r = _mm256_maskz_permutex_epi64::<0b11_11_11_11>(0, a);
9650        assert_eq_m256i(r, _mm256_setzero_si256());
9651        let r = _mm256_maskz_permutex_epi64::<0b11_11_11_11>(0b00001111, a);
9652        let e = _mm256_set_epi64x(3, 3, 3, 3);
9653        assert_eq_m256i(r, e);
9654    }
9655
9656    #[simd_test(enable = "avx512f")]
9657    unsafe fn test_mm512_permutex_pd() {
9658        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9659        let r = _mm512_permutex_pd::<0b11_11_11_11>(a);
9660        let e = _mm512_setr_pd(3., 3., 3., 3., 7., 7., 7., 7.);
9661        assert_eq_m512d(r, e);
9662    }
9663
9664    #[simd_test(enable = "avx512f")]
9665    unsafe fn test_mm512_mask_permutex_pd() {
9666        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9667        let r = _mm512_mask_permutex_pd::<0b11_11_11_11>(a, 0, a);
9668        assert_eq_m512d(r, a);
9669        let r = _mm512_mask_permutex_pd::<0b11_11_11_11>(a, 0b11111111, a);
9670        let e = _mm512_setr_pd(3., 3., 3., 3., 7., 7., 7., 7.);
9671        assert_eq_m512d(r, e);
9672    }
9673
9674    #[simd_test(enable = "avx512f")]
9675    unsafe fn test_mm512_maskz_permutex_pd() {
9676        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9677        let r = _mm512_maskz_permutex_pd::<0b11_11_11_11>(0, a);
9678        assert_eq_m512d(r, _mm512_setzero_pd());
9679        let r = _mm512_maskz_permutex_pd::<0b11_11_11_11>(0b11111111, a);
9680        let e = _mm512_setr_pd(3., 3., 3., 3., 7., 7., 7., 7.);
9681        assert_eq_m512d(r, e);
9682    }
9683
9684    #[simd_test(enable = "avx512f,avx512vl")]
9685    unsafe fn test_mm256_permutex_pd() {
9686        let a = _mm256_set_pd(0., 1., 2., 3.);
9687        let r = _mm256_permutex_pd::<0b11_11_11_11>(a);
9688        let e = _mm256_set_pd(0., 0., 0., 0.);
9689        assert_eq_m256d(r, e);
9690    }
9691
9692    #[simd_test(enable = "avx512f,avx512vl")]
9693    unsafe fn test_mm256_mask_permutex_pd() {
9694        let a = _mm256_set_pd(0., 1., 2., 3.);
9695        let r = _mm256_mask_permutex_pd::<0b11_11_11_11>(a, 0, a);
9696        assert_eq_m256d(r, a);
9697        let r = _mm256_mask_permutex_pd::<0b11_11_11_11>(a, 0b00001111, a);
9698        let e = _mm256_set_pd(0., 0., 0., 0.);
9699        assert_eq_m256d(r, e);
9700    }
9701
9702    #[simd_test(enable = "avx512f,avx512vl")]
9703    unsafe fn test_mm256_maskz_permutex_pd() {
9704        let a = _mm256_set_pd(0., 1., 2., 3.);
9705        let r = _mm256_maskz_permutex_pd::<0b11_11_11_11>(0, a);
9706        assert_eq_m256d(r, _mm256_setzero_pd());
9707        let r = _mm256_maskz_permutex_pd::<0b11_11_11_11>(0b00001111, a);
9708        let e = _mm256_set_pd(0., 0., 0., 0.);
9709        assert_eq_m256d(r, e);
9710    }
9711
9712    #[simd_test(enable = "avx512f")]
9713    unsafe fn test_mm512_permutevar_pd() {
9714        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9715        let b = _mm512_set1_epi64(0b1);
9716        let r = _mm512_permutevar_pd(a, b);
9717        let e = _mm512_set_pd(1., 1., 3., 3., 5., 5., 7., 7.);
9718        assert_eq_m512d(r, e);
9719    }
9720
9721    #[simd_test(enable = "avx512f")]
9722    unsafe fn test_mm512_mask_permutevar_pd() {
9723        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9724        let b = _mm512_set1_epi64(0b1);
9725        let r = _mm512_mask_permutevar_pd(a, 0, a, b);
9726        assert_eq_m512d(r, a);
9727        let r = _mm512_mask_permutevar_pd(a, 0b11111111, a, b);
9728        let e = _mm512_set_pd(1., 1., 3., 3., 5., 5., 7., 7.);
9729        assert_eq_m512d(r, e);
9730    }
9731
9732    #[simd_test(enable = "avx512f")]
9733    unsafe fn test_mm512_maskz_permutevar_pd() {
9734        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9735        let b = _mm512_set1_epi64(0b1);
9736        let r = _mm512_maskz_permutevar_pd(0, a, b);
9737        assert_eq_m512d(r, _mm512_setzero_pd());
9738        let r = _mm512_maskz_permutevar_pd(0b00001111, a, b);
9739        let e = _mm512_set_pd(0., 0., 0., 0., 5., 5., 7., 7.);
9740        assert_eq_m512d(r, e);
9741    }
9742
9743    #[simd_test(enable = "avx512f,avx512vl")]
9744    unsafe fn test_mm256_mask_permutevar_pd() {
9745        let a = _mm256_set_pd(0., 1., 2., 3.);
9746        let b = _mm256_set1_epi64x(0b1);
9747        let r = _mm256_mask_permutevar_pd(a, 0, a, b);
9748        assert_eq_m256d(r, a);
9749        let r = _mm256_mask_permutevar_pd(a, 0b00001111, a, b);
9750        let e = _mm256_set_pd(1., 1., 3., 3.);
9751        assert_eq_m256d(r, e);
9752    }
9753
9754    #[simd_test(enable = "avx512f,avx512vl")]
9755    unsafe fn test_mm256_maskz_permutevar_pd() {
9756        let a = _mm256_set_pd(0., 1., 2., 3.);
9757        let b = _mm256_set1_epi64x(0b1);
9758        let r = _mm256_maskz_permutevar_pd(0, a, b);
9759        assert_eq_m256d(r, _mm256_setzero_pd());
9760        let r = _mm256_maskz_permutevar_pd(0b00001111, a, b);
9761        let e = _mm256_set_pd(1., 1., 3., 3.);
9762        assert_eq_m256d(r, e);
9763    }
9764
9765    #[simd_test(enable = "avx512f,avx512vl")]
9766    unsafe fn test_mm_mask_permutevar_pd() {
9767        let a = _mm_set_pd(0., 1.);
9768        let b = _mm_set1_epi64x(0b1);
9769        let r = _mm_mask_permutevar_pd(a, 0, a, b);
9770        assert_eq_m128d(r, a);
9771        let r = _mm_mask_permutevar_pd(a, 0b00000011, a, b);
9772        let e = _mm_set_pd(1., 1.);
9773        assert_eq_m128d(r, e);
9774    }
9775
9776    #[simd_test(enable = "avx512f,avx512vl")]
9777    unsafe fn test_mm_maskz_permutevar_pd() {
9778        let a = _mm_set_pd(0., 1.);
9779        let b = _mm_set1_epi64x(0b1);
9780        let r = _mm_maskz_permutevar_pd(0, a, b);
9781        assert_eq_m128d(r, _mm_setzero_pd());
9782        let r = _mm_maskz_permutevar_pd(0b00000011, a, b);
9783        let e = _mm_set_pd(1., 1.);
9784        assert_eq_m128d(r, e);
9785    }
9786
9787    #[simd_test(enable = "avx512f")]
9788    unsafe fn test_mm512_permutexvar_epi64() {
9789        let idx = _mm512_set1_epi64(1);
9790        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9791        let r = _mm512_permutexvar_epi64(idx, a);
9792        let e = _mm512_set1_epi64(6);
9793        assert_eq_m512i(r, e);
9794    }
9795
9796    #[simd_test(enable = "avx512f")]
9797    unsafe fn test_mm512_mask_permutexvar_epi64() {
9798        let idx = _mm512_set1_epi64(1);
9799        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9800        let r = _mm512_mask_permutexvar_epi64(a, 0, idx, a);
9801        assert_eq_m512i(r, a);
9802        let r = _mm512_mask_permutexvar_epi64(a, 0b11111111, idx, a);
9803        let e = _mm512_set1_epi64(6);
9804        assert_eq_m512i(r, e);
9805    }
9806
9807    #[simd_test(enable = "avx512f")]
9808    unsafe fn test_mm512_maskz_permutexvar_epi64() {
9809        let idx = _mm512_set1_epi64(1);
9810        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9811        let r = _mm512_maskz_permutexvar_epi64(0, idx, a);
9812        assert_eq_m512i(r, _mm512_setzero_si512());
9813        let r = _mm512_maskz_permutexvar_epi64(0b00001111, idx, a);
9814        let e = _mm512_set_epi64(0, 0, 0, 0, 6, 6, 6, 6);
9815        assert_eq_m512i(r, e);
9816    }
9817
9818    #[simd_test(enable = "avx512f,avx512vl")]
9819    unsafe fn test_mm256_permutexvar_epi64() {
9820        let idx = _mm256_set1_epi64x(1);
9821        let a = _mm256_set_epi64x(0, 1, 2, 3);
9822        let r = _mm256_permutexvar_epi64(idx, a);
9823        let e = _mm256_set1_epi64x(2);
9824        assert_eq_m256i(r, e);
9825    }
9826
9827    #[simd_test(enable = "avx512f,avx512vl")]
9828    unsafe fn test_mm256_mask_permutexvar_epi64() {
9829        let idx = _mm256_set1_epi64x(1);
9830        let a = _mm256_set_epi64x(0, 1, 2, 3);
9831        let r = _mm256_mask_permutexvar_epi64(a, 0, idx, a);
9832        assert_eq_m256i(r, a);
9833        let r = _mm256_mask_permutexvar_epi64(a, 0b00001111, idx, a);
9834        let e = _mm256_set1_epi64x(2);
9835        assert_eq_m256i(r, e);
9836    }
9837
9838    #[simd_test(enable = "avx512f,avx512vl")]
9839    unsafe fn test_mm256_maskz_permutexvar_epi64() {
9840        let idx = _mm256_set1_epi64x(1);
9841        let a = _mm256_set_epi64x(0, 1, 2, 3);
9842        let r = _mm256_maskz_permutexvar_epi64(0, idx, a);
9843        assert_eq_m256i(r, _mm256_setzero_si256());
9844        let r = _mm256_maskz_permutexvar_epi64(0b00001111, idx, a);
9845        let e = _mm256_set1_epi64x(2);
9846        assert_eq_m256i(r, e);
9847    }
9848
9849    #[simd_test(enable = "avx512f")]
9850    unsafe fn test_mm512_permutexvar_pd() {
9851        let idx = _mm512_set1_epi64(1);
9852        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9853        let r = _mm512_permutexvar_pd(idx, a);
9854        let e = _mm512_set1_pd(6.);
9855        assert_eq_m512d(r, e);
9856    }
9857
9858    #[simd_test(enable = "avx512f")]
9859    unsafe fn test_mm512_mask_permutexvar_pd() {
9860        let idx = _mm512_set1_epi64(1);
9861        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9862        let r = _mm512_mask_permutexvar_pd(a, 0, idx, a);
9863        assert_eq_m512d(r, a);
9864        let r = _mm512_mask_permutexvar_pd(a, 0b11111111, idx, a);
9865        let e = _mm512_set1_pd(6.);
9866        assert_eq_m512d(r, e);
9867    }
9868
9869    #[simd_test(enable = "avx512f")]
9870    unsafe fn test_mm512_maskz_permutexvar_pd() {
9871        let idx = _mm512_set1_epi64(1);
9872        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9873        let r = _mm512_maskz_permutexvar_pd(0, idx, a);
9874        assert_eq_m512d(r, _mm512_setzero_pd());
9875        let r = _mm512_maskz_permutexvar_pd(0b00001111, idx, a);
9876        let e = _mm512_set_pd(0., 0., 0., 0., 6., 6., 6., 6.);
9877        assert_eq_m512d(r, e);
9878    }
9879
9880    #[simd_test(enable = "avx512f,avx512vl")]
9881    unsafe fn test_mm256_permutexvar_pd() {
9882        let idx = _mm256_set1_epi64x(1);
9883        let a = _mm256_set_pd(0., 1., 2., 3.);
9884        let r = _mm256_permutexvar_pd(idx, a);
9885        let e = _mm256_set1_pd(2.);
9886        assert_eq_m256d(r, e);
9887    }
9888
9889    #[simd_test(enable = "avx512f,avx512vl")]
9890    unsafe fn test_mm256_mask_permutexvar_pd() {
9891        let idx = _mm256_set1_epi64x(1);
9892        let a = _mm256_set_pd(0., 1., 2., 3.);
9893        let r = _mm256_mask_permutexvar_pd(a, 0, idx, a);
9894        assert_eq_m256d(r, a);
9895        let r = _mm256_mask_permutexvar_pd(a, 0b00001111, idx, a);
9896        let e = _mm256_set1_pd(2.);
9897        assert_eq_m256d(r, e);
9898    }
9899
9900    #[simd_test(enable = "avx512f,avx512vl")]
9901    unsafe fn test_mm256_maskz_permutexvar_pd() {
9902        let idx = _mm256_set1_epi64x(1);
9903        let a = _mm256_set_pd(0., 1., 2., 3.);
9904        let r = _mm256_maskz_permutexvar_pd(0, idx, a);
9905        assert_eq_m256d(r, _mm256_setzero_pd());
9906        let r = _mm256_maskz_permutexvar_pd(0b00001111, idx, a);
9907        let e = _mm256_set1_pd(2.);
9908        assert_eq_m256d(r, e);
9909    }
9910
9911    #[simd_test(enable = "avx512f")]
9912    unsafe fn test_mm512_permutex2var_epi64() {
9913        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9914        let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
9915        let b = _mm512_set1_epi64(100);
9916        let r = _mm512_permutex2var_epi64(a, idx, b);
9917        let e = _mm512_set_epi64(6, 100, 5, 100, 4, 100, 3, 100);
9918        assert_eq_m512i(r, e);
9919    }
9920
9921    #[simd_test(enable = "avx512f")]
9922    unsafe fn test_mm512_mask_permutex2var_epi64() {
9923        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9924        let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
9925        let b = _mm512_set1_epi64(100);
9926        let r = _mm512_mask_permutex2var_epi64(a, 0, idx, b);
9927        assert_eq_m512i(r, a);
9928        let r = _mm512_mask_permutex2var_epi64(a, 0b11111111, idx, b);
9929        let e = _mm512_set_epi64(6, 100, 5, 100, 4, 100, 3, 100);
9930        assert_eq_m512i(r, e);
9931    }
9932
9933    #[simd_test(enable = "avx512f")]
9934    unsafe fn test_mm512_maskz_permutex2var_epi64() {
9935        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9936        let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
9937        let b = _mm512_set1_epi64(100);
9938        let r = _mm512_maskz_permutex2var_epi64(0, a, idx, b);
9939        assert_eq_m512i(r, _mm512_setzero_si512());
9940        let r = _mm512_maskz_permutex2var_epi64(0b00001111, a, idx, b);
9941        let e = _mm512_set_epi64(0, 0, 0, 0, 4, 100, 3, 100);
9942        assert_eq_m512i(r, e);
9943    }
9944
9945    #[simd_test(enable = "avx512f")]
9946    unsafe fn test_mm512_mask2_permutex2var_epi64() {
9947        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9948        let idx = _mm512_set_epi64(1000, 1 << 3, 2000, 1 << 3, 3, 1 << 3, 4, 1 << 3);
9949        let b = _mm512_set1_epi64(100);
9950        let r = _mm512_mask2_permutex2var_epi64(a, idx, 0, b);
9951        assert_eq_m512i(r, idx);
9952        let r = _mm512_mask2_permutex2var_epi64(a, idx, 0b00001111, b);
9953        let e = _mm512_set_epi64(1000, 1 << 3, 2000, 1 << 3, 4, 100, 3, 100);
9954        assert_eq_m512i(r, e);
9955    }
9956
9957    #[simd_test(enable = "avx512f,avx512vl")]
9958    unsafe fn test_mm256_permutex2var_epi64() {
9959        let a = _mm256_set_epi64x(0, 1, 2, 3);
9960        let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
9961        let b = _mm256_set1_epi64x(100);
9962        let r = _mm256_permutex2var_epi64(a, idx, b);
9963        let e = _mm256_set_epi64x(2, 100, 1, 100);
9964        assert_eq_m256i(r, e);
9965    }
9966
9967    #[simd_test(enable = "avx512f,avx512vl")]
9968    unsafe fn test_mm256_mask_permutex2var_epi64() {
9969        let a = _mm256_set_epi64x(0, 1, 2, 3);
9970        let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
9971        let b = _mm256_set1_epi64x(100);
9972        let r = _mm256_mask_permutex2var_epi64(a, 0, idx, b);
9973        assert_eq_m256i(r, a);
9974        let r = _mm256_mask_permutex2var_epi64(a, 0b00001111, idx, b);
9975        let e = _mm256_set_epi64x(2, 100, 1, 100);
9976        assert_eq_m256i(r, e);
9977    }
9978
9979    #[simd_test(enable = "avx512f,avx512vl")]
9980    unsafe fn test_mm256_maskz_permutex2var_epi64() {
9981        let a = _mm256_set_epi64x(0, 1, 2, 3);
9982        let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
9983        let b = _mm256_set1_epi64x(100);
9984        let r = _mm256_maskz_permutex2var_epi64(0, a, idx, b);
9985        assert_eq_m256i(r, _mm256_setzero_si256());
9986        let r = _mm256_maskz_permutex2var_epi64(0b00001111, a, idx, b);
9987        let e = _mm256_set_epi64x(2, 100, 1, 100);
9988        assert_eq_m256i(r, e);
9989    }
9990
9991    #[simd_test(enable = "avx512f,avx512vl")]
9992    unsafe fn test_mm256_mask2_permutex2var_epi64() {
9993        let a = _mm256_set_epi64x(0, 1, 2, 3);
9994        let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
9995        let b = _mm256_set1_epi64x(100);
9996        let r = _mm256_mask2_permutex2var_epi64(a, idx, 0, b);
9997        assert_eq_m256i(r, idx);
9998        let r = _mm256_mask2_permutex2var_epi64(a, idx, 0b00001111, b);
9999        let e = _mm256_set_epi64x(2, 100, 1, 100);
10000        assert_eq_m256i(r, e);
10001    }
10002
10003    #[simd_test(enable = "avx512f,avx512vl")]
10004    unsafe fn test_mm_permutex2var_epi64() {
10005        let a = _mm_set_epi64x(0, 1);
10006        let idx = _mm_set_epi64x(1, 1 << 1);
10007        let b = _mm_set1_epi64x(100);
10008        let r = _mm_permutex2var_epi64(a, idx, b);
10009        let e = _mm_set_epi64x(0, 100);
10010        assert_eq_m128i(r, e);
10011    }
10012
10013    #[simd_test(enable = "avx512f,avx512vl")]
10014    unsafe fn test_mm_mask_permutex2var_epi64() {
10015        let a = _mm_set_epi64x(0, 1);
10016        let idx = _mm_set_epi64x(1, 1 << 1);
10017        let b = _mm_set1_epi64x(100);
10018        let r = _mm_mask_permutex2var_epi64(a, 0, idx, b);
10019        assert_eq_m128i(r, a);
10020        let r = _mm_mask_permutex2var_epi64(a, 0b00000011, idx, b);
10021        let e = _mm_set_epi64x(0, 100);
10022        assert_eq_m128i(r, e);
10023    }
10024
10025    #[simd_test(enable = "avx512f,avx512vl")]
10026    unsafe fn test_mm_maskz_permutex2var_epi64() {
10027        let a = _mm_set_epi64x(0, 1);
10028        let idx = _mm_set_epi64x(1, 1 << 1);
10029        let b = _mm_set1_epi64x(100);
10030        let r = _mm_maskz_permutex2var_epi64(0, a, idx, b);
10031        assert_eq_m128i(r, _mm_setzero_si128());
10032        let r = _mm_maskz_permutex2var_epi64(0b00000011, a, idx, b);
10033        let e = _mm_set_epi64x(0, 100);
10034        assert_eq_m128i(r, e);
10035    }
10036
10037    #[simd_test(enable = "avx512f,avx512vl")]
10038    unsafe fn test_mm_mask2_permutex2var_epi64() {
10039        let a = _mm_set_epi64x(0, 1);
10040        let idx = _mm_set_epi64x(1, 1 << 1);
10041        let b = _mm_set1_epi64x(100);
10042        let r = _mm_mask2_permutex2var_epi64(a, idx, 0, b);
10043        assert_eq_m128i(r, idx);
10044        let r = _mm_mask2_permutex2var_epi64(a, idx, 0b00000011, b);
10045        let e = _mm_set_epi64x(0, 100);
10046        assert_eq_m128i(r, e);
10047    }
10048
10049    #[simd_test(enable = "avx512f")]
10050    unsafe fn test_mm512_permutex2var_pd() {
10051        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
10052        let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
10053        let b = _mm512_set1_pd(100.);
10054        let r = _mm512_permutex2var_pd(a, idx, b);
10055        let e = _mm512_set_pd(6., 100., 5., 100., 4., 100., 3., 100.);
10056        assert_eq_m512d(r, e);
10057    }
10058
10059    #[simd_test(enable = "avx512f")]
10060    unsafe fn test_mm512_mask_permutex2var_pd() {
10061        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
10062        let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
10063        let b = _mm512_set1_pd(100.);
10064        let r = _mm512_mask_permutex2var_pd(a, 0, idx, b);
10065        assert_eq_m512d(r, a);
10066        let r = _mm512_mask_permutex2var_pd(a, 0b11111111, idx, b);
10067        let e = _mm512_set_pd(6., 100., 5., 100., 4., 100., 3., 100.);
10068        assert_eq_m512d(r, e);
10069    }
10070
10071    #[simd_test(enable = "avx512f")]
10072    unsafe fn test_mm512_maskz_permutex2var_pd() {
10073        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
10074        let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
10075        let b = _mm512_set1_pd(100.);
10076        let r = _mm512_maskz_permutex2var_pd(0, a, idx, b);
10077        assert_eq_m512d(r, _mm512_setzero_pd());
10078        let r = _mm512_maskz_permutex2var_pd(0b00001111, a, idx, b);
10079        let e = _mm512_set_pd(0., 0., 0., 0., 4., 100., 3., 100.);
10080        assert_eq_m512d(r, e);
10081    }
10082
10083    #[simd_test(enable = "avx512f")]
10084    unsafe fn test_mm512_mask2_permutex2var_pd() {
10085        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
10086        let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
10087        let b = _mm512_set1_pd(100.);
10088        let r = _mm512_mask2_permutex2var_pd(a, idx, 0, b);
10089        assert_eq_m512d(r, _mm512_castsi512_pd(idx));
10090        let r = _mm512_mask2_permutex2var_pd(a, idx, 0b11111111, b);
10091        let e = _mm512_set_pd(6., 100., 5., 100., 4., 100., 3., 100.);
10092        assert_eq_m512d(r, e);
10093    }
10094
10095    #[simd_test(enable = "avx512f,avx512vl")]
10096    unsafe fn test_mm256_permutex2var_pd() {
10097        let a = _mm256_set_pd(0., 1., 2., 3.);
10098        let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10099        let b = _mm256_set1_pd(100.);
10100        let r = _mm256_permutex2var_pd(a, idx, b);
10101        let e = _mm256_set_pd(2., 100., 1., 100.);
10102        assert_eq_m256d(r, e);
10103    }
10104
10105    #[simd_test(enable = "avx512f,avx512vl")]
10106    unsafe fn test_mm256_mask_permutex2var_pd() {
10107        let a = _mm256_set_pd(0., 1., 2., 3.);
10108        let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10109        let b = _mm256_set1_pd(100.);
10110        let r = _mm256_mask_permutex2var_pd(a, 0, idx, b);
10111        assert_eq_m256d(r, a);
10112        let r = _mm256_mask_permutex2var_pd(a, 0b00001111, idx, b);
10113        let e = _mm256_set_pd(2., 100., 1., 100.);
10114        assert_eq_m256d(r, e);
10115    }
10116
10117    #[simd_test(enable = "avx512f,avx512vl")]
10118    unsafe fn test_mm256_maskz_permutex2var_pd() {
10119        let a = _mm256_set_pd(0., 1., 2., 3.);
10120        let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10121        let b = _mm256_set1_pd(100.);
10122        let r = _mm256_maskz_permutex2var_pd(0, a, idx, b);
10123        assert_eq_m256d(r, _mm256_setzero_pd());
10124        let r = _mm256_maskz_permutex2var_pd(0b00001111, a, idx, b);
10125        let e = _mm256_set_pd(2., 100., 1., 100.);
10126        assert_eq_m256d(r, e);
10127    }
10128
10129    #[simd_test(enable = "avx512f,avx512vl")]
10130    unsafe fn test_mm256_mask2_permutex2var_pd() {
10131        let a = _mm256_set_pd(0., 1., 2., 3.);
10132        let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10133        let b = _mm256_set1_pd(100.);
10134        let r = _mm256_mask2_permutex2var_pd(a, idx, 0, b);
10135        assert_eq_m256d(r, _mm256_castsi256_pd(idx));
10136        let r = _mm256_mask2_permutex2var_pd(a, idx, 0b00001111, b);
10137        let e = _mm256_set_pd(2., 100., 1., 100.);
10138        assert_eq_m256d(r, e);
10139    }
10140
10141    #[simd_test(enable = "avx512f,avx512vl")]
10142    unsafe fn test_mm_permutex2var_pd() {
10143        let a = _mm_set_pd(0., 1.);
10144        let idx = _mm_set_epi64x(1, 1 << 1);
10145        let b = _mm_set1_pd(100.);
10146        let r = _mm_permutex2var_pd(a, idx, b);
10147        let e = _mm_set_pd(0., 100.);
10148        assert_eq_m128d(r, e);
10149    }
10150
10151    #[simd_test(enable = "avx512f,avx512vl")]
10152    unsafe fn test_mm_mask_permutex2var_pd() {
10153        let a = _mm_set_pd(0., 1.);
10154        let idx = _mm_set_epi64x(1, 1 << 1);
10155        let b = _mm_set1_pd(100.);
10156        let r = _mm_mask_permutex2var_pd(a, 0, idx, b);
10157        assert_eq_m128d(r, a);
10158        let r = _mm_mask_permutex2var_pd(a, 0b00000011, idx, b);
10159        let e = _mm_set_pd(0., 100.);
10160        assert_eq_m128d(r, e);
10161    }
10162
10163    #[simd_test(enable = "avx512f,avx512vl")]
10164    unsafe fn test_mm_maskz_permutex2var_pd() {
10165        let a = _mm_set_pd(0., 1.);
10166        let idx = _mm_set_epi64x(1, 1 << 1);
10167        let b = _mm_set1_pd(100.);
10168        let r = _mm_maskz_permutex2var_pd(0, a, idx, b);
10169        assert_eq_m128d(r, _mm_setzero_pd());
10170        let r = _mm_maskz_permutex2var_pd(0b00000011, a, idx, b);
10171        let e = _mm_set_pd(0., 100.);
10172        assert_eq_m128d(r, e);
10173    }
10174
10175    #[simd_test(enable = "avx512f,avx512vl")]
10176    unsafe fn test_mm_mask2_permutex2var_pd() {
10177        let a = _mm_set_pd(0., 1.);
10178        let idx = _mm_set_epi64x(1, 1 << 1);
10179        let b = _mm_set1_pd(100.);
10180        let r = _mm_mask2_permutex2var_pd(a, idx, 0, b);
10181        assert_eq_m128d(r, _mm_castsi128_pd(idx));
10182        let r = _mm_mask2_permutex2var_pd(a, idx, 0b00000011, b);
10183        let e = _mm_set_pd(0., 100.);
10184        assert_eq_m128d(r, e);
10185    }
10186
10187    #[simd_test(enable = "avx512f,avx512vl")]
10188    unsafe fn test_mm256_mask_shuffle_pd() {
10189        let a = _mm256_set_pd(1., 4., 5., 8.);
10190        let b = _mm256_set_pd(2., 3., 6., 7.);
10191        let r = _mm256_mask_shuffle_pd::<0b11_11_11_11>(a, 0, a, b);
10192        assert_eq_m256d(r, a);
10193        let r = _mm256_mask_shuffle_pd::<0b11_11_11_11>(a, 0b00001111, a, b);
10194        let e = _mm256_set_pd(2., 1., 6., 5.);
10195        assert_eq_m256d(r, e);
10196    }
10197
10198    #[simd_test(enable = "avx512f,avx512vl")]
10199    unsafe fn test_mm256_maskz_shuffle_pd() {
10200        let a = _mm256_set_pd(1., 4., 5., 8.);
10201        let b = _mm256_set_pd(2., 3., 6., 7.);
10202        let r = _mm256_maskz_shuffle_pd::<0b11_11_11_11>(0, a, b);
10203        assert_eq_m256d(r, _mm256_setzero_pd());
10204        let r = _mm256_maskz_shuffle_pd::<0b11_11_11_11>(0b00001111, a, b);
10205        let e = _mm256_set_pd(2., 1., 6., 5.);
10206        assert_eq_m256d(r, e);
10207    }
10208
10209    #[simd_test(enable = "avx512f,avx512vl")]
10210    unsafe fn test_mm_mask_shuffle_pd() {
10211        let a = _mm_set_pd(1., 4.);
10212        let b = _mm_set_pd(2., 3.);
10213        let r = _mm_mask_shuffle_pd::<0b11_11_11_11>(a, 0, a, b);
10214        assert_eq_m128d(r, a);
10215        let r = _mm_mask_shuffle_pd::<0b11_11_11_11>(a, 0b00000011, a, b);
10216        let e = _mm_set_pd(2., 1.);
10217        assert_eq_m128d(r, e);
10218    }
10219
10220    #[simd_test(enable = "avx512f,avx512vl")]
10221    unsafe fn test_mm_maskz_shuffle_pd() {
10222        let a = _mm_set_pd(1., 4.);
10223        let b = _mm_set_pd(2., 3.);
10224        let r = _mm_maskz_shuffle_pd::<0b11_11_11_11>(0, a, b);
10225        assert_eq_m128d(r, _mm_setzero_pd());
10226        let r = _mm_maskz_shuffle_pd::<0b11_11_11_11>(0b00000011, a, b);
10227        let e = _mm_set_pd(2., 1.);
10228        assert_eq_m128d(r, e);
10229    }
10230
10231    #[simd_test(enable = "avx512f")]
10232    unsafe fn test_mm512_shuffle_i64x2() {
10233        let a = _mm512_setr_epi64(1, 4, 5, 8, 9, 12, 13, 16);
10234        let b = _mm512_setr_epi64(2, 3, 6, 7, 10, 11, 14, 15);
10235        let r = _mm512_shuffle_i64x2::<0b00_00_00_00>(a, b);
10236        let e = _mm512_setr_epi64(1, 4, 1, 4, 2, 3, 2, 3);
10237        assert_eq_m512i(r, e);
10238    }
10239
10240    #[simd_test(enable = "avx512f")]
10241    unsafe fn test_mm512_mask_shuffle_i64x2() {
10242        let a = _mm512_setr_epi64(1, 4, 5, 8, 9, 12, 13, 16);
10243        let b = _mm512_setr_epi64(2, 3, 6, 7, 10, 11, 14, 15);
10244        let r = _mm512_mask_shuffle_i64x2::<0b00_00_00_00>(a, 0, a, b);
10245        assert_eq_m512i(r, a);
10246        let r = _mm512_mask_shuffle_i64x2::<0b00_00_00_00>(a, 0b11111111, a, b);
10247        let e = _mm512_setr_epi64(1, 4, 1, 4, 2, 3, 2, 3);
10248        assert_eq_m512i(r, e);
10249    }
10250
10251    #[simd_test(enable = "avx512f")]
10252    unsafe fn test_mm512_maskz_shuffle_i64x2() {
10253        let a = _mm512_setr_epi64(1, 4, 5, 8, 9, 12, 13, 16);
10254        let b = _mm512_setr_epi64(2, 3, 6, 7, 10, 11, 14, 15);
10255        let r = _mm512_maskz_shuffle_i64x2::<0b00_00_00_00>(0, a, b);
10256        assert_eq_m512i(r, _mm512_setzero_si512());
10257        let r = _mm512_maskz_shuffle_i64x2::<0b00_00_00_00>(0b00001111, a, b);
10258        let e = _mm512_setr_epi64(1, 4, 1, 4, 0, 0, 0, 0);
10259        assert_eq_m512i(r, e);
10260    }
10261
10262    #[simd_test(enable = "avx512f,avx512vl")]
10263    unsafe fn test_mm256_shuffle_i64x2() {
10264        let a = _mm256_set_epi64x(1, 4, 5, 8);
10265        let b = _mm256_set_epi64x(2, 3, 6, 7);
10266        let r = _mm256_shuffle_i64x2::<0b00>(a, b);
10267        let e = _mm256_set_epi64x(6, 7, 5, 8);
10268        assert_eq_m256i(r, e);
10269    }
10270
10271    #[simd_test(enable = "avx512f,avx512vl")]
10272    unsafe fn test_mm256_mask_shuffle_i64x2() {
10273        let a = _mm256_set_epi64x(1, 4, 5, 8);
10274        let b = _mm256_set_epi64x(2, 3, 6, 7);
10275        let r = _mm256_mask_shuffle_i64x2::<0b00>(a, 0, a, b);
10276        assert_eq_m256i(r, a);
10277        let r = _mm256_mask_shuffle_i64x2::<0b00>(a, 0b00001111, a, b);
10278        let e = _mm256_set_epi64x(6, 7, 5, 8);
10279        assert_eq_m256i(r, e);
10280    }
10281
10282    #[simd_test(enable = "avx512f,avx512vl")]
10283    unsafe fn test_mm256_maskz_shuffle_i64x2() {
10284        let a = _mm256_set_epi64x(1, 4, 5, 8);
10285        let b = _mm256_set_epi64x(2, 3, 6, 7);
10286        let r = _mm256_maskz_shuffle_i64x2::<0b00>(0, a, b);
10287        assert_eq_m256i(r, _mm256_setzero_si256());
10288        let r = _mm256_maskz_shuffle_i64x2::<0b00>(0b00001111, a, b);
10289        let e = _mm256_set_epi64x(6, 7, 5, 8);
10290        assert_eq_m256i(r, e);
10291    }
10292
10293    #[simd_test(enable = "avx512f")]
10294    unsafe fn test_mm512_shuffle_f64x2() {
10295        let a = _mm512_setr_pd(1., 4., 5., 8., 9., 12., 13., 16.);
10296        let b = _mm512_setr_pd(2., 3., 6., 7., 10., 11., 14., 15.);
10297        let r = _mm512_shuffle_f64x2::<0b00_00_00_00>(a, b);
10298        let e = _mm512_setr_pd(1., 4., 1., 4., 2., 3., 2., 3.);
10299        assert_eq_m512d(r, e);
10300    }
10301
10302    #[simd_test(enable = "avx512f")]
10303    unsafe fn test_mm512_mask_shuffle_f64x2() {
10304        let a = _mm512_setr_pd(1., 4., 5., 8., 9., 12., 13., 16.);
10305        let b = _mm512_setr_pd(2., 3., 6., 7., 10., 11., 14., 15.);
10306        let r = _mm512_mask_shuffle_f64x2::<0b00_00_00_00>(a, 0, a, b);
10307        assert_eq_m512d(r, a);
10308        let r = _mm512_mask_shuffle_f64x2::<0b00_00_00_00>(a, 0b11111111, a, b);
10309        let e = _mm512_setr_pd(1., 4., 1., 4., 2., 3., 2., 3.);
10310        assert_eq_m512d(r, e);
10311    }
10312
10313    #[simd_test(enable = "avx512f")]
10314    unsafe fn test_mm512_maskz_shuffle_f64x2() {
10315        let a = _mm512_setr_pd(1., 4., 5., 8., 9., 12., 13., 16.);
10316        let b = _mm512_setr_pd(2., 3., 6., 7., 10., 11., 14., 15.);
10317        let r = _mm512_maskz_shuffle_f64x2::<0b00_00_00_00>(0, a, b);
10318        assert_eq_m512d(r, _mm512_setzero_pd());
10319        let r = _mm512_maskz_shuffle_f64x2::<0b00_00_00_00>(0b00001111, a, b);
10320        let e = _mm512_setr_pd(1., 4., 1., 4., 0., 0., 0., 0.);
10321        assert_eq_m512d(r, e);
10322    }
10323
10324    #[simd_test(enable = "avx512f,avx512vl")]
10325    unsafe fn test_mm256_shuffle_f64x2() {
10326        let a = _mm256_set_pd(1., 4., 5., 8.);
10327        let b = _mm256_set_pd(2., 3., 6., 7.);
10328        let r = _mm256_shuffle_f64x2::<0b00>(a, b);
10329        let e = _mm256_set_pd(6., 7., 5., 8.);
10330        assert_eq_m256d(r, e);
10331    }
10332
10333    #[simd_test(enable = "avx512f,avx512vl")]
10334    unsafe fn test_mm256_mask_shuffle_f64x2() {
10335        let a = _mm256_set_pd(1., 4., 5., 8.);
10336        let b = _mm256_set_pd(2., 3., 6., 7.);
10337        let r = _mm256_mask_shuffle_f64x2::<0b00>(a, 0, a, b);
10338        assert_eq_m256d(r, a);
10339        let r = _mm256_mask_shuffle_f64x2::<0b00>(a, 0b00001111, a, b);
10340        let e = _mm256_set_pd(6., 7., 5., 8.);
10341        assert_eq_m256d(r, e);
10342    }
10343
10344    #[simd_test(enable = "avx512f,avx512vl")]
10345    unsafe fn test_mm256_maskz_shuffle_f64x2() {
10346        let a = _mm256_set_pd(1., 4., 5., 8.);
10347        let b = _mm256_set_pd(2., 3., 6., 7.);
10348        let r = _mm256_maskz_shuffle_f64x2::<0b00>(0, a, b);
10349        assert_eq_m256d(r, _mm256_setzero_pd());
10350        let r = _mm256_maskz_shuffle_f64x2::<0b00>(0b00001111, a, b);
10351        let e = _mm256_set_pd(6., 7., 5., 8.);
10352        assert_eq_m256d(r, e);
10353    }
10354
10355    #[simd_test(enable = "avx512f")]
10356    unsafe fn test_mm512_movedup_pd() {
10357        let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10358        let r = _mm512_movedup_pd(a);
10359        let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
10360        assert_eq_m512d(r, e);
10361    }
10362
10363    #[simd_test(enable = "avx512f")]
10364    unsafe fn test_mm512_mask_movedup_pd() {
10365        let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10366        let r = _mm512_mask_movedup_pd(a, 0, a);
10367        assert_eq_m512d(r, a);
10368        let r = _mm512_mask_movedup_pd(a, 0b11111111, a);
10369        let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
10370        assert_eq_m512d(r, e);
10371    }
10372
10373    #[simd_test(enable = "avx512f")]
10374    unsafe fn test_mm512_maskz_movedup_pd() {
10375        let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10376        let r = _mm512_maskz_movedup_pd(0, a);
10377        assert_eq_m512d(r, _mm512_setzero_pd());
10378        let r = _mm512_maskz_movedup_pd(0b00001111, a);
10379        let e = _mm512_setr_pd(1., 1., 3., 3., 0., 0., 0., 0.);
10380        assert_eq_m512d(r, e);
10381    }
10382
10383    #[simd_test(enable = "avx512f,avx512vl")]
10384    unsafe fn test_mm256_mask_movedup_pd() {
10385        let a = _mm256_set_pd(1., 2., 3., 4.);
10386        let r = _mm256_mask_movedup_pd(a, 0, a);
10387        assert_eq_m256d(r, a);
10388        let r = _mm256_mask_movedup_pd(a, 0b00001111, a);
10389        let e = _mm256_set_pd(2., 2., 4., 4.);
10390        assert_eq_m256d(r, e);
10391    }
10392
10393    #[simd_test(enable = "avx512f,avx512vl")]
10394    unsafe fn test_mm256_maskz_movedup_pd() {
10395        let a = _mm256_set_pd(1., 2., 3., 4.);
10396        let r = _mm256_maskz_movedup_pd(0, a);
10397        assert_eq_m256d(r, _mm256_setzero_pd());
10398        let r = _mm256_maskz_movedup_pd(0b00001111, a);
10399        let e = _mm256_set_pd(2., 2., 4., 4.);
10400        assert_eq_m256d(r, e);
10401    }
10402
10403    #[simd_test(enable = "avx512f,avx512vl")]
10404    unsafe fn test_mm_mask_movedup_pd() {
10405        let a = _mm_set_pd(1., 2.);
10406        let r = _mm_mask_movedup_pd(a, 0, a);
10407        assert_eq_m128d(r, a);
10408        let r = _mm_mask_movedup_pd(a, 0b00000011, a);
10409        let e = _mm_set_pd(2., 2.);
10410        assert_eq_m128d(r, e);
10411    }
10412
10413    #[simd_test(enable = "avx512f,avx512vl")]
10414    unsafe fn test_mm_maskz_movedup_pd() {
10415        let a = _mm_set_pd(1., 2.);
10416        let r = _mm_maskz_movedup_pd(0, a);
10417        assert_eq_m128d(r, _mm_setzero_pd());
10418        let r = _mm_maskz_movedup_pd(0b00000011, a);
10419        let e = _mm_set_pd(2., 2.);
10420        assert_eq_m128d(r, e);
10421    }
10422
10423    #[simd_test(enable = "avx512f")]
10424    unsafe fn test_mm512_inserti64x4() {
10425        let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10426        let b = _mm256_setr_epi64x(17, 18, 19, 20);
10427        let r = _mm512_inserti64x4::<1>(a, b);
10428        let e = _mm512_setr_epi64(1, 2, 3, 4, 17, 18, 19, 20);
10429        assert_eq_m512i(r, e);
10430    }
10431
10432    #[simd_test(enable = "avx512f")]
10433    unsafe fn test_mm512_mask_inserti64x4() {
10434        let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10435        let b = _mm256_setr_epi64x(17, 18, 19, 20);
10436        let r = _mm512_mask_inserti64x4::<1>(a, 0, a, b);
10437        assert_eq_m512i(r, a);
10438        let r = _mm512_mask_inserti64x4::<1>(a, 0b11111111, a, b);
10439        let e = _mm512_setr_epi64(1, 2, 3, 4, 17, 18, 19, 20);
10440        assert_eq_m512i(r, e);
10441    }
10442
10443    #[simd_test(enable = "avx512f")]
10444    unsafe fn test_mm512_maskz_inserti64x4() {
10445        let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10446        let b = _mm256_setr_epi64x(17, 18, 19, 20);
10447        let r = _mm512_maskz_inserti64x4::<1>(0, a, b);
10448        assert_eq_m512i(r, _mm512_setzero_si512());
10449        let r = _mm512_maskz_inserti64x4::<1>(0b00001111, a, b);
10450        let e = _mm512_setr_epi64(1, 2, 3, 4, 0, 0, 0, 0);
10451        assert_eq_m512i(r, e);
10452    }
10453
10454    #[simd_test(enable = "avx512f")]
10455    unsafe fn test_mm512_insertf64x4() {
10456        let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10457        let b = _mm256_setr_pd(17., 18., 19., 20.);
10458        let r = _mm512_insertf64x4::<1>(a, b);
10459        let e = _mm512_setr_pd(1., 2., 3., 4., 17., 18., 19., 20.);
10460        assert_eq_m512d(r, e);
10461    }
10462
10463    #[simd_test(enable = "avx512f")]
10464    unsafe fn test_mm512_mask_insertf64x4() {
10465        let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10466        let b = _mm256_setr_pd(17., 18., 19., 20.);
10467        let r = _mm512_mask_insertf64x4::<1>(a, 0, a, b);
10468        assert_eq_m512d(r, a);
10469        let r = _mm512_mask_insertf64x4::<1>(a, 0b11111111, a, b);
10470        let e = _mm512_setr_pd(1., 2., 3., 4., 17., 18., 19., 20.);
10471        assert_eq_m512d(r, e);
10472    }
10473
10474    #[simd_test(enable = "avx512f")]
10475    unsafe fn test_mm512_maskz_insertf64x4() {
10476        let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10477        let b = _mm256_setr_pd(17., 18., 19., 20.);
10478        let r = _mm512_maskz_insertf64x4::<1>(0, a, b);
10479        assert_eq_m512d(r, _mm512_setzero_pd());
10480        let r = _mm512_maskz_insertf64x4::<1>(0b00001111, a, b);
10481        let e = _mm512_setr_pd(1., 2., 3., 4., 0., 0., 0., 0.);
10482        assert_eq_m512d(r, e);
10483    }
10484
10485    #[simd_test(enable = "avx512f")]
10486    unsafe fn test_mm512_castpd128_pd512() {
10487        let a = _mm_setr_pd(17., 18.);
10488        let r = _mm512_castpd128_pd512(a);
10489        assert_eq_m128d(_mm512_castpd512_pd128(r), a);
10490    }
10491
10492    #[simd_test(enable = "avx512f")]
10493    unsafe fn test_mm512_castpd256_pd512() {
10494        let a = _mm256_setr_pd(17., 18., 19., 20.);
10495        let r = _mm512_castpd256_pd512(a);
10496        assert_eq_m256d(_mm512_castpd512_pd256(r), a);
10497    }
10498
10499    #[simd_test(enable = "avx512f")]
10500    unsafe fn test_mm512_zextpd128_pd512() {
10501        let a = _mm_setr_pd(17., 18.);
10502        let r = _mm512_zextpd128_pd512(a);
10503        let e = _mm512_setr_pd(17., 18., 0., 0., 0., 0., 0., 0.);
10504        assert_eq_m512d(r, e);
10505    }
10506
10507    #[simd_test(enable = "avx512f")]
10508    unsafe fn test_mm512_zextpd256_pd512() {
10509        let a = _mm256_setr_pd(17., 18., 19., 20.);
10510        let r = _mm512_zextpd256_pd512(a);
10511        let e = _mm512_setr_pd(17., 18., 19., 20., 0., 0., 0., 0.);
10512        assert_eq_m512d(r, e);
10513    }
10514
10515    #[simd_test(enable = "avx512f")]
10516    unsafe fn test_mm512_castpd512_pd128() {
10517        let a = _mm512_setr_pd(17., 18., -1., -1., -1., -1., -1., -1.);
10518        let r = _mm512_castpd512_pd128(a);
10519        let e = _mm_setr_pd(17., 18.);
10520        assert_eq_m128d(r, e);
10521    }
10522
10523    #[simd_test(enable = "avx512f")]
10524    unsafe fn test_mm512_castpd512_pd256() {
10525        let a = _mm512_setr_pd(17., 18., 19., 20., -1., -1., -1., -1.);
10526        let r = _mm512_castpd512_pd256(a);
10527        let e = _mm256_setr_pd(17., 18., 19., 20.);
10528        assert_eq_m256d(r, e);
10529    }
10530
10531    #[simd_test(enable = "avx512f")]
10532    unsafe fn test_mm512_castpd_ps() {
10533        let a = _mm512_set1_pd(1.);
10534        let r = _mm512_castpd_ps(a);
10535        let e = _mm512_set_ps(
10536            1.875, 0.0, 1.875, 0.0, 1.875, 0.0, 1.875, 0.0, 1.875, 0.0, 1.875, 0.0, 1.875, 0.0,
10537            1.875, 0.0,
10538        );
10539        assert_eq_m512(r, e);
10540    }
10541
10542    #[simd_test(enable = "avx512f")]
10543    unsafe fn test_mm512_castpd_si512() {
10544        let a = _mm512_set1_pd(1.);
10545        let r = _mm512_castpd_si512(a);
10546        let e = _mm512_set_epi32(
10547            1072693248, 0, 1072693248, 0, 1072693248, 0, 1072693248, 0, 1072693248, 0, 1072693248,
10548            0, 1072693248, 0, 1072693248, 0,
10549        );
10550        assert_eq_m512i(r, e);
10551    }
10552
10553    #[simd_test(enable = "avx512f")]
10554    unsafe fn test_mm512_castsi128_si512() {
10555        let a = _mm_setr_epi64x(17, 18);
10556        let r = _mm512_castsi128_si512(a);
10557        assert_eq_m128i(_mm512_castsi512_si128(r), a);
10558    }
10559
10560    #[simd_test(enable = "avx512f")]
10561    unsafe fn test_mm512_castsi256_si512() {
10562        let a = _mm256_setr_epi64x(17, 18, 19, 20);
10563        let r = _mm512_castsi256_si512(a);
10564        assert_eq_m256i(_mm512_castsi512_si256(r), a);
10565    }
10566
10567    #[simd_test(enable = "avx512f")]
10568    unsafe fn test_mm512_zextsi128_si512() {
10569        let a = _mm_setr_epi64x(17, 18);
10570        let r = _mm512_zextsi128_si512(a);
10571        let e = _mm512_setr_epi64(17, 18, 0, 0, 0, 0, 0, 0);
10572        assert_eq_m512i(r, e);
10573    }
10574
10575    #[simd_test(enable = "avx512f")]
10576    unsafe fn test_mm512_zextsi256_si512() {
10577        let a = _mm256_setr_epi64x(17, 18, 19, 20);
10578        let r = _mm512_zextsi256_si512(a);
10579        let e = _mm512_setr_epi64(17, 18, 19, 20, 0, 0, 0, 0);
10580        assert_eq_m512i(r, e);
10581    }
10582
10583    #[simd_test(enable = "avx512f")]
10584    unsafe fn test_mm512_castsi512_si128() {
10585        let a = _mm512_setr_epi64(17, 18, -1, -1, -1, -1, -1, -1);
10586        let r = _mm512_castsi512_si128(a);
10587        let e = _mm_setr_epi64x(17, 18);
10588        assert_eq_m128i(r, e);
10589    }
10590
10591    #[simd_test(enable = "avx512f")]
10592    unsafe fn test_mm512_castsi512_si256() {
10593        let a = _mm512_setr_epi64(17, 18, 19, 20, -1, -1, -1, -1);
10594        let r = _mm512_castsi512_si256(a);
10595        let e = _mm256_setr_epi64x(17, 18, 19, 20);
10596        assert_eq_m256i(r, e);
10597    }
10598
10599    #[simd_test(enable = "avx512f")]
10600    unsafe fn test_mm512_castsi512_ps() {
10601        let a = _mm512_set1_epi64(1 << 62);
10602        let r = _mm512_castsi512_ps(a);
10603        let e = _mm512_set_ps(
10604            2., 0., 2., 0., 2., 0., 2., 0., 2., 0., 2., 0., 2., 0., 2., 0.,
10605        );
10606        assert_eq_m512(r, e);
10607    }
10608
10609    #[simd_test(enable = "avx512f")]
10610    unsafe fn test_mm512_castsi512_pd() {
10611        let a = _mm512_set1_epi64(1 << 62);
10612        let r = _mm512_castsi512_pd(a);
10613        let e = _mm512_set_pd(2., 2., 2., 2., 2., 2., 2., 2.);
10614        assert_eq_m512d(r, e);
10615    }
10616
10617    #[simd_test(enable = "avx512f")]
10618    unsafe fn test_mm512_broadcastq_epi64() {
10619        let a = _mm_setr_epi64x(17, 18);
10620        let r = _mm512_broadcastq_epi64(a);
10621        let e = _mm512_set1_epi64(17);
10622        assert_eq_m512i(r, e);
10623    }
10624
10625    #[simd_test(enable = "avx512f")]
10626    unsafe fn test_mm512_mask_broadcastq_epi64() {
10627        let src = _mm512_set1_epi64(18);
10628        let a = _mm_setr_epi64x(17, 18);
10629        let r = _mm512_mask_broadcastq_epi64(src, 0, a);
10630        assert_eq_m512i(r, src);
10631        let r = _mm512_mask_broadcastq_epi64(src, 0b11111111, a);
10632        let e = _mm512_set1_epi64(17);
10633        assert_eq_m512i(r, e);
10634    }
10635
10636    #[simd_test(enable = "avx512f")]
10637    unsafe fn test_mm512_maskz_broadcastq_epi64() {
10638        let a = _mm_setr_epi64x(17, 18);
10639        let r = _mm512_maskz_broadcastq_epi64(0, a);
10640        assert_eq_m512i(r, _mm512_setzero_si512());
10641        let r = _mm512_maskz_broadcastq_epi64(0b00001111, a);
10642        let e = _mm512_set_epi64(0, 0, 0, 0, 17, 17, 17, 17);
10643        assert_eq_m512i(r, e);
10644    }
10645
10646    #[simd_test(enable = "avx512f,avx512vl")]
10647    unsafe fn test_mm256_mask_broadcastq_epi64() {
10648        let src = _mm256_set1_epi64x(18);
10649        let a = _mm_set_epi64x(17, 18);
10650        let r = _mm256_mask_broadcastq_epi64(src, 0, a);
10651        assert_eq_m256i(r, src);
10652        let r = _mm256_mask_broadcastq_epi64(src, 0b00001111, a);
10653        let e = _mm256_set1_epi64x(18);
10654        assert_eq_m256i(r, e);
10655    }
10656
10657    #[simd_test(enable = "avx512f,avx512vl")]
10658    unsafe fn test_mm256_maskz_broadcastq_epi64() {
10659        let a = _mm_set_epi64x(17, 18);
10660        let r = _mm256_maskz_broadcastq_epi64(0, a);
10661        assert_eq_m256i(r, _mm256_setzero_si256());
10662        let r = _mm256_maskz_broadcastq_epi64(0b00001111, a);
10663        let e = _mm256_set1_epi64x(18);
10664        assert_eq_m256i(r, e);
10665    }
10666
10667    #[simd_test(enable = "avx512f,avx512vl")]
10668    unsafe fn test_mm_mask_broadcastq_epi64() {
10669        let src = _mm_set1_epi64x(18);
10670        let a = _mm_set_epi64x(17, 18);
10671        let r = _mm_mask_broadcastq_epi64(src, 0, a);
10672        assert_eq_m128i(r, src);
10673        let r = _mm_mask_broadcastq_epi64(src, 0b00000011, a);
10674        let e = _mm_set1_epi64x(18);
10675        assert_eq_m128i(r, e);
10676    }
10677
10678    #[simd_test(enable = "avx512f,avx512vl")]
10679    unsafe fn test_mm_maskz_broadcastq_epi64() {
10680        let a = _mm_set_epi64x(17, 18);
10681        let r = _mm_maskz_broadcastq_epi64(0, a);
10682        assert_eq_m128i(r, _mm_setzero_si128());
10683        let r = _mm_maskz_broadcastq_epi64(0b00000011, a);
10684        let e = _mm_set1_epi64x(18);
10685        assert_eq_m128i(r, e);
10686    }
10687
10688    #[simd_test(enable = "avx512f")]
10689    unsafe fn test_mm512_broadcastsd_pd() {
10690        let a = _mm_set_pd(17., 18.);
10691        let r = _mm512_broadcastsd_pd(a);
10692        let e = _mm512_set1_pd(18.);
10693        assert_eq_m512d(r, e);
10694    }
10695
10696    #[simd_test(enable = "avx512f")]
10697    unsafe fn test_mm512_mask_broadcastsd_pd() {
10698        let src = _mm512_set1_pd(18.);
10699        let a = _mm_set_pd(17., 18.);
10700        let r = _mm512_mask_broadcastsd_pd(src, 0, a);
10701        assert_eq_m512d(r, src);
10702        let r = _mm512_mask_broadcastsd_pd(src, 0b11111111, a);
10703        let e = _mm512_set1_pd(18.);
10704        assert_eq_m512d(r, e);
10705    }
10706
10707    #[simd_test(enable = "avx512f")]
10708    unsafe fn test_mm512_maskz_broadcastsd_pd() {
10709        let a = _mm_set_pd(17., 18.);
10710        let r = _mm512_maskz_broadcastsd_pd(0, a);
10711        assert_eq_m512d(r, _mm512_setzero_pd());
10712        let r = _mm512_maskz_broadcastsd_pd(0b00001111, a);
10713        let e = _mm512_set_pd(0., 0., 0., 0., 18., 18., 18., 18.);
10714        assert_eq_m512d(r, e);
10715    }
10716
10717    #[simd_test(enable = "avx512f,avx512vl")]
10718    unsafe fn test_mm256_mask_broadcastsd_pd() {
10719        let src = _mm256_set1_pd(18.);
10720        let a = _mm_set_pd(17., 18.);
10721        let r = _mm256_mask_broadcastsd_pd(src, 0, a);
10722        assert_eq_m256d(r, src);
10723        let r = _mm256_mask_broadcastsd_pd(src, 0b00001111, a);
10724        let e = _mm256_set1_pd(18.);
10725        assert_eq_m256d(r, e);
10726    }
10727
10728    #[simd_test(enable = "avx512f,avx512vl")]
10729    unsafe fn test_mm256_maskz_broadcastsd_pd() {
10730        let a = _mm_set_pd(17., 18.);
10731        let r = _mm256_maskz_broadcastsd_pd(0, a);
10732        assert_eq_m256d(r, _mm256_setzero_pd());
10733        let r = _mm256_maskz_broadcastsd_pd(0b00001111, a);
10734        let e = _mm256_set1_pd(18.);
10735        assert_eq_m256d(r, e);
10736    }
10737
10738    #[simd_test(enable = "avx512f")]
10739    unsafe fn test_mm512_broadcast_i64x4() {
10740        let a = _mm256_set_epi64x(17, 18, 19, 20);
10741        let r = _mm512_broadcast_i64x4(a);
10742        let e = _mm512_set_epi64(17, 18, 19, 20, 17, 18, 19, 20);
10743        assert_eq_m512i(r, e);
10744    }
10745
10746    #[simd_test(enable = "avx512f")]
10747    unsafe fn test_mm512_mask_broadcast_i64x4() {
10748        let src = _mm512_set1_epi64(18);
10749        let a = _mm256_set_epi64x(17, 18, 19, 20);
10750        let r = _mm512_mask_broadcast_i64x4(src, 0, a);
10751        assert_eq_m512i(r, src);
10752        let r = _mm512_mask_broadcast_i64x4(src, 0b11111111, a);
10753        let e = _mm512_set_epi64(17, 18, 19, 20, 17, 18, 19, 20);
10754        assert_eq_m512i(r, e);
10755    }
10756
10757    #[simd_test(enable = "avx512f")]
10758    unsafe fn test_mm512_maskz_broadcast_i64x4() {
10759        let a = _mm256_set_epi64x(17, 18, 19, 20);
10760        let r = _mm512_maskz_broadcast_i64x4(0, a);
10761        assert_eq_m512i(r, _mm512_setzero_si512());
10762        let r = _mm512_maskz_broadcast_i64x4(0b00001111, a);
10763        let e = _mm512_set_epi64(0, 0, 0, 0, 17, 18, 19, 20);
10764        assert_eq_m512i(r, e);
10765    }
10766
10767    #[simd_test(enable = "avx512f")]
10768    unsafe fn test_mm512_broadcast_f64x4() {
10769        let a = _mm256_set_pd(17., 18., 19., 20.);
10770        let r = _mm512_broadcast_f64x4(a);
10771        let e = _mm512_set_pd(17., 18., 19., 20., 17., 18., 19., 20.);
10772        assert_eq_m512d(r, e);
10773    }
10774
10775    #[simd_test(enable = "avx512f")]
10776    unsafe fn test_mm512_mask_broadcast_f64x4() {
10777        let src = _mm512_set1_pd(18.);
10778        let a = _mm256_set_pd(17., 18., 19., 20.);
10779        let r = _mm512_mask_broadcast_f64x4(src, 0, a);
10780        assert_eq_m512d(r, src);
10781        let r = _mm512_mask_broadcast_f64x4(src, 0b11111111, a);
10782        let e = _mm512_set_pd(17., 18., 19., 20., 17., 18., 19., 20.);
10783        assert_eq_m512d(r, e);
10784    }
10785
10786    #[simd_test(enable = "avx512f")]
10787    unsafe fn test_mm512_maskz_broadcast_f64x4() {
10788        let a = _mm256_set_pd(17., 18., 19., 20.);
10789        let r = _mm512_maskz_broadcast_f64x4(0, a);
10790        assert_eq_m512d(r, _mm512_setzero_pd());
10791        let r = _mm512_maskz_broadcast_f64x4(0b00001111, a);
10792        let e = _mm512_set_pd(0., 0., 0., 0., 17., 18., 19., 20.);
10793        assert_eq_m512d(r, e);
10794    }
10795
10796    #[simd_test(enable = "avx512f")]
10797    unsafe fn test_mm512_mask_blend_epi64() {
10798        let a = _mm512_set1_epi64(1);
10799        let b = _mm512_set1_epi64(2);
10800        let r = _mm512_mask_blend_epi64(0b11110000, a, b);
10801        let e = _mm512_set_epi64(2, 2, 2, 2, 1, 1, 1, 1);
10802        assert_eq_m512i(r, e);
10803    }
10804
10805    #[simd_test(enable = "avx512f,avx512vl")]
10806    unsafe fn test_mm256_mask_blend_epi64() {
10807        let a = _mm256_set1_epi64x(1);
10808        let b = _mm256_set1_epi64x(2);
10809        let r = _mm256_mask_blend_epi64(0b00001111, a, b);
10810        let e = _mm256_set1_epi64x(2);
10811        assert_eq_m256i(r, e);
10812    }
10813
10814    #[simd_test(enable = "avx512f,avx512vl")]
10815    unsafe fn test_mm_mask_blend_epi64() {
10816        let a = _mm_set1_epi64x(1);
10817        let b = _mm_set1_epi64x(2);
10818        let r = _mm_mask_blend_epi64(0b00000011, a, b);
10819        let e = _mm_set1_epi64x(2);
10820        assert_eq_m128i(r, e);
10821    }
10822
10823    #[simd_test(enable = "avx512f")]
10824    unsafe fn test_mm512_mask_blend_pd() {
10825        let a = _mm512_set1_pd(1.);
10826        let b = _mm512_set1_pd(2.);
10827        let r = _mm512_mask_blend_pd(0b11110000, a, b);
10828        let e = _mm512_set_pd(2., 2., 2., 2., 1., 1., 1., 1.);
10829        assert_eq_m512d(r, e);
10830    }
10831
10832    #[simd_test(enable = "avx512f,avx512vl")]
10833    unsafe fn test_mm256_mask_blend_pd() {
10834        let a = _mm256_set1_pd(1.);
10835        let b = _mm256_set1_pd(2.);
10836        let r = _mm256_mask_blend_pd(0b00001111, a, b);
10837        let e = _mm256_set1_pd(2.);
10838        assert_eq_m256d(r, e);
10839    }
10840
10841    #[simd_test(enable = "avx512f,avx512vl")]
10842    unsafe fn test_mm_mask_blend_pd() {
10843        let a = _mm_set1_pd(1.);
10844        let b = _mm_set1_pd(2.);
10845        let r = _mm_mask_blend_pd(0b00000011, a, b);
10846        let e = _mm_set1_pd(2.);
10847        assert_eq_m128d(r, e);
10848    }
10849
10850    #[simd_test(enable = "avx512f")]
10851    unsafe fn test_mm512_unpackhi_epi64() {
10852        let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10853        let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
10854        let r = _mm512_unpackhi_epi64(a, b);
10855        let e = _mm512_set_epi64(17, 1, 19, 3, 21, 5, 23, 7);
10856        assert_eq_m512i(r, e);
10857    }
10858
10859    #[simd_test(enable = "avx512f")]
10860    unsafe fn test_mm512_mask_unpackhi_epi64() {
10861        let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10862        let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
10863        let r = _mm512_mask_unpackhi_epi64(a, 0, a, b);
10864        assert_eq_m512i(r, a);
10865        let r = _mm512_mask_unpackhi_epi64(a, 0b11111111, a, b);
10866        let e = _mm512_set_epi64(17, 1, 19, 3, 21, 5, 23, 7);
10867        assert_eq_m512i(r, e);
10868    }
10869
10870    #[simd_test(enable = "avx512f")]
10871    unsafe fn test_mm512_maskz_unpackhi_epi64() {
10872        let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10873        let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
10874        let r = _mm512_maskz_unpackhi_epi64(0, a, b);
10875        assert_eq_m512i(r, _mm512_setzero_si512());
10876        let r = _mm512_maskz_unpackhi_epi64(0b00001111, a, b);
10877        let e = _mm512_set_epi64(0, 0, 0, 0, 21, 5, 23, 7);
10878        assert_eq_m512i(r, e);
10879    }
10880
10881    #[simd_test(enable = "avx512f,avx512vl")]
10882    unsafe fn test_mm256_mask_unpackhi_epi64() {
10883        let a = _mm256_set_epi64x(1, 2, 3, 4);
10884        let b = _mm256_set_epi64x(17, 18, 19, 20);
10885        let r = _mm256_mask_unpackhi_epi64(a, 0, a, b);
10886        assert_eq_m256i(r, a);
10887        let r = _mm256_mask_unpackhi_epi64(a, 0b00001111, a, b);
10888        let e = _mm256_set_epi64x(17, 1, 19, 3);
10889        assert_eq_m256i(r, e);
10890    }
10891
10892    #[simd_test(enable = "avx512f,avx512vl")]
10893    unsafe fn test_mm256_maskz_unpackhi_epi64() {
10894        let a = _mm256_set_epi64x(1, 2, 3, 4);
10895        let b = _mm256_set_epi64x(17, 18, 19, 20);
10896        let r = _mm256_maskz_unpackhi_epi64(0, a, b);
10897        assert_eq_m256i(r, _mm256_setzero_si256());
10898        let r = _mm256_maskz_unpackhi_epi64(0b00001111, a, b);
10899        let e = _mm256_set_epi64x(17, 1, 19, 3);
10900        assert_eq_m256i(r, e);
10901    }
10902
10903    #[simd_test(enable = "avx512f,avx512vl")]
10904    unsafe fn test_mm_mask_unpackhi_epi64() {
10905        let a = _mm_set_epi64x(1, 2);
10906        let b = _mm_set_epi64x(17, 18);
10907        let r = _mm_mask_unpackhi_epi64(a, 0, a, b);
10908        assert_eq_m128i(r, a);
10909        let r = _mm_mask_unpackhi_epi64(a, 0b00000011, a, b);
10910        let e = _mm_set_epi64x(17, 1);
10911        assert_eq_m128i(r, e);
10912    }
10913
10914    #[simd_test(enable = "avx512f,avx512vl")]
10915    unsafe fn test_mm_maskz_unpackhi_epi64() {
10916        let a = _mm_set_epi64x(1, 2);
10917        let b = _mm_set_epi64x(17, 18);
10918        let r = _mm_maskz_unpackhi_epi64(0, a, b);
10919        assert_eq_m128i(r, _mm_setzero_si128());
10920        let r = _mm_maskz_unpackhi_epi64(0b00000011, a, b);
10921        let e = _mm_set_epi64x(17, 1);
10922        assert_eq_m128i(r, e);
10923    }
10924
10925    #[simd_test(enable = "avx512f")]
10926    unsafe fn test_mm512_unpackhi_pd() {
10927        let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10928        let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
10929        let r = _mm512_unpackhi_pd(a, b);
10930        let e = _mm512_set_pd(17., 1., 19., 3., 21., 5., 23., 7.);
10931        assert_eq_m512d(r, e);
10932    }
10933
10934    #[simd_test(enable = "avx512f")]
10935    unsafe fn test_mm512_mask_unpackhi_pd() {
10936        let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10937        let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
10938        let r = _mm512_mask_unpackhi_pd(a, 0, a, b);
10939        assert_eq_m512d(r, a);
10940        let r = _mm512_mask_unpackhi_pd(a, 0b11111111, a, b);
10941        let e = _mm512_set_pd(17., 1., 19., 3., 21., 5., 23., 7.);
10942        assert_eq_m512d(r, e);
10943    }
10944
10945    #[simd_test(enable = "avx512f")]
10946    unsafe fn test_mm512_maskz_unpackhi_pd() {
10947        let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10948        let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
10949        let r = _mm512_maskz_unpackhi_pd(0, a, b);
10950        assert_eq_m512d(r, _mm512_setzero_pd());
10951        let r = _mm512_maskz_unpackhi_pd(0b00001111, a, b);
10952        let e = _mm512_set_pd(0., 0., 0., 0., 21., 5., 23., 7.);
10953        assert_eq_m512d(r, e);
10954    }
10955
10956    #[simd_test(enable = "avx512f,avx512vl")]
10957    unsafe fn test_mm256_mask_unpackhi_pd() {
10958        let a = _mm256_set_pd(1., 2., 3., 4.);
10959        let b = _mm256_set_pd(17., 18., 19., 20.);
10960        let r = _mm256_mask_unpackhi_pd(a, 0, a, b);
10961        assert_eq_m256d(r, a);
10962        let r = _mm256_mask_unpackhi_pd(a, 0b00001111, a, b);
10963        let e = _mm256_set_pd(17., 1., 19., 3.);
10964        assert_eq_m256d(r, e);
10965    }
10966
10967    #[simd_test(enable = "avx512f,avx512vl")]
10968    unsafe fn test_mm256_maskz_unpackhi_pd() {
10969        let a = _mm256_set_pd(1., 2., 3., 4.);
10970        let b = _mm256_set_pd(17., 18., 19., 20.);
10971        let r = _mm256_maskz_unpackhi_pd(0, a, b);
10972        assert_eq_m256d(r, _mm256_setzero_pd());
10973        let r = _mm256_maskz_unpackhi_pd(0b00001111, a, b);
10974        let e = _mm256_set_pd(17., 1., 19., 3.);
10975        assert_eq_m256d(r, e);
10976    }
10977
10978    #[simd_test(enable = "avx512f,avx512vl")]
10979    unsafe fn test_mm_mask_unpackhi_pd() {
10980        let a = _mm_set_pd(1., 2.);
10981        let b = _mm_set_pd(17., 18.);
10982        let r = _mm_mask_unpackhi_pd(a, 0, a, b);
10983        assert_eq_m128d(r, a);
10984        let r = _mm_mask_unpackhi_pd(a, 0b00000011, a, b);
10985        let e = _mm_set_pd(17., 1.);
10986        assert_eq_m128d(r, e);
10987    }
10988
10989    #[simd_test(enable = "avx512f,avx512vl")]
10990    unsafe fn test_mm_maskz_unpackhi_pd() {
10991        let a = _mm_set_pd(1., 2.);
10992        let b = _mm_set_pd(17., 18.);
10993        let r = _mm_maskz_unpackhi_pd(0, a, b);
10994        assert_eq_m128d(r, _mm_setzero_pd());
10995        let r = _mm_maskz_unpackhi_pd(0b00000011, a, b);
10996        let e = _mm_set_pd(17., 1.);
10997        assert_eq_m128d(r, e);
10998    }
10999
11000    #[simd_test(enable = "avx512f")]
11001    unsafe fn test_mm512_unpacklo_epi64() {
11002        let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11003        let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
11004        let r = _mm512_unpacklo_epi64(a, b);
11005        let e = _mm512_set_epi64(18, 2, 20, 4, 22, 6, 24, 8);
11006        assert_eq_m512i(r, e);
11007    }
11008
11009    #[simd_test(enable = "avx512f")]
11010    unsafe fn test_mm512_mask_unpacklo_epi64() {
11011        let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11012        let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
11013        let r = _mm512_mask_unpacklo_epi64(a, 0, a, b);
11014        assert_eq_m512i(r, a);
11015        let r = _mm512_mask_unpacklo_epi64(a, 0b11111111, a, b);
11016        let e = _mm512_set_epi64(18, 2, 20, 4, 22, 6, 24, 8);
11017        assert_eq_m512i(r, e);
11018    }
11019
11020    #[simd_test(enable = "avx512f")]
11021    unsafe fn test_mm512_maskz_unpacklo_epi64() {
11022        let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11023        let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
11024        let r = _mm512_maskz_unpacklo_epi64(0, a, b);
11025        assert_eq_m512i(r, _mm512_setzero_si512());
11026        let r = _mm512_maskz_unpacklo_epi64(0b00001111, a, b);
11027        let e = _mm512_set_epi64(0, 0, 0, 0, 22, 6, 24, 8);
11028        assert_eq_m512i(r, e);
11029    }
11030
11031    #[simd_test(enable = "avx512f,avx512vl")]
11032    unsafe fn test_mm256_mask_unpacklo_epi64() {
11033        let a = _mm256_set_epi64x(1, 2, 3, 4);
11034        let b = _mm256_set_epi64x(17, 18, 19, 20);
11035        let r = _mm256_mask_unpacklo_epi64(a, 0, a, b);
11036        assert_eq_m256i(r, a);
11037        let r = _mm256_mask_unpacklo_epi64(a, 0b00001111, a, b);
11038        let e = _mm256_set_epi64x(18, 2, 20, 4);
11039        assert_eq_m256i(r, e);
11040    }
11041
11042    #[simd_test(enable = "avx512f,avx512vl")]
11043    unsafe fn test_mm256_maskz_unpacklo_epi64() {
11044        let a = _mm256_set_epi64x(1, 2, 3, 4);
11045        let b = _mm256_set_epi64x(17, 18, 19, 20);
11046        let r = _mm256_maskz_unpacklo_epi64(0, a, b);
11047        assert_eq_m256i(r, _mm256_setzero_si256());
11048        let r = _mm256_maskz_unpacklo_epi64(0b00001111, a, b);
11049        let e = _mm256_set_epi64x(18, 2, 20, 4);
11050        assert_eq_m256i(r, e);
11051    }
11052
11053    #[simd_test(enable = "avx512f,avx512vl")]
11054    unsafe fn test_mm_mask_unpacklo_epi64() {
11055        let a = _mm_set_epi64x(1, 2);
11056        let b = _mm_set_epi64x(17, 18);
11057        let r = _mm_mask_unpacklo_epi64(a, 0, a, b);
11058        assert_eq_m128i(r, a);
11059        let r = _mm_mask_unpacklo_epi64(a, 0b00000011, a, b);
11060        let e = _mm_set_epi64x(18, 2);
11061        assert_eq_m128i(r, e);
11062    }
11063
11064    #[simd_test(enable = "avx512f,avx512vl")]
11065    unsafe fn test_mm_maskz_unpacklo_epi64() {
11066        let a = _mm_set_epi64x(1, 2);
11067        let b = _mm_set_epi64x(17, 18);
11068        let r = _mm_maskz_unpacklo_epi64(0, a, b);
11069        assert_eq_m128i(r, _mm_setzero_si128());
11070        let r = _mm_maskz_unpacklo_epi64(0b00000011, a, b);
11071        let e = _mm_set_epi64x(18, 2);
11072        assert_eq_m128i(r, e);
11073    }
11074
11075    #[simd_test(enable = "avx512f")]
11076    unsafe fn test_mm512_unpacklo_pd() {
11077        let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11078        let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
11079        let r = _mm512_unpacklo_pd(a, b);
11080        let e = _mm512_set_pd(18., 2., 20., 4., 22., 6., 24., 8.);
11081        assert_eq_m512d(r, e);
11082    }
11083
11084    #[simd_test(enable = "avx512f")]
11085    unsafe fn test_mm512_mask_unpacklo_pd() {
11086        let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11087        let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
11088        let r = _mm512_mask_unpacklo_pd(a, 0, a, b);
11089        assert_eq_m512d(r, a);
11090        let r = _mm512_mask_unpacklo_pd(a, 0b11111111, a, b);
11091        let e = _mm512_set_pd(18., 2., 20., 4., 22., 6., 24., 8.);
11092        assert_eq_m512d(r, e);
11093    }
11094
11095    #[simd_test(enable = "avx512f")]
11096    unsafe fn test_mm512_maskz_unpacklo_pd() {
11097        let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11098        let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
11099        let r = _mm512_maskz_unpacklo_pd(0, a, b);
11100        assert_eq_m512d(r, _mm512_setzero_pd());
11101        let r = _mm512_maskz_unpacklo_pd(0b00001111, a, b);
11102        let e = _mm512_set_pd(0., 0., 0., 0., 22., 6., 24., 8.);
11103        assert_eq_m512d(r, e);
11104    }
11105
11106    #[simd_test(enable = "avx512f,avx512vl")]
11107    unsafe fn test_mm256_mask_unpacklo_pd() {
11108        let a = _mm256_set_pd(1., 2., 3., 4.);
11109        let b = _mm256_set_pd(17., 18., 19., 20.);
11110        let r = _mm256_mask_unpacklo_pd(a, 0, a, b);
11111        assert_eq_m256d(r, a);
11112        let r = _mm256_mask_unpacklo_pd(a, 0b00001111, a, b);
11113        let e = _mm256_set_pd(18., 2., 20., 4.);
11114        assert_eq_m256d(r, e);
11115    }
11116
11117    #[simd_test(enable = "avx512f,avx512vl")]
11118    unsafe fn test_mm256_maskz_unpacklo_pd() {
11119        let a = _mm256_set_pd(1., 2., 3., 4.);
11120        let b = _mm256_set_pd(17., 18., 19., 20.);
11121        let r = _mm256_maskz_unpacklo_pd(0, a, b);
11122        assert_eq_m256d(r, _mm256_setzero_pd());
11123        let r = _mm256_maskz_unpacklo_pd(0b00001111, a, b);
11124        let e = _mm256_set_pd(18., 2., 20., 4.);
11125        assert_eq_m256d(r, e);
11126    }
11127
11128    #[simd_test(enable = "avx512f,avx512vl")]
11129    unsafe fn test_mm_mask_unpacklo_pd() {
11130        let a = _mm_set_pd(1., 2.);
11131        let b = _mm_set_pd(17., 18.);
11132        let r = _mm_mask_unpacklo_pd(a, 0, a, b);
11133        assert_eq_m128d(r, a);
11134        let r = _mm_mask_unpacklo_pd(a, 0b00000011, a, b);
11135        let e = _mm_set_pd(18., 2.);
11136        assert_eq_m128d(r, e);
11137    }
11138
11139    #[simd_test(enable = "avx512f,avx512vl")]
11140    unsafe fn test_mm_maskz_unpacklo_pd() {
11141        let a = _mm_set_pd(1., 2.);
11142        let b = _mm_set_pd(17., 18.);
11143        let r = _mm_maskz_unpacklo_pd(0, a, b);
11144        assert_eq_m128d(r, _mm_setzero_pd());
11145        let r = _mm_maskz_unpacklo_pd(0b00000011, a, b);
11146        let e = _mm_set_pd(18., 2.);
11147        assert_eq_m128d(r, e);
11148    }
11149
11150    #[simd_test(enable = "avx512f")]
11151    unsafe fn test_mm512_alignr_epi64() {
11152        let a = _mm512_set_epi64(8, 7, 6, 5, 4, 3, 2, 1);
11153        let b = _mm512_set_epi64(16, 15, 14, 13, 12, 11, 10, 9);
11154        let r = _mm512_alignr_epi64::<0>(a, b);
11155        assert_eq_m512i(r, b);
11156        let r = _mm512_alignr_epi64::<8>(a, b);
11157        assert_eq_m512i(r, b);
11158        let r = _mm512_alignr_epi64::<1>(a, b);
11159        let e = _mm512_set_epi64(1, 16, 15, 14, 13, 12, 11, 10);
11160        assert_eq_m512i(r, e);
11161    }
11162
11163    #[simd_test(enable = "avx512f")]
11164    unsafe fn test_mm512_mask_alignr_epi64() {
11165        let a = _mm512_set_epi64(8, 7, 6, 5, 4, 3, 2, 1);
11166        let b = _mm512_set_epi64(16, 15, 14, 13, 12, 11, 10, 9);
11167        let r = _mm512_mask_alignr_epi64::<1>(a, 0, a, b);
11168        assert_eq_m512i(r, a);
11169        let r = _mm512_mask_alignr_epi64::<1>(a, 0b11111111, a, b);
11170        let e = _mm512_set_epi64(1, 16, 15, 14, 13, 12, 11, 10);
11171        assert_eq_m512i(r, e);
11172    }
11173
11174    #[simd_test(enable = "avx512f")]
11175    unsafe fn test_mm512_maskz_alignr_epi64() {
11176        let a = _mm512_set_epi64(8, 7, 6, 5, 4, 3, 2, 1);
11177        let b = _mm512_set_epi64(16, 15, 14, 13, 12, 11, 10, 9);
11178        let r = _mm512_maskz_alignr_epi64::<1>(0, a, b);
11179        assert_eq_m512i(r, _mm512_setzero_si512());
11180        let r = _mm512_maskz_alignr_epi64::<1>(0b00001111, a, b);
11181        let e = _mm512_set_epi64(0, 0, 0, 0, 13, 12, 11, 10);
11182        assert_eq_m512i(r, e);
11183    }
11184
11185    #[simd_test(enable = "avx512f,avx512vl")]
11186    unsafe fn test_mm256_alignr_epi64() {
11187        let a = _mm256_set_epi64x(4, 3, 2, 1);
11188        let b = _mm256_set_epi64x(8, 7, 6, 5);
11189        let r = _mm256_alignr_epi64::<0>(a, b);
11190        let e = _mm256_set_epi64x(8, 7, 6, 5);
11191        assert_eq_m256i(r, e);
11192        let r = _mm256_alignr_epi64::<1>(a, b);
11193        let e = _mm256_set_epi64x(1, 8, 7, 6);
11194        assert_eq_m256i(r, e);
11195        let r = _mm256_alignr_epi64::<6>(a, b);
11196        let e = _mm256_set_epi64x(2, 1, 8, 7);
11197        assert_eq_m256i(r, e);
11198    }
11199
11200    #[simd_test(enable = "avx512f,avx512vl")]
11201    unsafe fn test_mm256_mask_alignr_epi64() {
11202        let a = _mm256_set_epi64x(4, 3, 2, 1);
11203        let b = _mm256_set_epi64x(8, 7, 6, 5);
11204        let r = _mm256_mask_alignr_epi64::<1>(a, 0, a, b);
11205        assert_eq_m256i(r, a);
11206        let r = _mm256_mask_alignr_epi64::<0>(a, 0b00001111, a, b);
11207        let e = _mm256_set_epi64x(8, 7, 6, 5);
11208        assert_eq_m256i(r, e);
11209    }
11210
11211    #[simd_test(enable = "avx512f,avx512vl")]
11212    unsafe fn test_mm256_maskz_alignr_epi64() {
11213        let a = _mm256_set_epi64x(4, 3, 2, 1);
11214        let b = _mm256_set_epi64x(8, 7, 6, 5);
11215        let r = _mm256_maskz_alignr_epi64::<1>(0, a, b);
11216        assert_eq_m256i(r, _mm256_setzero_si256());
11217        let r = _mm256_maskz_alignr_epi64::<0>(0b00001111, a, b);
11218        let e = _mm256_set_epi64x(8, 7, 6, 5);
11219        assert_eq_m256i(r, e);
11220    }
11221
11222    #[simd_test(enable = "avx512f,avx512vl")]
11223    unsafe fn test_mm_alignr_epi64() {
11224        let a = _mm_set_epi64x(2, 1);
11225        let b = _mm_set_epi64x(4, 3);
11226        let r = _mm_alignr_epi64::<0>(a, b);
11227        let e = _mm_set_epi64x(4, 3);
11228        assert_eq_m128i(r, e);
11229    }
11230
11231    #[simd_test(enable = "avx512f,avx512vl")]
11232    unsafe fn test_mm_mask_alignr_epi64() {
11233        let a = _mm_set_epi64x(2, 1);
11234        let b = _mm_set_epi64x(4, 3);
11235        let r = _mm_mask_alignr_epi64::<1>(a, 0, a, b);
11236        assert_eq_m128i(r, a);
11237        let r = _mm_mask_alignr_epi64::<0>(a, 0b00000011, a, b);
11238        let e = _mm_set_epi64x(4, 3);
11239        assert_eq_m128i(r, e);
11240    }
11241
11242    #[simd_test(enable = "avx512f,avx512vl")]
11243    unsafe fn test_mm_maskz_alignr_epi64() {
11244        let a = _mm_set_epi64x(2, 1);
11245        let b = _mm_set_epi64x(4, 3);
11246        let r = _mm_maskz_alignr_epi64::<1>(0, a, b);
11247        assert_eq_m128i(r, _mm_setzero_si128());
11248        let r = _mm_maskz_alignr_epi64::<0>(0b00000011, a, b);
11249        let e = _mm_set_epi64x(4, 3);
11250        assert_eq_m128i(r, e);
11251    }
11252
11253    #[simd_test(enable = "avx512f")]
11254    unsafe fn test_mm512_and_epi64() {
11255        let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11256        let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11257        let r = _mm512_and_epi64(a, b);
11258        let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11259        assert_eq_m512i(r, e);
11260    }
11261
11262    #[simd_test(enable = "avx512f")]
11263    unsafe fn test_mm512_mask_and_epi64() {
11264        let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11265        let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11266        let r = _mm512_mask_and_epi64(a, 0, a, b);
11267        assert_eq_m512i(r, a);
11268        let r = _mm512_mask_and_epi64(a, 0b01111111, a, b);
11269        let e = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11270        assert_eq_m512i(r, e);
11271    }
11272
11273    #[simd_test(enable = "avx512f")]
11274    unsafe fn test_mm512_maskz_and_epi64() {
11275        let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11276        let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11277        let r = _mm512_maskz_and_epi64(0, a, b);
11278        assert_eq_m512i(r, _mm512_setzero_si512());
11279        let r = _mm512_maskz_and_epi64(0b00001111, a, b);
11280        let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11281        assert_eq_m512i(r, e);
11282    }
11283
11284    #[simd_test(enable = "avx512f,avx512vl")]
11285    unsafe fn test_mm256_mask_and_epi64() {
11286        let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11287        let b = _mm256_set1_epi64x(1 << 0);
11288        let r = _mm256_mask_and_epi64(a, 0, a, b);
11289        assert_eq_m256i(r, a);
11290        let r = _mm256_mask_and_epi64(a, 0b00001111, a, b);
11291        let e = _mm256_set1_epi64x(1 << 0);
11292        assert_eq_m256i(r, e);
11293    }
11294
11295    #[simd_test(enable = "avx512f,avx512vl")]
11296    unsafe fn test_mm256_maskz_and_epi64() {
11297        let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11298        let b = _mm256_set1_epi64x(1 << 0);
11299        let r = _mm256_maskz_and_epi64(0, a, b);
11300        assert_eq_m256i(r, _mm256_setzero_si256());
11301        let r = _mm256_maskz_and_epi64(0b00001111, a, b);
11302        let e = _mm256_set1_epi64x(1 << 0);
11303        assert_eq_m256i(r, e);
11304    }
11305
11306    #[simd_test(enable = "avx512f,avx512vl")]
11307    unsafe fn test_mm_mask_and_epi64() {
11308        let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11309        let b = _mm_set1_epi64x(1 << 0);
11310        let r = _mm_mask_and_epi64(a, 0, a, b);
11311        assert_eq_m128i(r, a);
11312        let r = _mm_mask_and_epi64(a, 0b00000011, a, b);
11313        let e = _mm_set1_epi64x(1 << 0);
11314        assert_eq_m128i(r, e);
11315    }
11316
11317    #[simd_test(enable = "avx512f,avx512vl")]
11318    unsafe fn test_mm_maskz_and_epi64() {
11319        let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11320        let b = _mm_set1_epi64x(1 << 0);
11321        let r = _mm_maskz_and_epi64(0, a, b);
11322        assert_eq_m128i(r, _mm_setzero_si128());
11323        let r = _mm_maskz_and_epi64(0b00000011, a, b);
11324        let e = _mm_set1_epi64x(1 << 0);
11325        assert_eq_m128i(r, e);
11326    }
11327
11328    #[simd_test(enable = "avx512f")]
11329    unsafe fn test_mm512_and_si512() {
11330        let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11331        let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11332        let r = _mm512_and_epi64(a, b);
11333        let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11334        assert_eq_m512i(r, e);
11335    }
11336
11337    #[simd_test(enable = "avx512f")]
11338    unsafe fn test_mm512_or_epi64() {
11339        let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11340        let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11341        let r = _mm512_or_epi64(a, b);
11342        #[rustfmt::skip]
11343        let e = _mm512_set_epi64(
11344            1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0,
11345            0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3,
11346        );
11347        assert_eq_m512i(r, e);
11348    }
11349
11350    #[simd_test(enable = "avx512f")]
11351    unsafe fn test_mm512_mask_or_epi64() {
11352        let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11353        let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11354        let r = _mm512_mask_or_epi64(a, 0, a, b);
11355        assert_eq_m512i(r, a);
11356        let r = _mm512_mask_or_epi64(a, 0b11111111, a, b);
11357        #[rustfmt::skip]
11358        let e = _mm512_set_epi64(
11359            1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0,
11360            0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3,
11361        );
11362        assert_eq_m512i(r, e);
11363    }
11364
11365    #[simd_test(enable = "avx512f")]
11366    unsafe fn test_mm512_maskz_or_epi64() {
11367        let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11368        let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11369        let r = _mm512_maskz_or_epi64(0, a, b);
11370        assert_eq_m512i(r, _mm512_setzero_si512());
11371        let r = _mm512_maskz_or_epi64(0b00001111, a, b);
11372        let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11373        assert_eq_m512i(r, e);
11374    }
11375
11376    #[simd_test(enable = "avx512f,avx512vl")]
11377    unsafe fn test_mm256_or_epi64() {
11378        let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11379        let b = _mm256_set1_epi64x(1 << 13);
11380        let r = _mm256_or_epi64(a, b);
11381        let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11382        assert_eq_m256i(r, e);
11383    }
11384
11385    #[simd_test(enable = "avx512f,avx512vl")]
11386    unsafe fn test_mm256_mask_or_epi64() {
11387        let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11388        let b = _mm256_set1_epi64x(1 << 13);
11389        let r = _mm256_mask_or_epi64(a, 0, a, b);
11390        assert_eq_m256i(r, a);
11391        let r = _mm256_mask_or_epi64(a, 0b00001111, a, b);
11392        let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11393        assert_eq_m256i(r, e);
11394    }
11395
11396    #[simd_test(enable = "avx512f,avx512vl")]
11397    unsafe fn test_mm256_maskz_or_epi64() {
11398        let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11399        let b = _mm256_set1_epi64x(1 << 13);
11400        let r = _mm256_maskz_or_epi64(0, a, b);
11401        assert_eq_m256i(r, _mm256_setzero_si256());
11402        let r = _mm256_maskz_or_epi64(0b00001111, a, b);
11403        let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11404        assert_eq_m256i(r, e);
11405    }
11406
11407    #[simd_test(enable = "avx512f,avx512vl")]
11408    unsafe fn test_mm_or_epi64() {
11409        let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11410        let b = _mm_set1_epi64x(1 << 13);
11411        let r = _mm_or_epi64(a, b);
11412        let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11413        assert_eq_m128i(r, e);
11414    }
11415
11416    #[simd_test(enable = "avx512f,avx512vl")]
11417    unsafe fn test_mm_mask_or_epi64() {
11418        let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11419        let b = _mm_set1_epi64x(1 << 13);
11420        let r = _mm_mask_or_epi64(a, 0, a, b);
11421        assert_eq_m128i(r, a);
11422        let r = _mm_mask_or_epi64(a, 0b00000011, a, b);
11423        let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11424        assert_eq_m128i(r, e);
11425    }
11426
11427    #[simd_test(enable = "avx512f,avx512vl")]
11428    unsafe fn test_mm_maskz_or_epi64() {
11429        let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11430        let b = _mm_set1_epi64x(1 << 13);
11431        let r = _mm_maskz_or_epi64(0, a, b);
11432        assert_eq_m128i(r, _mm_setzero_si128());
11433        let r = _mm_maskz_or_epi64(0b00000011, a, b);
11434        let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11435        assert_eq_m128i(r, e);
11436    }
11437
11438    #[simd_test(enable = "avx512f")]
11439    unsafe fn test_mm512_or_si512() {
11440        let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11441        let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11442        let r = _mm512_or_epi64(a, b);
11443        #[rustfmt::skip]
11444        let e = _mm512_set_epi64(
11445            1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0,
11446            0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3,
11447        );
11448        assert_eq_m512i(r, e);
11449    }
11450
11451    #[simd_test(enable = "avx512f")]
11452    unsafe fn test_mm512_xor_epi64() {
11453        let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11454        let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11455        let r = _mm512_xor_epi64(a, b);
11456        let e = _mm512_set_epi64(1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0, 0, 0, 0, 0);
11457        assert_eq_m512i(r, e);
11458    }
11459
11460    #[simd_test(enable = "avx512f")]
11461    unsafe fn test_mm512_mask_xor_epi64() {
11462        let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11463        let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11464        let r = _mm512_mask_xor_epi64(a, 0, a, b);
11465        assert_eq_m512i(r, a);
11466        let r = _mm512_mask_xor_epi64(a, 0b11111111, a, b);
11467        let e = _mm512_set_epi64(1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0, 0, 0, 0, 0);
11468        assert_eq_m512i(r, e);
11469    }
11470
11471    #[simd_test(enable = "avx512f")]
11472    unsafe fn test_mm512_maskz_xor_epi64() {
11473        let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11474        let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11475        let r = _mm512_maskz_xor_epi64(0, a, b);
11476        assert_eq_m512i(r, _mm512_setzero_si512());
11477        let r = _mm512_maskz_xor_epi64(0b00001111, a, b);
11478        let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 0);
11479        assert_eq_m512i(r, e);
11480    }
11481
11482    #[simd_test(enable = "avx512f,avx512vl")]
11483    unsafe fn test_mm256_xor_epi64() {
11484        let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11485        let b = _mm256_set1_epi64x(1 << 13);
11486        let r = _mm256_xor_epi64(a, b);
11487        let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11488        assert_eq_m256i(r, e);
11489    }
11490
11491    #[simd_test(enable = "avx512f,avx512vl")]
11492    unsafe fn test_mm256_mask_xor_epi64() {
11493        let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11494        let b = _mm256_set1_epi64x(1 << 13);
11495        let r = _mm256_mask_xor_epi64(a, 0, a, b);
11496        assert_eq_m256i(r, a);
11497        let r = _mm256_mask_xor_epi64(a, 0b00001111, a, b);
11498        let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11499        assert_eq_m256i(r, e);
11500    }
11501
11502    #[simd_test(enable = "avx512f,avx512vl")]
11503    unsafe fn test_mm256_maskz_xor_epi64() {
11504        let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11505        let b = _mm256_set1_epi64x(1 << 13);
11506        let r = _mm256_maskz_xor_epi64(0, a, b);
11507        assert_eq_m256i(r, _mm256_setzero_si256());
11508        let r = _mm256_maskz_xor_epi64(0b00001111, a, b);
11509        let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11510        assert_eq_m256i(r, e);
11511    }
11512
11513    #[simd_test(enable = "avx512f,avx512vl")]
11514    unsafe fn test_mm_xor_epi64() {
11515        let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11516        let b = _mm_set1_epi64x(1 << 13);
11517        let r = _mm_xor_epi64(a, b);
11518        let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11519        assert_eq_m128i(r, e);
11520    }
11521
11522    #[simd_test(enable = "avx512f,avx512vl")]
11523    unsafe fn test_mm_mask_xor_epi64() {
11524        let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11525        let b = _mm_set1_epi64x(1 << 13);
11526        let r = _mm_mask_xor_epi64(a, 0, a, b);
11527        assert_eq_m128i(r, a);
11528        let r = _mm_mask_xor_epi64(a, 0b00000011, a, b);
11529        let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11530        assert_eq_m128i(r, e);
11531    }
11532
11533    #[simd_test(enable = "avx512f,avx512vl")]
11534    unsafe fn test_mm_maskz_xor_epi64() {
11535        let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11536        let b = _mm_set1_epi64x(1 << 13);
11537        let r = _mm_maskz_xor_epi64(0, a, b);
11538        assert_eq_m128i(r, _mm_setzero_si128());
11539        let r = _mm_maskz_xor_epi64(0b00000011, a, b);
11540        let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11541        assert_eq_m128i(r, e);
11542    }
11543
11544    #[simd_test(enable = "avx512f")]
11545    unsafe fn test_mm512_xor_si512() {
11546        let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11547        let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11548        let r = _mm512_xor_epi64(a, b);
11549        let e = _mm512_set_epi64(1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0, 0, 0, 0, 0);
11550        assert_eq_m512i(r, e);
11551    }
11552
11553    #[simd_test(enable = "avx512f")]
11554    unsafe fn test_mm512_andnot_epi64() {
11555        let a = _mm512_set1_epi64(0);
11556        let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
11557        let r = _mm512_andnot_epi64(a, b);
11558        let e = _mm512_set1_epi64(1 << 3 | 1 << 4);
11559        assert_eq_m512i(r, e);
11560    }
11561
11562    #[simd_test(enable = "avx512f")]
11563    unsafe fn test_mm512_mask_andnot_epi64() {
11564        let a = _mm512_set1_epi64(1 << 1 | 1 << 2);
11565        let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
11566        let r = _mm512_mask_andnot_epi64(a, 0, a, b);
11567        assert_eq_m512i(r, a);
11568        let r = _mm512_mask_andnot_epi64(a, 0b11111111, a, b);
11569        let e = _mm512_set1_epi64(1 << 3 | 1 << 4);
11570        assert_eq_m512i(r, e);
11571    }
11572
11573    #[simd_test(enable = "avx512f")]
11574    unsafe fn test_mm512_maskz_andnot_epi64() {
11575        let a = _mm512_set1_epi64(1 << 1 | 1 << 2);
11576        let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
11577        let r = _mm512_maskz_andnot_epi64(0, a, b);
11578        assert_eq_m512i(r, _mm512_setzero_si512());
11579        let r = _mm512_maskz_andnot_epi64(0b00001111, a, b);
11580        #[rustfmt::skip]
11581        let e = _mm512_set_epi64(
11582            0, 0, 0, 0,
11583            1 << 3 | 1 << 4, 1 << 3 | 1 << 4, 1 << 3 | 1 << 4, 1 << 3 | 1 << 4,
11584        );
11585        assert_eq_m512i(r, e);
11586    }
11587
11588    #[simd_test(enable = "avx512f,avx512vl")]
11589    unsafe fn test_mm256_mask_andnot_epi64() {
11590        let a = _mm256_set1_epi64x(1 << 1 | 1 << 2);
11591        let b = _mm256_set1_epi64x(1 << 3 | 1 << 4);
11592        let r = _mm256_mask_andnot_epi64(a, 0, a, b);
11593        assert_eq_m256i(r, a);
11594        let r = _mm256_mask_andnot_epi64(a, 0b00001111, a, b);
11595        let e = _mm256_set1_epi64x(1 << 3 | 1 << 4);
11596        assert_eq_m256i(r, e);
11597    }
11598
11599    #[simd_test(enable = "avx512f,avx512vl")]
11600    unsafe fn test_mm256_maskz_andnot_epi64() {
11601        let a = _mm256_set1_epi64x(1 << 1 | 1 << 2);
11602        let b = _mm256_set1_epi64x(1 << 3 | 1 << 4);
11603        let r = _mm256_maskz_andnot_epi64(0, a, b);
11604        assert_eq_m256i(r, _mm256_setzero_si256());
11605        let r = _mm256_maskz_andnot_epi64(0b00001111, a, b);
11606        let e = _mm256_set1_epi64x(1 << 3 | 1 << 4);
11607        assert_eq_m256i(r, e);
11608    }
11609
11610    #[simd_test(enable = "avx512f,avx512vl")]
11611    unsafe fn test_mm_mask_andnot_epi64() {
11612        let a = _mm_set1_epi64x(1 << 1 | 1 << 2);
11613        let b = _mm_set1_epi64x(1 << 3 | 1 << 4);
11614        let r = _mm_mask_andnot_epi64(a, 0, a, b);
11615        assert_eq_m128i(r, a);
11616        let r = _mm_mask_andnot_epi64(a, 0b00000011, a, b);
11617        let e = _mm_set1_epi64x(1 << 3 | 1 << 4);
11618        assert_eq_m128i(r, e);
11619    }
11620
11621    #[simd_test(enable = "avx512f,avx512vl")]
11622    unsafe fn test_mm_maskz_andnot_epi64() {
11623        let a = _mm_set1_epi64x(1 << 1 | 1 << 2);
11624        let b = _mm_set1_epi64x(1 << 3 | 1 << 4);
11625        let r = _mm_maskz_andnot_epi64(0, a, b);
11626        assert_eq_m128i(r, _mm_setzero_si128());
11627        let r = _mm_maskz_andnot_epi64(0b00000011, a, b);
11628        let e = _mm_set1_epi64x(1 << 3 | 1 << 4);
11629        assert_eq_m128i(r, e);
11630    }
11631
11632    #[simd_test(enable = "avx512f")]
11633    unsafe fn test_mm512_andnot_si512() {
11634        let a = _mm512_set1_epi64(0);
11635        let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
11636        let r = _mm512_andnot_si512(a, b);
11637        let e = _mm512_set1_epi64(1 << 3 | 1 << 4);
11638        assert_eq_m512i(r, e);
11639    }
11640
11641    #[simd_test(enable = "avx512f")]
11642    unsafe fn test_mm512_reduce_add_epi64() {
11643        let a = _mm512_set1_epi64(1);
11644        let e: i64 = _mm512_reduce_add_epi64(a);
11645        assert_eq!(8, e);
11646    }
11647
11648    #[simd_test(enable = "avx512f")]
11649    unsafe fn test_mm512_mask_reduce_add_epi64() {
11650        let a = _mm512_set1_epi64(1);
11651        let e: i64 = _mm512_mask_reduce_add_epi64(0b11110000, a);
11652        assert_eq!(4, e);
11653    }
11654
11655    #[simd_test(enable = "avx512f")]
11656    unsafe fn test_mm512_reduce_add_pd() {
11657        let a = _mm512_set1_pd(1.);
11658        let e: f64 = _mm512_reduce_add_pd(a);
11659        assert_eq!(8., e);
11660    }
11661
11662    #[simd_test(enable = "avx512f")]
11663    unsafe fn test_mm512_mask_reduce_add_pd() {
11664        let a = _mm512_set1_pd(1.);
11665        let e: f64 = _mm512_mask_reduce_add_pd(0b11110000, a);
11666        assert_eq!(4., e);
11667    }
11668
11669    #[simd_test(enable = "avx512f")]
11670    unsafe fn test_mm512_reduce_mul_epi64() {
11671        let a = _mm512_set1_epi64(2);
11672        let e: i64 = _mm512_reduce_mul_epi64(a);
11673        assert_eq!(256, e);
11674    }
11675
11676    #[simd_test(enable = "avx512f")]
11677    unsafe fn test_mm512_mask_reduce_mul_epi64() {
11678        let a = _mm512_set1_epi64(2);
11679        let e: i64 = _mm512_mask_reduce_mul_epi64(0b11110000, a);
11680        assert_eq!(16, e);
11681    }
11682
11683    #[simd_test(enable = "avx512f")]
11684    unsafe fn test_mm512_reduce_mul_pd() {
11685        let a = _mm512_set1_pd(2.);
11686        let e: f64 = _mm512_reduce_mul_pd(a);
11687        assert_eq!(256., e);
11688    }
11689
11690    #[simd_test(enable = "avx512f")]
11691    unsafe fn test_mm512_mask_reduce_mul_pd() {
11692        let a = _mm512_set1_pd(2.);
11693        let e: f64 = _mm512_mask_reduce_mul_pd(0b11110000, a);
11694        assert_eq!(16., e);
11695    }
11696
11697    #[simd_test(enable = "avx512f")]
11698    unsafe fn test_mm512_reduce_max_epi64() {
11699        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11700        let e: i64 = _mm512_reduce_max_epi64(a);
11701        assert_eq!(7, e);
11702    }
11703
11704    #[simd_test(enable = "avx512f")]
11705    unsafe fn test_mm512_mask_reduce_max_epi64() {
11706        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11707        let e: i64 = _mm512_mask_reduce_max_epi64(0b11110000, a);
11708        assert_eq!(3, e);
11709    }
11710
11711    #[simd_test(enable = "avx512f")]
11712    unsafe fn test_mm512_reduce_max_epu64() {
11713        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11714        let e: u64 = _mm512_reduce_max_epu64(a);
11715        assert_eq!(7, e);
11716    }
11717
11718    #[simd_test(enable = "avx512f")]
11719    unsafe fn test_mm512_mask_reduce_max_epu64() {
11720        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11721        let e: u64 = _mm512_mask_reduce_max_epu64(0b11110000, a);
11722        assert_eq!(3, e);
11723    }
11724
11725    #[simd_test(enable = "avx512f")]
11726    unsafe fn test_mm512_reduce_max_pd() {
11727        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11728        let e: f64 = _mm512_reduce_max_pd(a);
11729        assert_eq!(7., e);
11730    }
11731
11732    #[simd_test(enable = "avx512f")]
11733    unsafe fn test_mm512_mask_reduce_max_pd() {
11734        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11735        let e: f64 = _mm512_mask_reduce_max_pd(0b11110000, a);
11736        assert_eq!(3., e);
11737    }
11738
11739    #[simd_test(enable = "avx512f")]
11740    unsafe fn test_mm512_reduce_min_epi64() {
11741        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11742        let e: i64 = _mm512_reduce_min_epi64(a);
11743        assert_eq!(0, e);
11744    }
11745
11746    #[simd_test(enable = "avx512f")]
11747    unsafe fn test_mm512_mask_reduce_min_epi64() {
11748        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11749        let e: i64 = _mm512_mask_reduce_min_epi64(0b11110000, a);
11750        assert_eq!(0, e);
11751    }
11752
11753    #[simd_test(enable = "avx512f")]
11754    unsafe fn test_mm512_reduce_min_epu64() {
11755        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11756        let e: u64 = _mm512_reduce_min_epu64(a);
11757        assert_eq!(0, e);
11758    }
11759
11760    #[simd_test(enable = "avx512f")]
11761    unsafe fn test_mm512_mask_reduce_min_epu64() {
11762        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11763        let e: u64 = _mm512_mask_reduce_min_epu64(0b11110000, a);
11764        assert_eq!(0, e);
11765    }
11766
11767    #[simd_test(enable = "avx512f")]
11768    unsafe fn test_mm512_reduce_min_pd() {
11769        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11770        let e: f64 = _mm512_reduce_min_pd(a);
11771        assert_eq!(0., e);
11772    }
11773
11774    #[simd_test(enable = "avx512f")]
11775    unsafe fn test_mm512_mask_reduce_min_pd() {
11776        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11777        let e: f64 = _mm512_mask_reduce_min_pd(0b11110000, a);
11778        assert_eq!(0., e);
11779    }
11780
11781    #[simd_test(enable = "avx512f")]
11782    unsafe fn test_mm512_reduce_and_epi64() {
11783        let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
11784        let e: i64 = _mm512_reduce_and_epi64(a);
11785        assert_eq!(0, e);
11786    }
11787
11788    #[simd_test(enable = "avx512f")]
11789    unsafe fn test_mm512_mask_reduce_and_epi64() {
11790        let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
11791        let e: i64 = _mm512_mask_reduce_and_epi64(0b11110000, a);
11792        assert_eq!(1, e);
11793    }
11794
11795    #[simd_test(enable = "avx512f")]
11796    unsafe fn test_mm512_reduce_or_epi64() {
11797        let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
11798        let e: i64 = _mm512_reduce_or_epi64(a);
11799        assert_eq!(3, e);
11800    }
11801
11802    #[simd_test(enable = "avx512f")]
11803    unsafe fn test_mm512_mask_reduce_or_epi64() {
11804        let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
11805        let e: i64 = _mm512_mask_reduce_or_epi64(0b11110000, a);
11806        assert_eq!(1, e);
11807    }
11808
11809    #[simd_test(enable = "avx512f")]
11810    unsafe fn test_mm512_extractf64x4_pd() {
11811        let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11812        let r = _mm512_extractf64x4_pd::<1>(a);
11813        let e = _mm256_setr_pd(5., 6., 7., 8.);
11814        assert_eq_m256d(r, e);
11815    }
11816
11817    #[simd_test(enable = "avx512f")]
11818    unsafe fn test_mm512_mask_extractf64x4_pd() {
11819        let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11820        let src = _mm256_set1_pd(100.);
11821        let r = _mm512_mask_extractf64x4_pd::<1>(src, 0, a);
11822        assert_eq_m256d(r, src);
11823        let r = _mm512_mask_extractf64x4_pd::<1>(src, 0b11111111, a);
11824        let e = _mm256_setr_pd(5., 6., 7., 8.);
11825        assert_eq_m256d(r, e);
11826    }
11827
11828    #[simd_test(enable = "avx512f")]
11829    unsafe fn test_mm512_maskz_extractf64x4_pd() {
11830        let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11831        let r = _mm512_maskz_extractf64x4_pd::<1>(0, a);
11832        assert_eq_m256d(r, _mm256_setzero_pd());
11833        let r = _mm512_maskz_extractf64x4_pd::<1>(0b00000001, a);
11834        let e = _mm256_setr_pd(5., 0., 0., 0.);
11835        assert_eq_m256d(r, e);
11836    }
11837
11838    #[simd_test(enable = "avx512f")]
11839    unsafe fn test_mm512_extracti64x4_epi64() {
11840        let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11841        let r = _mm512_extracti64x4_epi64::<0x1>(a);
11842        let e = _mm256_setr_epi64x(5, 6, 7, 8);
11843        assert_eq_m256i(r, e);
11844    }
11845
11846    #[simd_test(enable = "avx512f")]
11847    unsafe fn test_mm512_mask_extracti64x4_epi64() {
11848        let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11849        let src = _mm256_set1_epi64x(100);
11850        let r = _mm512_mask_extracti64x4_epi64::<0x1>(src, 0, a);
11851        assert_eq_m256i(r, src);
11852        let r = _mm512_mask_extracti64x4_epi64::<0x1>(src, 0b11111111, a);
11853        let e = _mm256_setr_epi64x(5, 6, 7, 8);
11854        assert_eq_m256i(r, e);
11855    }
11856
11857    #[simd_test(enable = "avx512f")]
11858    unsafe fn test_mm512_maskz_extracti64x4_epi64() {
11859        let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11860        let r = _mm512_maskz_extracti64x4_epi64::<0x1>(0, a);
11861        assert_eq_m256i(r, _mm256_setzero_si256());
11862        let r = _mm512_maskz_extracti64x4_epi64::<0x1>(0b00000001, a);
11863        let e = _mm256_setr_epi64x(5, 0, 0, 0);
11864        assert_eq_m256i(r, e);
11865    }
11866
11867    #[simd_test(enable = "avx512f")]
11868    unsafe fn test_mm512_mask_compress_epi64() {
11869        let src = _mm512_set1_epi64(200);
11870        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11871        let r = _mm512_mask_compress_epi64(src, 0, a);
11872        assert_eq_m512i(r, src);
11873        let r = _mm512_mask_compress_epi64(src, 0b01010101, a);
11874        let e = _mm512_set_epi64(200, 200, 200, 200, 1, 3, 5, 7);
11875        assert_eq_m512i(r, e);
11876    }
11877
11878    #[simd_test(enable = "avx512f")]
11879    unsafe fn test_mm512_maskz_compress_epi64() {
11880        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11881        let r = _mm512_maskz_compress_epi64(0, a);
11882        assert_eq_m512i(r, _mm512_setzero_si512());
11883        let r = _mm512_maskz_compress_epi64(0b01010101, a);
11884        let e = _mm512_set_epi64(0, 0, 0, 0, 1, 3, 5, 7);
11885        assert_eq_m512i(r, e);
11886    }
11887
11888    #[simd_test(enable = "avx512f,avx512vl")]
11889    unsafe fn test_mm256_mask_compress_epi64() {
11890        let src = _mm256_set1_epi64x(200);
11891        let a = _mm256_set_epi64x(0, 1, 2, 3);
11892        let r = _mm256_mask_compress_epi64(src, 0, a);
11893        assert_eq_m256i(r, src);
11894        let r = _mm256_mask_compress_epi64(src, 0b00000101, a);
11895        let e = _mm256_set_epi64x(200, 200, 1, 3);
11896        assert_eq_m256i(r, e);
11897    }
11898
11899    #[simd_test(enable = "avx512f,avx512vl")]
11900    unsafe fn test_mm256_maskz_compress_epi64() {
11901        let a = _mm256_set_epi64x(0, 1, 2, 3);
11902        let r = _mm256_maskz_compress_epi64(0, a);
11903        assert_eq_m256i(r, _mm256_setzero_si256());
11904        let r = _mm256_maskz_compress_epi64(0b00000101, a);
11905        let e = _mm256_set_epi64x(0, 0, 1, 3);
11906        assert_eq_m256i(r, e);
11907    }
11908
11909    #[simd_test(enable = "avx512f,avx512vl")]
11910    unsafe fn test_mm_mask_compress_epi64() {
11911        let src = _mm_set1_epi64x(200);
11912        let a = _mm_set_epi64x(0, 1);
11913        let r = _mm_mask_compress_epi64(src, 0, a);
11914        assert_eq_m128i(r, src);
11915        let r = _mm_mask_compress_epi64(src, 0b00000001, a);
11916        let e = _mm_set_epi64x(200, 1);
11917        assert_eq_m128i(r, e);
11918    }
11919
11920    #[simd_test(enable = "avx512f,avx512vl")]
11921    unsafe fn test_mm_maskz_compress_epi64() {
11922        let a = _mm_set_epi64x(0, 1);
11923        let r = _mm_maskz_compress_epi64(0, a);
11924        assert_eq_m128i(r, _mm_setzero_si128());
11925        let r = _mm_maskz_compress_epi64(0b00000001, a);
11926        let e = _mm_set_epi64x(0, 1);
11927        assert_eq_m128i(r, e);
11928    }
11929
11930    #[simd_test(enable = "avx512f")]
11931    unsafe fn test_mm512_mask_compress_pd() {
11932        let src = _mm512_set1_pd(200.);
11933        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11934        let r = _mm512_mask_compress_pd(src, 0, a);
11935        assert_eq_m512d(r, src);
11936        let r = _mm512_mask_compress_pd(src, 0b01010101, a);
11937        let e = _mm512_set_pd(200., 200., 200., 200., 1., 3., 5., 7.);
11938        assert_eq_m512d(r, e);
11939    }
11940
11941    #[simd_test(enable = "avx512f")]
11942    unsafe fn test_mm512_maskz_compress_pd() {
11943        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11944        let r = _mm512_maskz_compress_pd(0, a);
11945        assert_eq_m512d(r, _mm512_setzero_pd());
11946        let r = _mm512_maskz_compress_pd(0b01010101, a);
11947        let e = _mm512_set_pd(0., 0., 0., 0., 1., 3., 5., 7.);
11948        assert_eq_m512d(r, e);
11949    }
11950
11951    #[simd_test(enable = "avx512f,avx512vl")]
11952    unsafe fn test_mm256_mask_compress_pd() {
11953        let src = _mm256_set1_pd(200.);
11954        let a = _mm256_set_pd(0., 1., 2., 3.);
11955        let r = _mm256_mask_compress_pd(src, 0, a);
11956        assert_eq_m256d(r, src);
11957        let r = _mm256_mask_compress_pd(src, 0b00000101, a);
11958        let e = _mm256_set_pd(200., 200., 1., 3.);
11959        assert_eq_m256d(r, e);
11960    }
11961
11962    #[simd_test(enable = "avx512f,avx512vl")]
11963    unsafe fn test_mm256_maskz_compress_pd() {
11964        let a = _mm256_set_pd(0., 1., 2., 3.);
11965        let r = _mm256_maskz_compress_pd(0, a);
11966        assert_eq_m256d(r, _mm256_setzero_pd());
11967        let r = _mm256_maskz_compress_pd(0b00000101, a);
11968        let e = _mm256_set_pd(0., 0., 1., 3.);
11969        assert_eq_m256d(r, e);
11970    }
11971
11972    #[simd_test(enable = "avx512f,avx512vl")]
11973    unsafe fn test_mm_mask_compress_pd() {
11974        let src = _mm_set1_pd(200.);
11975        let a = _mm_set_pd(0., 1.);
11976        let r = _mm_mask_compress_pd(src, 0, a);
11977        assert_eq_m128d(r, src);
11978        let r = _mm_mask_compress_pd(src, 0b00000001, a);
11979        let e = _mm_set_pd(200., 1.);
11980        assert_eq_m128d(r, e);
11981    }
11982
11983    #[simd_test(enable = "avx512f,avx512vl")]
11984    unsafe fn test_mm_maskz_compress_pd() {
11985        let a = _mm_set_pd(0., 1.);
11986        let r = _mm_maskz_compress_pd(0, a);
11987        assert_eq_m128d(r, _mm_setzero_pd());
11988        let r = _mm_maskz_compress_pd(0b00000001, a);
11989        let e = _mm_set_pd(0., 1.);
11990        assert_eq_m128d(r, e);
11991    }
11992
11993    #[simd_test(enable = "avx512f")]
11994    unsafe fn test_mm512_mask_expand_epi64() {
11995        let src = _mm512_set1_epi64(200);
11996        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11997        let r = _mm512_mask_expand_epi64(src, 0, a);
11998        assert_eq_m512i(r, src);
11999        let r = _mm512_mask_expand_epi64(src, 0b01010101, a);
12000        let e = _mm512_set_epi64(200, 4, 200, 5, 200, 6, 200, 7);
12001        assert_eq_m512i(r, e);
12002    }
12003
12004    #[simd_test(enable = "avx512f")]
12005    unsafe fn test_mm512_maskz_expand_epi64() {
12006        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
12007        let r = _mm512_maskz_expand_epi64(0, a);
12008        assert_eq_m512i(r, _mm512_setzero_si512());
12009        let r = _mm512_maskz_expand_epi64(0b01010101, a);
12010        let e = _mm512_set_epi64(0, 4, 0, 5, 0, 6, 0, 7);
12011        assert_eq_m512i(r, e);
12012    }
12013
12014    #[simd_test(enable = "avx512f,avx512vl")]
12015    unsafe fn test_mm256_mask_expand_epi64() {
12016        let src = _mm256_set1_epi64x(200);
12017        let a = _mm256_set_epi64x(0, 1, 2, 3);
12018        let r = _mm256_mask_expand_epi64(src, 0, a);
12019        assert_eq_m256i(r, src);
12020        let r = _mm256_mask_expand_epi64(src, 0b00000101, a);
12021        let e = _mm256_set_epi64x(200, 2, 200, 3);
12022        assert_eq_m256i(r, e);
12023    }
12024
12025    #[simd_test(enable = "avx512f,avx512vl")]
12026    unsafe fn test_mm256_maskz_expand_epi64() {
12027        let a = _mm256_set_epi64x(0, 1, 2, 3);
12028        let r = _mm256_maskz_expand_epi64(0, a);
12029        assert_eq_m256i(r, _mm256_setzero_si256());
12030        let r = _mm256_maskz_expand_epi64(0b00000101, a);
12031        let e = _mm256_set_epi64x(0, 2, 0, 3);
12032        assert_eq_m256i(r, e);
12033    }
12034
12035    #[simd_test(enable = "avx512f,avx512vl")]
12036    unsafe fn test_mm_mask_expand_epi64() {
12037        let src = _mm_set1_epi64x(200);
12038        let a = _mm_set_epi64x(0, 1);
12039        let r = _mm_mask_expand_epi64(src, 0, a);
12040        assert_eq_m128i(r, src);
12041        let r = _mm_mask_expand_epi64(src, 0b00000001, a);
12042        let e = _mm_set_epi64x(200, 1);
12043        assert_eq_m128i(r, e);
12044    }
12045
12046    #[simd_test(enable = "avx512f,avx512vl")]
12047    unsafe fn test_mm_maskz_expand_epi64() {
12048        let a = _mm_set_epi64x(0, 1);
12049        let r = _mm_maskz_expand_epi64(0, a);
12050        assert_eq_m128i(r, _mm_setzero_si128());
12051        let r = _mm_maskz_expand_epi64(0b00000001, a);
12052        let e = _mm_set_epi64x(0, 1);
12053        assert_eq_m128i(r, e);
12054    }
12055
12056    #[simd_test(enable = "avx512f")]
12057    unsafe fn test_mm512_mask_expand_pd() {
12058        let src = _mm512_set1_pd(200.);
12059        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
12060        let r = _mm512_mask_expand_pd(src, 0, a);
12061        assert_eq_m512d(r, src);
12062        let r = _mm512_mask_expand_pd(src, 0b01010101, a);
12063        let e = _mm512_set_pd(200., 4., 200., 5., 200., 6., 200., 7.);
12064        assert_eq_m512d(r, e);
12065    }
12066
12067    #[simd_test(enable = "avx512f")]
12068    unsafe fn test_mm512_maskz_expand_pd() {
12069        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
12070        let r = _mm512_maskz_expand_pd(0, a);
12071        assert_eq_m512d(r, _mm512_setzero_pd());
12072        let r = _mm512_maskz_expand_pd(0b01010101, a);
12073        let e = _mm512_set_pd(0., 4., 0., 5., 0., 6., 0., 7.);
12074        assert_eq_m512d(r, e);
12075    }
12076
12077    #[simd_test(enable = "avx512f,avx512vl")]
12078    unsafe fn test_mm256_mask_expand_pd() {
12079        let src = _mm256_set1_pd(200.);
12080        let a = _mm256_set_pd(0., 1., 2., 3.);
12081        let r = _mm256_mask_expand_pd(src, 0, a);
12082        assert_eq_m256d(r, src);
12083        let r = _mm256_mask_expand_pd(src, 0b00000101, a);
12084        let e = _mm256_set_pd(200., 2., 200., 3.);
12085        assert_eq_m256d(r, e);
12086    }
12087
12088    #[simd_test(enable = "avx512f,avx512vl")]
12089    unsafe fn test_mm256_maskz_expand_pd() {
12090        let a = _mm256_set_pd(0., 1., 2., 3.);
12091        let r = _mm256_maskz_expand_pd(0, a);
12092        assert_eq_m256d(r, _mm256_setzero_pd());
12093        let r = _mm256_maskz_expand_pd(0b00000101, a);
12094        let e = _mm256_set_pd(0., 2., 0., 3.);
12095        assert_eq_m256d(r, e);
12096    }
12097
12098    #[simd_test(enable = "avx512f,avx512vl")]
12099    unsafe fn test_mm_mask_expand_pd() {
12100        let src = _mm_set1_pd(200.);
12101        let a = _mm_set_pd(0., 1.);
12102        let r = _mm_mask_expand_pd(src, 0, a);
12103        assert_eq_m128d(r, src);
12104        let r = _mm_mask_expand_pd(src, 0b00000001, a);
12105        let e = _mm_set_pd(200., 1.);
12106        assert_eq_m128d(r, e);
12107    }
12108
12109    #[simd_test(enable = "avx512f,avx512vl")]
12110    unsafe fn test_mm_maskz_expand_pd() {
12111        let a = _mm_set_pd(0., 1.);
12112        let r = _mm_maskz_expand_pd(0, a);
12113        assert_eq_m128d(r, _mm_setzero_pd());
12114        let r = _mm_maskz_expand_pd(0b00000001, a);
12115        let e = _mm_set_pd(0., 1.);
12116        assert_eq_m128d(r, e);
12117    }
12118
12119    #[simd_test(enable = "avx512f")]
12120    unsafe fn test_mm512_loadu_epi64() {
12121        let a = &[4, 3, 2, 5, -8, -9, -64, -50];
12122        let p = a.as_ptr();
12123        let r = _mm512_loadu_epi64(black_box(p));
12124        let e = _mm512_setr_epi64(4, 3, 2, 5, -8, -9, -64, -50);
12125        assert_eq_m512i(r, e);
12126    }
12127
12128    #[simd_test(enable = "avx512f,avx512vl")]
12129    unsafe fn test_mm256_loadu_epi64() {
12130        let a = &[4, 3, 2, 5];
12131        let p = a.as_ptr();
12132        let r = _mm256_loadu_epi64(black_box(p));
12133        let e = _mm256_setr_epi64x(4, 3, 2, 5);
12134        assert_eq_m256i(r, e);
12135    }
12136
12137    #[simd_test(enable = "avx512f,avx512vl")]
12138    unsafe fn test_mm_loadu_epi64() {
12139        let a = &[4, 3];
12140        let p = a.as_ptr();
12141        let r = _mm_loadu_epi64(black_box(p));
12142        let e = _mm_setr_epi64x(4, 3);
12143        assert_eq_m128i(r, e);
12144    }
12145
12146    #[simd_test(enable = "avx512f")]
12147    unsafe fn test_mm512_mask_cvtepi64_storeu_epi16() {
12148        let a = _mm512_set1_epi64(9);
12149        let mut r = _mm_undefined_si128();
12150        _mm512_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i8, 0b11111111, a);
12151        let e = _mm_set1_epi16(9);
12152        assert_eq_m128i(r, e);
12153    }
12154
12155    #[simd_test(enable = "avx512f,avx512vl")]
12156    unsafe fn test_mm256_mask_cvtepi64_storeu_epi16() {
12157        let a = _mm256_set1_epi64x(9);
12158        let mut r = _mm_set1_epi16(0);
12159        _mm256_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i8, 0b11111111, a);
12160        let e = _mm_set_epi16(0, 0, 0, 0, 9, 9, 9, 9);
12161        assert_eq_m128i(r, e);
12162    }
12163
12164    #[simd_test(enable = "avx512f,avx512vl")]
12165    unsafe fn test_mm_mask_cvtepi64_storeu_epi16() {
12166        let a = _mm_set1_epi64x(9);
12167        let mut r = _mm_set1_epi16(0);
12168        _mm_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i8, 0b11111111, a);
12169        let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 9, 9);
12170        assert_eq_m128i(r, e);
12171    }
12172
12173    #[simd_test(enable = "avx512f")]
12174    unsafe fn test_mm512_mask_cvtsepi64_storeu_epi16() {
12175        let a = _mm512_set1_epi64(i64::MAX);
12176        let mut r = _mm_undefined_si128();
12177        _mm512_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i8, 0b11111111, a);
12178        let e = _mm_set1_epi16(i16::MAX);
12179        assert_eq_m128i(r, e);
12180    }
12181
12182    #[simd_test(enable = "avx512f,avx512vl")]
12183    unsafe fn test_mm256_mask_cvtsepi64_storeu_epi16() {
12184        let a = _mm256_set1_epi64x(i64::MAX);
12185        let mut r = _mm_set1_epi16(0);
12186        _mm256_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i8, 0b11111111, a);
12187        let e = _mm_set_epi16(0, 0, 0, 0, i16::MAX, i16::MAX, i16::MAX, i16::MAX);
12188        assert_eq_m128i(r, e);
12189    }
12190
12191    #[simd_test(enable = "avx512f,avx512vl")]
12192    unsafe fn test_mm_mask_cvtsepi64_storeu_epi16() {
12193        let a = _mm_set1_epi64x(i64::MAX);
12194        let mut r = _mm_set1_epi16(0);
12195        _mm_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i8, 0b11111111, a);
12196        let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, i16::MAX, i16::MAX);
12197        assert_eq_m128i(r, e);
12198    }
12199
12200    #[simd_test(enable = "avx512f")]
12201    unsafe fn test_mm512_mask_cvtusepi64_storeu_epi16() {
12202        let a = _mm512_set1_epi64(i64::MAX);
12203        let mut r = _mm_undefined_si128();
12204        _mm512_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i8, 0b11111111, a);
12205        let e = _mm_set1_epi16(u16::MAX as i16);
12206        assert_eq_m128i(r, e);
12207    }
12208
12209    #[simd_test(enable = "avx512f,avx512vl")]
12210    unsafe fn test_mm256_mask_cvtusepi64_storeu_epi16() {
12211        let a = _mm256_set1_epi64x(i64::MAX);
12212        let mut r = _mm_set1_epi16(0);
12213        _mm256_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i8, 0b11111111, a);
12214        let e = _mm_set_epi16(
12215            0,
12216            0,
12217            0,
12218            0,
12219            u16::MAX as i16,
12220            u16::MAX as i16,
12221            u16::MAX as i16,
12222            u16::MAX as i16,
12223        );
12224        assert_eq_m128i(r, e);
12225    }
12226
12227    #[simd_test(enable = "avx512f,avx512vl")]
12228    unsafe fn test_mm_mask_cvtusepi64_storeu_epi16() {
12229        let a = _mm_set1_epi64x(i64::MAX);
12230        let mut r = _mm_set1_epi16(0);
12231        _mm_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i8, 0b11111111, a);
12232        let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, u16::MAX as i16, u16::MAX as i16);
12233        assert_eq_m128i(r, e);
12234    }
12235
12236    #[simd_test(enable = "avx512f")]
12237    unsafe fn test_mm512_mask_cvtepi64_storeu_epi8() {
12238        let a = _mm512_set1_epi64(9);
12239        let mut r = _mm_set1_epi8(0);
12240        _mm512_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12241        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9, 9, 9, 9, 9);
12242        assert_eq_m128i(r, e);
12243    }
12244
12245    #[simd_test(enable = "avx512f,avx512vl")]
12246    unsafe fn test_mm256_mask_cvtepi64_storeu_epi8() {
12247        let a = _mm256_set1_epi64x(9);
12248        let mut r = _mm_set1_epi8(0);
12249        _mm256_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12250        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9);
12251        assert_eq_m128i(r, e);
12252    }
12253
12254    #[simd_test(enable = "avx512f,avx512vl")]
12255    unsafe fn test_mm_mask_cvtepi64_storeu_epi8() {
12256        let a = _mm_set1_epi64x(9);
12257        let mut r = _mm_set1_epi8(0);
12258        _mm_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12259        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9);
12260        assert_eq_m128i(r, e);
12261    }
12262
12263    #[simd_test(enable = "avx512f")]
12264    unsafe fn test_mm512_mask_cvtsepi64_storeu_epi8() {
12265        let a = _mm512_set1_epi64(i64::MAX);
12266        let mut r = _mm_set1_epi8(0);
12267        _mm512_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12268        #[rustfmt::skip]
12269        let e = _mm_set_epi8(
12270            0, 0, 0, 0,
12271            0, 0, 0, 0,
12272            i8::MAX, i8::MAX, i8::MAX, i8::MAX,
12273            i8::MAX, i8::MAX, i8::MAX, i8::MAX,
12274        );
12275        assert_eq_m128i(r, e);
12276    }
12277
12278    #[simd_test(enable = "avx512f,avx512vl")]
12279    unsafe fn test_mm256_mask_cvtsepi64_storeu_epi8() {
12280        let a = _mm256_set1_epi64x(i64::MAX);
12281        let mut r = _mm_set1_epi8(0);
12282        _mm256_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12283        #[rustfmt::skip]
12284        let e = _mm_set_epi8(
12285            0, 0, 0, 0,
12286            0, 0, 0, 0,
12287            0, 0, 0, 0,
12288            i8::MAX, i8::MAX, i8::MAX, i8::MAX,
12289        );
12290        assert_eq_m128i(r, e);
12291    }
12292
12293    #[simd_test(enable = "avx512f,avx512vl")]
12294    unsafe fn test_mm_mask_cvtsepi64_storeu_epi8() {
12295        let a = _mm_set1_epi64x(i64::MAX);
12296        let mut r = _mm_set1_epi8(0);
12297        _mm_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12298        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MAX, i8::MAX);
12299        assert_eq_m128i(r, e);
12300    }
12301
12302    #[simd_test(enable = "avx512f")]
12303    unsafe fn test_mm512_mask_cvtusepi64_storeu_epi8() {
12304        let a = _mm512_set1_epi64(i64::MAX);
12305        let mut r = _mm_set1_epi8(0);
12306        _mm512_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12307        #[rustfmt::skip]
12308        let e = _mm_set_epi8(
12309            0, 0, 0, 0,
12310            0, 0, 0, 0,
12311            u8::MAX as i8, u8::MAX as i8, u8::MAX as i8, u8::MAX as i8,
12312            u8::MAX as i8, u8::MAX as i8, u8::MAX as i8, u8::MAX as i8,
12313        );
12314        assert_eq_m128i(r, e);
12315    }
12316
12317    #[simd_test(enable = "avx512f,avx512vl")]
12318    unsafe fn test_mm256_mask_cvtusepi64_storeu_epi8() {
12319        let a = _mm256_set1_epi64x(i64::MAX);
12320        let mut r = _mm_set1_epi8(0);
12321        _mm256_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12322        #[rustfmt::skip]
12323        let e = _mm_set_epi8(
12324            0, 0, 0, 0,
12325            0, 0, 0, 0,
12326            0, 0, 0, 0,
12327            u8::MAX as i8, u8::MAX as i8, u8::MAX as i8, u8::MAX as i8,
12328        );
12329        assert_eq_m128i(r, e);
12330    }
12331
12332    #[simd_test(enable = "avx512f,avx512vl")]
12333    unsafe fn test_mm_mask_cvtusepi64_storeu_epi8() {
12334        let a = _mm_set1_epi64x(i64::MAX);
12335        let mut r = _mm_set1_epi8(0);
12336        _mm_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12337        #[rustfmt::skip]
12338        let e = _mm_set_epi8(
12339            0, 0, 0, 0,
12340            0, 0, 0, 0,
12341            0, 0, 0, 0,
12342            0, 0, u8::MAX as i8, u8::MAX as i8,
12343        );
12344        assert_eq_m128i(r, e);
12345    }
12346
12347    #[simd_test(enable = "avx512f")]
12348    unsafe fn test_mm512_mask_cvtepi64_storeu_epi32() {
12349        let a = _mm512_set1_epi64(9);
12350        let mut r = _mm256_undefined_si256();
12351        _mm512_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i8, 0b11111111, a);
12352        let e = _mm256_set1_epi32(9);
12353        assert_eq_m256i(r, e);
12354    }
12355
12356    #[simd_test(enable = "avx512f,avx512vl")]
12357    unsafe fn test_mm256_mask_cvtepi64_storeu_epi32() {
12358        let a = _mm256_set1_epi64x(9);
12359        let mut r = _mm_set1_epi32(0);
12360        _mm256_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i8, 0b11111111, a);
12361        let e = _mm_set_epi32(9, 9, 9, 9);
12362        assert_eq_m128i(r, e);
12363    }
12364
12365    #[simd_test(enable = "avx512f,avx512vl")]
12366    unsafe fn test_mm_mask_cvtepi64_storeu_epi32() {
12367        let a = _mm_set1_epi64x(9);
12368        let mut r = _mm_set1_epi16(0);
12369        _mm_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i8, 0b11111111, a);
12370        let e = _mm_set_epi32(0, 0, 9, 9);
12371        assert_eq_m128i(r, e);
12372    }
12373
12374    #[simd_test(enable = "avx512f")]
12375    unsafe fn test_mm512_mask_cvtsepi64_storeu_epi32() {
12376        let a = _mm512_set1_epi64(i64::MAX);
12377        let mut r = _mm256_undefined_si256();
12378        _mm512_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i8, 0b11111111, a);
12379        let e = _mm256_set1_epi32(i32::MAX);
12380        assert_eq_m256i(r, e);
12381    }
12382
12383    #[simd_test(enable = "avx512f,avx512vl")]
12384    unsafe fn test_mm256_mask_cvtsepi64_storeu_epi32() {
12385        let a = _mm256_set1_epi64x(i64::MAX);
12386        let mut r = _mm_set1_epi32(0);
12387        _mm256_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i8, 0b00001111, a);
12388        let e = _mm_set1_epi32(i32::MAX);
12389        assert_eq_m128i(r, e);
12390    }
12391
12392    #[simd_test(enable = "avx512f,avx512vl")]
12393    unsafe fn test_mm_mask_cvtsepi64_storeu_epi32() {
12394        let a = _mm_set1_epi64x(i64::MAX);
12395        let mut r = _mm_set1_epi16(0);
12396        _mm_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i8, 0b00000011, a);
12397        let e = _mm_set_epi32(0, 0, i32::MAX, i32::MAX);
12398        assert_eq_m128i(r, e);
12399    }
12400
12401    #[simd_test(enable = "avx512f")]
12402    unsafe fn test_mm512_mask_cvtusepi64_storeu_epi32() {
12403        let a = _mm512_set1_epi64(i64::MAX);
12404        let mut r = _mm256_undefined_si256();
12405        _mm512_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i8, 0b11111111, a);
12406        let e = _mm256_set1_epi32(u32::MAX as i32);
12407        assert_eq_m256i(r, e);
12408    }
12409
12410    #[simd_test(enable = "avx512f,avx512vl")]
12411    unsafe fn test_mm256_mask_cvtusepi64_storeu_epi32() {
12412        let a = _mm256_set1_epi64x(i64::MAX);
12413        let mut r = _mm_set1_epi32(0);
12414        _mm256_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i8, 0b00001111, a);
12415        let e = _mm_set1_epi32(u32::MAX as i32);
12416        assert_eq_m128i(r, e);
12417    }
12418
12419    #[simd_test(enable = "avx512f,avx512vl")]
12420    unsafe fn test_mm_mask_cvtusepi64_storeu_epi32() {
12421        let a = _mm_set1_epi64x(i64::MAX);
12422        let mut r = _mm_set1_epi16(0);
12423        _mm_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i8, 0b00000011, a);
12424        let e = _mm_set_epi32(0, 0, u32::MAX as i32, u32::MAX as i32);
12425        assert_eq_m128i(r, e);
12426    }
12427
12428    #[simd_test(enable = "avx512f")]
12429    unsafe fn test_mm512_storeu_epi64() {
12430        let a = _mm512_set1_epi64(9);
12431        let mut r = _mm512_set1_epi64(0);
12432        _mm512_storeu_epi64(&mut r as *mut _ as *mut i64, a);
12433        assert_eq_m512i(r, a);
12434    }
12435
12436    #[simd_test(enable = "avx512f,avx512vl")]
12437    unsafe fn test_mm256_storeu_epi64() {
12438        let a = _mm256_set1_epi64x(9);
12439        let mut r = _mm256_set1_epi64x(0);
12440        _mm256_storeu_epi64(&mut r as *mut _ as *mut i64, a);
12441        assert_eq_m256i(r, a);
12442    }
12443
12444    #[simd_test(enable = "avx512f,avx512vl")]
12445    unsafe fn test_mm_storeu_epi64() {
12446        let a = _mm_set1_epi64x(9);
12447        let mut r = _mm_set1_epi64x(0);
12448        _mm_storeu_epi64(&mut r as *mut _ as *mut i64, a);
12449        assert_eq_m128i(r, a);
12450    }
12451
12452    #[simd_test(enable = "avx512f")]
12453    unsafe fn test_mm512_load_epi64() {
12454        #[repr(align(64))]
12455        struct Align {
12456            data: [i64; 8], // 64 bytes
12457        }
12458        let a = Align {
12459            data: [4, 3, 2, 5, -8, -9, -64, -50],
12460        };
12461        let p = (a.data).as_ptr();
12462        let r = _mm512_load_epi64(black_box(p));
12463        let e = _mm512_setr_epi64(4, 3, 2, 5, -8, -9, -64, -50);
12464        assert_eq_m512i(r, e);
12465    }
12466
12467    #[simd_test(enable = "avx512f,avx512vl")]
12468    unsafe fn test_mm256_load_epi64() {
12469        #[repr(align(64))]
12470        struct Align {
12471            data: [i64; 4],
12472        }
12473        let a = Align { data: [4, 3, 2, 5] };
12474        let p = (a.data).as_ptr();
12475        let r = _mm256_load_epi64(black_box(p));
12476        let e = _mm256_set_epi64x(5, 2, 3, 4);
12477        assert_eq_m256i(r, e);
12478    }
12479
12480    #[simd_test(enable = "avx512f,avx512vl")]
12481    unsafe fn test_mm_load_epi64() {
12482        #[repr(align(64))]
12483        struct Align {
12484            data: [i64; 2],
12485        }
12486        let a = Align { data: [4, 3] };
12487        let p = (a.data).as_ptr();
12488        let r = _mm_load_epi64(black_box(p));
12489        let e = _mm_set_epi64x(3, 4);
12490        assert_eq_m128i(r, e);
12491    }
12492
12493    #[simd_test(enable = "avx512f")]
12494    unsafe fn test_mm512_store_epi64() {
12495        let a = _mm512_set1_epi64(9);
12496        let mut r = _mm512_set1_epi64(0);
12497        _mm512_store_epi64(&mut r as *mut _ as *mut i64, a);
12498        assert_eq_m512i(r, a);
12499    }
12500
12501    #[simd_test(enable = "avx512f,avx512vl")]
12502    unsafe fn test_mm256_store_epi64() {
12503        let a = _mm256_set1_epi64x(9);
12504        let mut r = _mm256_set1_epi64x(0);
12505        _mm256_store_epi64(&mut r as *mut _ as *mut i64, a);
12506        assert_eq_m256i(r, a);
12507    }
12508
12509    #[simd_test(enable = "avx512f,avx512vl")]
12510    unsafe fn test_mm_store_epi64() {
12511        let a = _mm_set1_epi64x(9);
12512        let mut r = _mm_set1_epi64x(0);
12513        _mm_store_epi64(&mut r as *mut _ as *mut i64, a);
12514        assert_eq_m128i(r, a);
12515    }
12516
12517    #[simd_test(enable = "avx512f")]
12518    unsafe fn test_mm512_load_pd() {
12519        #[repr(align(64))]
12520        struct Align {
12521            data: [f64; 8], // 64 bytes
12522        }
12523        let a = Align {
12524            data: [4., 3., 2., 5., -8., -9., -64., -50.],
12525        };
12526        let p = (a.data).as_ptr();
12527        let r = _mm512_load_pd(black_box(p));
12528        let e = _mm512_setr_pd(4., 3., 2., 5., -8., -9., -64., -50.);
12529        assert_eq_m512d(r, e);
12530    }
12531
12532    #[simd_test(enable = "avx512f")]
12533    unsafe fn test_mm512_store_pd() {
12534        let a = _mm512_set1_pd(9.);
12535        let mut r = _mm512_undefined_pd();
12536        _mm512_store_pd(&mut r as *mut _ as *mut f64, a);
12537        assert_eq_m512d(r, a);
12538    }
12539
12540    #[simd_test(enable = "avx512f")]
12541    unsafe fn test_mm512_test_epi64_mask() {
12542        let a = _mm512_set1_epi64(1 << 0);
12543        let b = _mm512_set1_epi64(1 << 0 | 1 << 1);
12544        let r = _mm512_test_epi64_mask(a, b);
12545        let e: __mmask8 = 0b11111111;
12546        assert_eq!(r, e);
12547    }
12548
12549    #[simd_test(enable = "avx512f")]
12550    unsafe fn test_mm512_mask_test_epi64_mask() {
12551        let a = _mm512_set1_epi64(1 << 0);
12552        let b = _mm512_set1_epi64(1 << 0 | 1 << 1);
12553        let r = _mm512_mask_test_epi64_mask(0, a, b);
12554        assert_eq!(r, 0);
12555        let r = _mm512_mask_test_epi64_mask(0b11111111, a, b);
12556        let e: __mmask8 = 0b11111111;
12557        assert_eq!(r, e);
12558    }
12559
12560    #[simd_test(enable = "avx512f,avx512vl")]
12561    unsafe fn test_mm256_test_epi64_mask() {
12562        let a = _mm256_set1_epi64x(1 << 0);
12563        let b = _mm256_set1_epi64x(1 << 0 | 1 << 1);
12564        let r = _mm256_test_epi64_mask(a, b);
12565        let e: __mmask8 = 0b00001111;
12566        assert_eq!(r, e);
12567    }
12568
12569    #[simd_test(enable = "avx512f,avx512vl")]
12570    unsafe fn test_mm256_mask_test_epi64_mask() {
12571        let a = _mm256_set1_epi64x(1 << 0);
12572        let b = _mm256_set1_epi64x(1 << 0 | 1 << 1);
12573        let r = _mm256_mask_test_epi64_mask(0, a, b);
12574        assert_eq!(r, 0);
12575        let r = _mm256_mask_test_epi64_mask(0b00001111, a, b);
12576        let e: __mmask8 = 0b00001111;
12577        assert_eq!(r, e);
12578    }
12579
12580    #[simd_test(enable = "avx512f,avx512vl")]
12581    unsafe fn test_mm_test_epi64_mask() {
12582        let a = _mm_set1_epi64x(1 << 0);
12583        let b = _mm_set1_epi64x(1 << 0 | 1 << 1);
12584        let r = _mm_test_epi64_mask(a, b);
12585        let e: __mmask8 = 0b00000011;
12586        assert_eq!(r, e);
12587    }
12588
12589    #[simd_test(enable = "avx512f,avx512vl")]
12590    unsafe fn test_mm_mask_test_epi64_mask() {
12591        let a = _mm_set1_epi64x(1 << 0);
12592        let b = _mm_set1_epi64x(1 << 0 | 1 << 1);
12593        let r = _mm_mask_test_epi64_mask(0, a, b);
12594        assert_eq!(r, 0);
12595        let r = _mm_mask_test_epi64_mask(0b00000011, a, b);
12596        let e: __mmask8 = 0b00000011;
12597        assert_eq!(r, e);
12598    }
12599
12600    #[simd_test(enable = "avx512f")]
12601    unsafe fn test_mm512_testn_epi64_mask() {
12602        let a = _mm512_set1_epi64(1 << 0);
12603        let b = _mm512_set1_epi64(1 << 0 | 1 << 1);
12604        let r = _mm512_testn_epi64_mask(a, b);
12605        let e: __mmask8 = 0b00000000;
12606        assert_eq!(r, e);
12607    }
12608
12609    #[simd_test(enable = "avx512f")]
12610    unsafe fn test_mm512_mask_testn_epi64_mask() {
12611        let a = _mm512_set1_epi64(1 << 0);
12612        let b = _mm512_set1_epi64(1 << 1);
12613        let r = _mm512_mask_testn_epi64_mask(0, a, b);
12614        assert_eq!(r, 0);
12615        let r = _mm512_mask_testn_epi64_mask(0b11111111, a, b);
12616        let e: __mmask8 = 0b11111111;
12617        assert_eq!(r, e);
12618    }
12619
12620    #[simd_test(enable = "avx512f,avx512vl")]
12621    unsafe fn test_mm256_testn_epi64_mask() {
12622        let a = _mm256_set1_epi64x(1 << 0);
12623        let b = _mm256_set1_epi64x(1 << 1);
12624        let r = _mm256_testn_epi64_mask(a, b);
12625        let e: __mmask8 = 0b00001111;
12626        assert_eq!(r, e);
12627    }
12628
12629    #[simd_test(enable = "avx512f,avx512vl")]
12630    unsafe fn test_mm256_mask_testn_epi64_mask() {
12631        let a = _mm256_set1_epi64x(1 << 0);
12632        let b = _mm256_set1_epi64x(1 << 1);
12633        let r = _mm256_mask_testn_epi64_mask(0, a, b);
12634        assert_eq!(r, 0);
12635        let r = _mm256_mask_testn_epi64_mask(0b11111111, a, b);
12636        let e: __mmask8 = 0b00001111;
12637        assert_eq!(r, e);
12638    }
12639
12640    #[simd_test(enable = "avx512f,avx512vl")]
12641    unsafe fn test_mm_testn_epi64_mask() {
12642        let a = _mm_set1_epi64x(1 << 0);
12643        let b = _mm_set1_epi64x(1 << 1);
12644        let r = _mm_testn_epi64_mask(a, b);
12645        let e: __mmask8 = 0b00000011;
12646        assert_eq!(r, e);
12647    }
12648
12649    #[simd_test(enable = "avx512f,avx512vl")]
12650    unsafe fn test_mm_mask_testn_epi64_mask() {
12651        let a = _mm_set1_epi64x(1 << 0);
12652        let b = _mm_set1_epi64x(1 << 1);
12653        let r = _mm_mask_testn_epi64_mask(0, a, b);
12654        assert_eq!(r, 0);
12655        let r = _mm_mask_testn_epi64_mask(0b11111111, a, b);
12656        let e: __mmask8 = 0b00000011;
12657        assert_eq!(r, e);
12658    }
12659
12660    #[simd_test(enable = "avx512f")]
12661    unsafe fn test_mm512_mask_set1_epi64() {
12662        let src = _mm512_set1_epi64(2);
12663        let a: i64 = 11;
12664        let r = _mm512_mask_set1_epi64(src, 0, a);
12665        assert_eq_m512i(r, src);
12666        let r = _mm512_mask_set1_epi64(src, 0b11111111, a);
12667        let e = _mm512_set1_epi64(11);
12668        assert_eq_m512i(r, e);
12669    }
12670
12671    #[simd_test(enable = "avx512f")]
12672    unsafe fn test_mm512_maskz_set1_epi64() {
12673        let a: i64 = 11;
12674        let r = _mm512_maskz_set1_epi64(0, a);
12675        assert_eq_m512i(r, _mm512_setzero_si512());
12676        let r = _mm512_maskz_set1_epi64(0b11111111, a);
12677        let e = _mm512_set1_epi64(11);
12678        assert_eq_m512i(r, e);
12679    }
12680
12681    #[simd_test(enable = "avx512f,avx512vl")]
12682    unsafe fn test_mm256_mask_set1_epi64() {
12683        let src = _mm256_set1_epi64x(2);
12684        let a: i64 = 11;
12685        let r = _mm256_mask_set1_epi64(src, 0, a);
12686        assert_eq_m256i(r, src);
12687        let r = _mm256_mask_set1_epi64(src, 0b00001111, a);
12688        let e = _mm256_set1_epi64x(11);
12689        assert_eq_m256i(r, e);
12690    }
12691
12692    #[simd_test(enable = "avx512f,avx512vl")]
12693    unsafe fn test_mm256_maskz_set1_epi64() {
12694        let a: i64 = 11;
12695        let r = _mm256_maskz_set1_epi64(0, a);
12696        assert_eq_m256i(r, _mm256_setzero_si256());
12697        let r = _mm256_maskz_set1_epi64(0b00001111, a);
12698        let e = _mm256_set1_epi64x(11);
12699        assert_eq_m256i(r, e);
12700    }
12701
12702    #[simd_test(enable = "avx512f,avx512vl")]
12703    unsafe fn test_mm_mask_set1_epi64() {
12704        let src = _mm_set1_epi64x(2);
12705        let a: i64 = 11;
12706        let r = _mm_mask_set1_epi64(src, 0, a);
12707        assert_eq_m128i(r, src);
12708        let r = _mm_mask_set1_epi64(src, 0b00000011, a);
12709        let e = _mm_set1_epi64x(11);
12710        assert_eq_m128i(r, e);
12711    }
12712
12713    #[simd_test(enable = "avx512f,avx512vl")]
12714    unsafe fn test_mm_maskz_set1_epi64() {
12715        let a: i64 = 11;
12716        let r = _mm_maskz_set1_epi64(0, a);
12717        assert_eq_m128i(r, _mm_setzero_si128());
12718        let r = _mm_maskz_set1_epi64(0b00000011, a);
12719        let e = _mm_set1_epi64x(11);
12720        assert_eq_m128i(r, e);
12721    }
12722
12723    #[simd_test(enable = "avx512f")]
12724    unsafe fn test_mm_cvtsd_i64() {
12725        let a = _mm_set_pd(1., -1.5);
12726        let r = _mm_cvtsd_i64(a);
12727        let e: i64 = -2;
12728        assert_eq!(r, e);
12729    }
12730
12731    #[simd_test(enable = "avx512f")]
12732    unsafe fn test_mm_cvtss_i64() {
12733        let a = _mm_set_ps(0., -0.5, 1., -1.5);
12734        let r = _mm_cvtss_i64(a);
12735        let e: i64 = -2;
12736        assert_eq!(r, e);
12737    }
12738
12739    #[simd_test(enable = "avx512f")]
12740    unsafe fn test_mm_cvt_roundi64_ss() {
12741        let a = _mm_set_ps(0., -0.5, 1., -1.5);
12742        let b: i64 = 9;
12743        let r = _mm_cvt_roundi64_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
12744        let e = _mm_set_ps(0., -0.5, 1., 9.);
12745        assert_eq_m128(r, e);
12746    }
12747
12748    #[simd_test(enable = "avx512f")]
12749    unsafe fn test_mm_cvt_roundsi64_ss() {
12750        let a = _mm_set_ps(0., -0.5, 1., -1.5);
12751        let b: i64 = 9;
12752        let r = _mm_cvt_roundsi64_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
12753        let e = _mm_set_ps(0., -0.5, 1., 9.);
12754        assert_eq_m128(r, e);
12755    }
12756
12757    #[simd_test(enable = "avx512f")]
12758    unsafe fn test_mm_cvti64_ss() {
12759        let a = _mm_set_ps(0., -0.5, 1., -1.5);
12760        let b: i64 = 9;
12761        let r = _mm_cvti64_ss(a, b);
12762        let e = _mm_set_ps(0., -0.5, 1., 9.);
12763        assert_eq_m128(r, e);
12764    }
12765
12766    #[simd_test(enable = "avx512f")]
12767    unsafe fn test_mm_cvti64_sd() {
12768        let a = _mm_set_pd(1., -1.5);
12769        let b: i64 = 9;
12770        let r = _mm_cvti64_sd(a, b);
12771        let e = _mm_set_pd(1., 9.);
12772        assert_eq_m128d(r, e);
12773    }
12774
12775    #[simd_test(enable = "avx512f")]
12776    unsafe fn test_mm_cvt_roundsd_si64() {
12777        let a = _mm_set_pd(1., -1.5);
12778        let r = _mm_cvt_roundsd_si64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12779        let e: i64 = -1;
12780        assert_eq!(r, e);
12781    }
12782
12783    #[simd_test(enable = "avx512f")]
12784    unsafe fn test_mm_cvt_roundsd_i64() {
12785        let a = _mm_set_pd(1., -1.5);
12786        let r = _mm_cvt_roundsd_i64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12787        let e: i64 = -1;
12788        assert_eq!(r, e);
12789    }
12790
12791    #[simd_test(enable = "avx512f")]
12792    unsafe fn test_mm_cvt_roundsd_u64() {
12793        let a = _mm_set_pd(1., f64::MAX);
12794        let r = _mm_cvt_roundsd_u64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12795        let e: u64 = u64::MAX;
12796        assert_eq!(r, e);
12797    }
12798
12799    #[simd_test(enable = "avx512f")]
12800    unsafe fn test_mm_cvtsd_u64() {
12801        let a = _mm_set_pd(1., -1.5);
12802        let r = _mm_cvtsd_u64(a);
12803        let e: u64 = u64::MAX;
12804        assert_eq!(r, e);
12805    }
12806
12807    #[simd_test(enable = "avx512f")]
12808    unsafe fn test_mm_cvt_roundss_i64() {
12809        let a = _mm_set_ps(0., -0.5, 1., -1.5);
12810        let r = _mm_cvt_roundss_i64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12811        let e: i64 = -1;
12812        assert_eq!(r, e);
12813    }
12814
12815    #[simd_test(enable = "avx512f")]
12816    unsafe fn test_mm_cvt_roundss_si64() {
12817        let a = _mm_set_ps(0., -0.5, 1., -1.5);
12818        let r = _mm_cvt_roundss_si64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12819        let e: i64 = -1;
12820        assert_eq!(r, e);
12821    }
12822
12823    #[simd_test(enable = "avx512f")]
12824    unsafe fn test_mm_cvt_roundss_u64() {
12825        let a = _mm_set_ps(0., -0.5, 1., -1.5);
12826        let r = _mm_cvt_roundss_u64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12827        let e: u64 = u64::MAX;
12828        assert_eq!(r, e);
12829    }
12830
12831    #[simd_test(enable = "avx512f")]
12832    unsafe fn test_mm_cvtss_u64() {
12833        let a = _mm_set_ps(0., -0.5, 1., -1.5);
12834        let r = _mm_cvtss_u64(a);
12835        let e: u64 = u64::MAX;
12836        assert_eq!(r, e);
12837    }
12838
12839    #[simd_test(enable = "avx512f")]
12840    unsafe fn test_mm_cvttsd_i64() {
12841        let a = _mm_set_pd(1., -1.5);
12842        let r = _mm_cvttsd_i64(a);
12843        let e: i64 = -1;
12844        assert_eq!(r, e);
12845    }
12846
12847    #[simd_test(enable = "avx512f")]
12848    unsafe fn test_mm_cvtt_roundsd_i64() {
12849        let a = _mm_set_pd(1., -1.5);
12850        let r = _mm_cvtt_roundsd_i64::<_MM_FROUND_NO_EXC>(a);
12851        let e: i64 = -1;
12852        assert_eq!(r, e);
12853    }
12854
12855    #[simd_test(enable = "avx512f")]
12856    unsafe fn test_mm_cvtt_roundsd_si64() {
12857        let a = _mm_set_pd(1., -1.5);
12858        let r = _mm_cvtt_roundsd_si64::<_MM_FROUND_NO_EXC>(a);
12859        let e: i64 = -1;
12860        assert_eq!(r, e);
12861    }
12862
12863    #[simd_test(enable = "avx512f")]
12864    unsafe fn test_mm_cvtt_roundsd_u64() {
12865        let a = _mm_set_pd(1., -1.5);
12866        let r = _mm_cvtt_roundsd_u64::<_MM_FROUND_NO_EXC>(a);
12867        let e: u64 = u64::MAX;
12868        assert_eq!(r, e);
12869    }
12870
12871    #[simd_test(enable = "avx512f")]
12872    unsafe fn test_mm_cvttsd_u64() {
12873        let a = _mm_set_pd(1., -1.5);
12874        let r = _mm_cvttsd_u64(a);
12875        let e: u64 = u64::MAX;
12876        assert_eq!(r, e);
12877    }
12878
12879    #[simd_test(enable = "avx512f")]
12880    unsafe fn test_mm_cvttss_i64() {
12881        let a = _mm_set_ps(0., -0.5, 1., -1.5);
12882        let r = _mm_cvttss_i64(a);
12883        let e: i64 = -1;
12884        assert_eq!(r, e);
12885    }
12886
12887    #[simd_test(enable = "avx512f")]
12888    unsafe fn test_mm_cvtt_roundss_i64() {
12889        let a = _mm_set_ps(0., -0.5, 1., -1.5);
12890        let r = _mm_cvtt_roundss_i64::<_MM_FROUND_NO_EXC>(a);
12891        let e: i64 = -1;
12892        assert_eq!(r, e);
12893    }
12894
12895    #[simd_test(enable = "avx512f")]
12896    unsafe fn test_mm_cvtt_roundss_si64() {
12897        let a = _mm_set_ps(0., -0.5, 1., -1.5);
12898        let r = _mm_cvtt_roundss_si64::<_MM_FROUND_NO_EXC>(a);
12899        let e: i64 = -1;
12900        assert_eq!(r, e);
12901    }
12902
12903    #[simd_test(enable = "avx512f")]
12904    unsafe fn test_mm_cvtt_roundss_u64() {
12905        let a = _mm_set_ps(0., -0.5, 1., -1.5);
12906        let r = _mm_cvtt_roundss_u64::<_MM_FROUND_NO_EXC>(a);
12907        let e: u64 = u64::MAX;
12908        assert_eq!(r, e);
12909    }
12910
12911    #[simd_test(enable = "avx512f")]
12912    unsafe fn test_mm_cvttss_u64() {
12913        let a = _mm_set_ps(0., -0.5, 1., -1.5);
12914        let r = _mm_cvttss_u64(a);
12915        let e: u64 = u64::MAX;
12916        assert_eq!(r, e);
12917    }
12918
12919    #[simd_test(enable = "avx512f")]
12920    unsafe fn test_mm_cvtu64_ss() {
12921        let a = _mm_set_ps(0., -0.5, 1., -1.5);
12922        let b: u64 = 9;
12923        let r = _mm_cvtu64_ss(a, b);
12924        let e = _mm_set_ps(0., -0.5, 1., 9.);
12925        assert_eq_m128(r, e);
12926    }
12927
12928    #[simd_test(enable = "avx512f")]
12929    unsafe fn test_mm_cvtu64_sd() {
12930        let a = _mm_set_pd(1., -1.5);
12931        let b: u64 = 9;
12932        let r = _mm_cvtu64_sd(a, b);
12933        let e = _mm_set_pd(1., 9.);
12934        assert_eq_m128d(r, e);
12935    }
12936
12937    #[simd_test(enable = "avx512f")]
12938    unsafe fn test_mm_cvt_roundu64_ss() {
12939        let a = _mm_set_ps(0., -0.5, 1., -1.5);
12940        let b: u64 = 9;
12941        let r = _mm_cvt_roundu64_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
12942        let e = _mm_set_ps(0., -0.5, 1., 9.);
12943        assert_eq_m128(r, e);
12944    }
12945
12946    #[simd_test(enable = "avx512f")]
12947    unsafe fn test_mm_cvt_roundu64_sd() {
12948        let a = _mm_set_pd(1., -1.5);
12949        let b: u64 = 9;
12950        let r = _mm_cvt_roundu64_sd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
12951        let e = _mm_set_pd(1., 9.);
12952        assert_eq_m128d(r, e);
12953    }
12954
12955    #[simd_test(enable = "avx512f")]
12956    unsafe fn test_mm_cvt_roundi64_sd() {
12957        let a = _mm_set_pd(1., -1.5);
12958        let b: i64 = 9;
12959        let r = _mm_cvt_roundi64_sd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
12960        let e = _mm_set_pd(1., 9.);
12961        assert_eq_m128d(r, e);
12962    }
12963
12964    #[simd_test(enable = "avx512f")]
12965    unsafe fn test_mm_cvt_roundsi64_sd() {
12966        let a = _mm_set_pd(1., -1.5);
12967        let b: i64 = 9;
12968        let r = _mm_cvt_roundsi64_sd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
12969        let e = _mm_set_pd(1., 9.);
12970        assert_eq_m128d(r, e);
12971    }
12972}